CN113611713A - Array substrate and display panel - Google Patents
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- CN113611713A CN113611713A CN202110872576.7A CN202110872576A CN113611713A CN 113611713 A CN113611713 A CN 113611713A CN 202110872576 A CN202110872576 A CN 202110872576A CN 113611713 A CN113611713 A CN 113611713A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Abstract
The application discloses array substrate and display panel belongs to and shows technical field. The array substrate includes: a base substrate and a drive circuit. The array substrate is provided with a display area and an opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece. The at least one target thin film transistor corresponds to the at least one target conductive blocking piece one to one. The at least one target conductive blocking piece is electrically connected with the at least one target constant voltage signal line. Through setting up the electrically conductive dog that hides of target constant voltage signal line and the target of being connected with the electrically connected of target constant voltage signal line to shelter from the active layer with the adjacent target thin film transistor in trompil district by the electrically conductive dog of target, so alright make this target thin film transistor's performance comparatively stable, solved the relatively poor problem of stability of the adjacent thin film transistor in trompil district edge among the correlation technique, realized improving the effect of the stability of the adjacent thin film transistor in trompil district edge.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
At present, various intelligent terminals such as mobile phones, tablet computers and intelligent wearable devices are all provided with display panels, and the display panels are widely applied. An Active Matrix Organic Light Emitting Diode (AMOLED) display panel generally includes a driving circuit for driving light emitting elements to emit light. In order to make the occupation ratio of the display area of the display panel large, the occupation ratio of the non-display area is small. Set up the trompil district on display panel and set up parts such as camera and earphone in the trompil district, so can save the area occupied that the frame position corresponds the non-display area greatly, be favorable to the design of narrow frame more.
In the related art, a frame of an opening region of an array substrate is narrow, and a dummy pixel driving circuit disposed around the opening region is removed, so that a ratio of a display region is larger.
In the array substrate, due to external illumination, the stability of the thin film transistor adjacent to the edge of the opening region is poor.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel. The technical scheme is as follows:
according to a first aspect of the present application, there is provided an array substrate including: the drive circuit comprises a substrate base plate and a drive circuit positioned on the substrate base plate;
the array substrate is provided with a display area and an opening area, the display area at least partially surrounds the opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece which are positioned in the display area;
the plurality of thin film transistors comprise at least one target thin film transistor, the at least one target thin film transistor corresponds to the at least one target conductive shielding block in a one-to-one mode, and the target thin film transistor comprises at least one thin film transistor which is adjacent to the opening area in the plurality of thin film transistors;
many constant voltage signal lines include an at least target constant voltage signal line section, the electrically conductive stop dog of at least one target in the electrically conductive stop dog of a plurality of targets with at least one the electrically connected of target constant voltage signal line section, the electrically conductive stop dog of at least one target is located corresponding target thin film transistor and keeps away from one side of substrate base plate, the electrically conductive stop dog of at least one target is in orthographic projection on the substrate base plate is in with the active layer of the target thin film transistor that corresponds orthographic projection on the substrate base plate exists the overlap.
Optionally, the at least one target constant voltage signal line segment is located on a target side of the target thin film transistor, and the target thin film transistor is a thin film transistor whose target side is adjacent to the opening region.
Optionally, the number of the target thin film transistors is multiple, the multiple target thin film transistors are arranged in multiple rows on the substrate, and at least one row of the multiple rows of the target thin film transistors includes at least two target thin film transistors;
the number of the target constant voltage signal line segments is multiple, the multiple target constant voltage signal line segments correspond to multiple columns of the target thin film transistors one to one, and the target conductive blocking blocks corresponding to at least two target thin film transistors of at least one column of the target thin film transistors are electrically connected with the target constant voltage signal line segments corresponding to at least one column of the target thin film transistors.
Alternatively, the at least one column of target constant voltage signal line segments is electrically connected to at least other constant voltage signal lines in the driving circuit except for the at least one target constant voltage signal line segment.
Alternatively, a plurality of the target constant voltage signal line segments are all electrically connected.
Optionally, a plurality of the target constant voltage signal line segments are located outside the first region of the open region;
the opening area is divided into the first area and the second area by a first straight line, and the first straight line passes through the center of the opening area and is parallel to the arrangement direction of the at least one row of target thin film transistors.
Optionally, the open region is circular, and the first line passes through a center of the open region.
Optionally, the array substrate further includes a source drain metal layer, and the at least one target constant voltage signal line segment is located in the source drain metal layer.
Optionally, the array substrate further includes a dielectric layer, the target conductive blocking piece and the target constant voltage signal line segment are respectively located on two sides of the dielectric layer in a direction perpendicular to the substrate, at least one of the target conductive blocking piece and at least one of the target constant voltage signal line segments are electrically connected through a via hole, and the via hole penetrates through the dielectric layer.
Optionally, the target thin film transistor is a double-gate thin film transistor, the double-gate thin film transistor includes two gate electrodes, and an orthographic projection of the target conductive blocking block on the substrate base plate overlaps with an orthographic projection of a channel region between the two gate electrodes on the substrate base plate.
Optionally, the target constant voltage signal line segment includes a constant voltage power supply line.
According to another aspect of the present application, there is provided a display panel including the array substrate of any one of the above.
Optionally, the display panel further includes a plurality of light emitting units on the array substrate, the array substrate includes a driving circuit, the driving circuit includes a plurality of pixel circuits, and at least one of the pixel circuits is electrically connected to at least one of the light emitting units.
The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:
an array substrate including a substrate base and a driving circuit on the substrate base is provided. The array substrate is provided with a display area and an opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece. The at least one target thin film transistor corresponds to the at least one target conductive blocking piece one to one. At least one target conductive blocking piece of the plurality of target conductive blocking pieces is electrically connected with at least one target constant voltage signal line. Through setting up the electrically conductive dog that hides of target constant voltage signal line and the target of being connected with the electrically connected of target constant voltage signal line to shelter from the active layer with the adjacent target thin film transistor in trompil district by the electrically conductive dog of target, so alright make this target thin film transistor's performance comparatively stable, solved the relatively poor problem of stability of the adjacent thin film transistor in trompil district edge among the correlation technique, realized improving the effect of the stability of the adjacent thin film transistor in trompil district edge.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an array substrate;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic partial structure diagram of the array substrate shown in FIG. 1;
fig. 4 is a schematic structural diagram of another array substrate provided in the present embodiment;
fig. 5 is a schematic structural diagram of another array substrate provided in the present embodiment;
fig. 6 is a schematic structural diagram of another array substrate provided in the present embodiment;
fig. 7 is a schematic cross-sectional structure diagram of another array substrate provided in the embodiments of the present application;
fig. 8 is a schematic structural diagram of various layers of a driving circuit according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of another driving circuit provided in an embodiment of the present application;
fig. 10 is a circuit schematic diagram of a driving circuit according to an embodiment of the present application;
fig. 11 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
As shown in fig. 1, fig. 1 is a schematic structural diagram of an array substrate. The array substrate 101 includes a substrate 1011 and a driving circuit 1012 on the substrate 1011. The array substrate 101 has a display region 1013 and an opening region 1014, wherein the display region 1013 at least partially surrounds the opening region 1014. The array substrate can also be used for quantum dot display and the like.
The driver circuit 1012 has a plurality of pixel circuits each including a plurality of thin film transistors and a constant voltage power source signal line. The active layer of at least one thin film transistor in the plurality of thin film transistors is not completely shielded by the grid, and if the active layer is exposed, the active layer is easily influenced by light and is unstable.
In this regard, the driving circuit includes at least one conductive blocking block corresponding to the exposed active layer of the at least one thin film transistor to block the active layer of the at least one thin film transistor. And the conductive shielding block is electrically connected with a power signal wire of the adjacent pixel circuit, so that the voltage of the conductive shielding block is constant, and the potential influence of the voltage change of the conductive shielding block on the exposed active layer can be avoided.
The array substrate 101 may further have a non-display region 1015 surrounding a periphery of the opening region 1014, and the driving circuit 1012 may further include a dummy pixel driving circuit. The dummy pixel driving circuit provided in the non-display area 1015 has the same structure as the pixel circuit, but does not perform image display, and can be used to supply a constant voltage power supply to the conductive block in the pixel circuit adjacent to the non-display area in the display area. However, the non-display region 1015 makes the rim of the opening region 1014 wider. At the same time, the screen occupation ratio of the display area 1011 is also reduced. In order to make the frame of the opening 1014 narrower and to increase the screen area of the display 1011, the dummy pixel driving circuit may be eliminated.
However, when the dummy pixel driving circuit is removed, one side of a portion of the pixel circuit loses the neighboring dummy pixel driving circuit, i.e., a portion of the conductive shielding block disposed along the edge of the opening area 1014 loses the power signal line that can be electrically connected thereto. The portion of the conductive block mask is removed along with the dummy pixel driving circuit. However, this in turn makes the exposed active layer of a portion of the thin film transistor in the driving circuit 1012 adjacent to the opening region 1014 susceptible to light and less stable.
The embodiment of the application provides an array substrate and a display panel, which can solve the problems existing in the related art.
Fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure. As shown in fig. 2, the array substrate 10 may include: a base substrate 11, and a drive circuit 12 on the base substrate 11.
The array substrate 10 may have a display Area 13 and an opening Area 131, wherein the display Area 13 at least partially surrounds the opening Area 131. The opening area 131 can be used for placing a camera, an earphone and the like.
As shown in fig. 3, fig. 3 is a schematic structural diagram of a portion 10A of the array substrate shown in fig. 2. The driving circuit may include a plurality of thin film transistors 121, a plurality of constant voltage signal lines 122, and at least one target conductive blocking piece 123 in the display region. The target conductive block 123 may be used to block light.
The plurality of thin film transistors 121 include at least one target thin film transistor 1211, and the at least one target thin film transistor 1211 corresponds to the at least one target conductive blocking piece 123 one to one. The one-to-one correspondence may mean that one target thin film transistor 1211 corresponds to one target conductive blocking piece 123, and the number of the target thin film transistors 1211 may be identical to the number of the target conductive blocking pieces 123.
The target thin film transistor 1211 includes at least one thin film transistor adjacent to the opening region 131 among the plurality of thin film transistors 121. The adjacent to the opening region 131 may mean that no other tft is disposed between the target tft 1211 and the opening region 131.
The plurality of constant voltage signal lines 122 includes at least one target constant voltage signal line segment 1221, and at least one target conductive blocking piece 123 of the plurality of target conductive blocking pieces 123 is electrically connected to the at least one target constant voltage signal line segment 1221.
The at least one target conductive block 123 is located on a side of the corresponding target thin film transistor 1211 away from the substrate 11, and an orthogonal projection of the at least one target conductive block 123 on the substrate overlaps with an orthogonal projection of the active layer of the corresponding target thin film transistor 1211 on the substrate 11. The active layer of the target thin film transistor 1211 is relatively susceptible to light, making it less stable.
In this manner, the target conductive block 123 may prevent external light from being irradiated onto the active layer of the corresponding target thin film transistor 1211, thereby improving stability of the active layer of the target thin film transistor 1211.
In addition, the at least one target conductive blocking piece 123 is electrically connected to the at least one target constant voltage signal line 1221, and a constant voltage electrical signal is also applied to the target conductive blocking piece 123, so that the target conductive blocking piece 123 can effectively shield an external electric field from interfering with an active layer of the corresponding target thin film transistor 1211, thereby preventing the electrical characteristics of the active layer of the corresponding target thin film transistor 1211 from being unstable.
In summary, the embodiment of the present application provides an array substrate including a substrate base plate and a driving circuit on the substrate base plate. The array substrate is provided with a display area and an opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece. The at least one target thin film transistor corresponds to the at least one target conductive blocking piece one to one. At least one target conductive blocking piece of the plurality of target conductive blocking pieces is electrically connected with at least one target constant voltage signal line. Through setting up the electrically conductive dog that hides of target constant voltage signal line and the target of being connected with the electrically connected of target constant voltage signal line to shelter from the active layer with the adjacent target thin film transistor in trompil district by the electrically conductive dog of target, so alright make this target thin film transistor's performance comparatively stable, solved the relatively poor problem of stability of the adjacent thin film transistor in trompil district edge among the correlation technique, realized improving the effect of the stability of the adjacent thin film transistor in trompil district edge.
Further, please refer to fig. 4, fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure. The target thin film transistor 1211 is a thin film transistor having a target side B1 adjacent to the opening region 131, and the target constant voltage signal line segment 1221 is located on a target side B1 of the target thin film transistor 1211. The target constant voltage signal line segment 1221 may be positioned only on one side of the target thin film transistor 1211, and at least one target constant voltage signal line segment 1221 is positioned between the target thin film transistor 1211 and the open region 131.
Alternatively, as shown in fig. 4, the number of the target thin film transistors 1211 is plural. The plurality of target thin film transistors 1211 may be arranged in a plurality of columns on the substrate base plate 11. That is, a plurality of target thin film transistors 1211 may be arranged on the substrate base plate 11 in a column direction in the f1 direction. The plural columns of target thin film transistors 1211 may be arranged in the direction f 2. f1 and f2 intersect. Thus, the opening region 131 may be circular, so that a plurality of target tfts 1211 may be disposed along the edge of the opening region 131 without changing the original arrangement of the tfts in the array substrate.
At least one of the plurality of rows of target thin film transistors 1211 may include at least two target thin film transistors 1211. The plurality of columns of target thin film transistors 1211 may be arranged in a zigzag shape along the edge of the open region such that the plurality of columns of target thin film transistors 1211 conforms to the shape of the open region 131 as much as possible.
The number of the target constant voltage signal line segments 1221 is plural, and the plural target constant voltage signal line segments 1221 correspond to the plural rows of the target thin film transistors 1211 one to one. A plurality of target constant voltage signal line segments 1221 may be arranged outside the edges of the open area 131.
The target conductive blocking pieces 123 corresponding to at least two target thin film transistors 1211 of the at least one row of target thin film transistors 1211 are electrically connected to the target constant voltage signal line segments 1221 corresponding to the at least one row of target thin film transistors 1211.
In this way, a plurality of target constant voltage signal line segments corresponding one to one can be provided only on the target side of the plurality of columns of target thin film transistors. The occupied area of the constant voltage signal line on the substrate board can be further reduced. So that the borders of the open area can be further reduced. And the target conductive shielding block can stabilize the performance of the active layer of the target thin film transistor, so that the stability of the target thin film transistor adjacent to the opening area on the array substrate can be improved, and the display effect of the display panel adjacent to the opening area can be improved.
Alternatively, as shown in fig. 4, at least one target constant voltage signal line segment 1221 is electrically connected to at least the other constant voltage signal lines 1222 than the at least one target constant voltage signal line segment 1221 in the driving circuit. So that the constant voltage signal can be loaded on the at least one target constant voltage signal line segment 1221.
In this embodiment, the target constant voltage signal line segment 1221 is a line for electrically connecting to the target conductive shielding block to stabilize the voltage of the target conductive shielding block. And the other constant voltage signal line 1222 in the array substrate may refer to a constant voltage signal line in the driving circuit that is not directly connected to the target conductive blocking block. Other constant voltage signal lines may be arranged in a plurality of rows on the array substrate.
For example, the target constant voltage signal line segments in the embodiment of the present application may include two types, and as shown in fig. 4, one type of the target constant voltage signal line segment may be a first target constant voltage signal line segment 1211A, and the first target constant voltage signal line segment 1211A may extend along the direction f1 (the direction f1 may be parallel to the arrangement direction of at least one row of the target thin film transistors 1211), and may be a straight line segment. The first target constant voltage signal line segment 1211A may be electrically connected to other constant voltage signal lines of the same column.
Alternatively, the at least one target constant voltage signal line segment is a second target constant voltage signal line segment 1211B, and the second target constant voltage signal line segment 1211B includes a first line segment s1 extending in the f1 direction, and a second line segment s2 extending in the f2 direction (e.g., the f2 direction may be perpendicular to the f1 direction). The first line segment s1 and the second line segment s2 are connected. The first line segment s1 may be electrically connected to other constant voltage signal lines 1222 of the same column, and the second line segment s2 may be electrically connected to other constant voltage signal lines 1222 of other columns.
Among them, the other constant voltage signal line 1222 may extend in the f1 direction. The other signal line 1223 extending in the f2 direction in fig. 4 may include a gate line or a reference signal line.
In an alternative example, as shown in fig. 5, fig. 5 is a schematic structural diagram of another array substrate provided in this embodiment of the present application. The plurality of target constant voltage signal line segments 1221 are electrically connected to each other. The plurality of target constant voltage signal line segments 1221 may be regarded as one target constant voltage signal line segment 1221, and thus, the process of the target constant voltage signal line segment 1221 in the manufacturing process of the array substrate may be simplified. All the target thin film transistors in the array substrate may be connected through one target constant voltage signal line segment 1221.
The first end C1 of the one target constant voltage signal line segment 1221 may be electrically connected to at least one other constant voltage signal line 1222 in the driving circuit 12, and the second end C2 of the one target constant voltage signal line segment 1221 may be electrically connected to at least one other constant voltage signal line 1222 in the driving circuit 12.
In an alternative implementation manner, as shown in fig. 6, fig. 6 is a schematic structural diagram of another array substrate provided in the embodiment of the present application. The opening region 131 is partitioned into a first region 1311 and a second region 1312 by a first straight line L1. The plurality of target constant voltage signal line segments 1221 are located outside the first region 1311 of the open region 131. That is, the plurality of target constant voltage signal line segments 1221 do not overlap with the orthographic projection of the first region 1311 of the open region 131 on the substrate 11. And a plurality of target constant voltage signal line segments 1221 are located outside the first region and 1311 away from the second region 1312. In this way, the target constant voltage signal line can be provided only outside the first region of the opening region. The occupied area of the constant voltage signal line on the substrate board can be reduced. So that the borders of the open area can be further reduced.
The first straight line L1 passes through the center C1 of the opening 131 and is parallel to the arrangement direction of at least one row of target tfts 1211. The arrangement direction of at least the column target thin film transistors 1211 may be parallel to the first direction f 1.
Note that the parallelism may not be strictly parallel, and the arrangement direction of at least one row of the target thin film transistors 1211 may include a case where an angle between the arrangement direction and the first direction f1 is 10 degrees or less. Further, the opening region 131 may have a circular shape, and the first straight line L1 passes through a center C1 of the opening region 131. It should be noted that the opening region 131 may also be rectangular, square, hexagonal, etc., and the embodiments of the present application are not limited herein.
In an alternative example, as shown in fig. 7, fig. 7 is a schematic cross-sectional structure diagram of another array substrate provided in this application. The array substrate further includes a source/drain (source/drain; SD) metal layer, and the at least one target constant voltage signal line segment 1221 may be located on the source/drain metal layer. At least one target constant voltage signal line segment 1221 and a source-drain metal pattern in the source-drain metal layer can be formed through a one-time composition process, and therefore manufacturing procedures of the array substrate can be saved.
Optionally, as shown in fig. 7, the array substrate further includes a Dielectric Layer (ILD) 15, the target conductive block 123 and the target constant voltage signal line segment 1221 are respectively located at two sides of the Dielectric Layer 15 in a direction perpendicular to the substrate, at least one target conductive block 123 and at least one target constant voltage signal line segment 1221 may be electrically connected through a via 151, and the via 151 may penetrate through the Dielectric Layer 15.
In an exemplary implementation manner, as shown in fig. 8, fig. 8 is a schematic structural diagram of each film layer of a driving circuit provided in an embodiment of the present application. The driving circuit may include the active layer pattern 21. The first conductive pattern 22, the first conductive pattern 22 may include a first plate 221 of the capacitor structure, the gate line 111, and the gate electrode. The second conductive pattern 23, the second conductive pattern 23 may include a second plate 231 of the capacitor structure and a target conductive block piece 123. And the dielectric layer 15 is provided with a via hole 151 on the dielectric layer 15. The third conductive pattern 24, the third conductive pattern 24 may include a target constant voltage signal line segment 1221, a node connection line 119, a source electrode, and a drain electrode. The fourth conductive pattern 25, the fourth conductive pattern 25 may include a data signal line 112.
In an alternative implementation manner, as shown in fig. 9, fig. 9 is a schematic structural diagram of another driving circuit provided in an embodiment of the present application. The driving circuit may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and a capacitive structure Cst 1.
The first thin film transistor T1 may be a first initial thin film transistor, the second thin film transistor T2 may be a compensation thin film transistor, the third thin film transistor T3 may be a driving thin film transistor, the fourth thin film transistor T4 may be a data writing transistor, the fifth thin film transistor T5 may be an operation control thin film transistor, the sixth thin film transistor T6 may be an emission control thin film transistor, and the seventh thin film transistor T7 may be a second initial thin film transistor. The T1-T7 may include Low Temperature polysilicon thin film transistors (LTPS) and/or oxide thin film transistors (O-TFT). The T1-T7 may also be other types of thin film transistors, and the embodiments of the present application are not limited herein.
The target thin film transistor may be a double gate thin film transistor, which may correspond to the compensating thin film transistor T2 in fig. 9. A double gate transistor refers to a transistor comprising two switching tubes in series. As shown in fig. 9, the double-gate thin film transistor T2 includes two gates (T21 and T22), and an orthographic projection of the target conductive stopper 123 on the substrate overlaps with an orthographic projection of the channel region T23 between the two gates (T21 and T22) on the substrate. The channel region T23 between the two gates (T21 and T22) may be L-shaped. The channel region T23 may refer to a channel region T23 which is not covered by the two gates (T21 and T22) in the active layer of the double-gate thin film transistor T2, that is, an orthogonal projection of the channel region T23 on the substrate does not overlap an orthogonal projection of the two gates (T21 and T22) on the substrate.
As shown in fig. 10, fig. 10 is a circuit schematic diagram of a driving circuit according to an embodiment of the present application. A gate of the third thin film transistor T3 is connected to the first node N1, a source of the third thin film transistor T3 is connected to the second node N2, and a drain of the third thin film transistor T3 is connected to the third node N3.
A Gate electrode of the fourth thin film transistor T4 is connected to the Gate line (Gate)111, a source electrode of the fourth thin film transistor T4 is connected to the Data signal line (Data)112, and a drain electrode of the fourth thin film transistor T4 is connected to the second node N2.
A gate electrode of the second thin film transistor T2 is connected to the gate line 111, a source electrode of the second thin film transistor T2 is connected to the third node N3, and a drain electrode of the second thin film transistor T2 is connected to the first node N1.
The gate of the first thin film transistor T1 is connected to the Reset signal line (Reset)113, the drain of the first thin film transistor T1 is connected to the first reference signal line (Vinit)114-1, and the source of the first thin film transistor T1 is connected to the first node N1.
A gate of the fifth thin film transistor T5 and a gate of the sixth thin film transistor T6 are connected to the light signal line (EM)115, a source of the fifth thin film transistor T5 is connected to the constant voltage high potential (VDD)116, a drain of the fifth thin film transistor T5 is connected to the second node N2, a source of the sixth thin film transistor T6 is connected to the third node N3, a drain of the sixth thin film transistor T6 is connected to an anode of the light emitting device (OLED)117, and a cathode of the light emitting device 117 is connected to the low potential (VSS) 118.
A gate electrode of the seventh thin film transistor T7 is connected to the gate line 111, a drain electrode of the seventh thin film transistor T7 is connected to the second reference signal line 114-2, and a source electrode of the seventh thin film transistor T7 is connected to an anode electrode of the light emitting device 117.
One end of the capacitor structure Cst1 may be connected to the first node N1, and the other end of the capacitor structure Cst1 may be connected to the constant voltage high potential 116.
Wherein the voltage values of the first reference signal line 114-1 and the second reference signal line 114-2 may be different. Illustratively, the voltage values of the first reference signal line 114-1 and the second reference signal line 114-2 differ by 1V to 5V.
Alternatively, the same signal input terminal may be connected to both the first reference signal line 114-1 and the second reference signal line 114-2.
In the present specification, the functions of the "source" and the "drain" may be interchanged when transistors of opposite polarities are used or when the direction of current flow during circuit operation changes. Therefore, in this specification, "source" and "drain" may be interchanged with each other. The embodiment of the present application does not limit this.
The compensation thin film transistor T2 may be electrically connected to the gate driving terminal, the first node N1, and the third node N3, respectively. The compensation thin film transistor T2 may be used to adjust the potentials of the first node N1 and the third node N3 in response to a gate driving signal. The grid driving end is used for providing a grid driving signal.
The first node N1 may be connected to the gate of the third tft T3, the drain of the second tft T2, the drain of the first tft T1, and one end of the storage capacitor C1. Therefore, the potential at the first node N1 is relatively easily affected by other structures in the driving circuit, resulting in poor stability of the potential at the first node N1.
Alternatively, as shown in fig. 9, the target constant voltage signal line segment may include a constant voltage power supply line 116. The constant voltage power line is used for providing a driving power signal. The driving power supply line is connected to a source of the fifth thin film transistor. The compensation thin film transistor T2 is connected to the driving gate electrode of the driving thin film transistor T1 through a node connection line 119. Since the voltage at node N1 is less stable, the voltage on node connection 119 is also less stable and is more susceptible to external voltage. The voltage on the data signal line may change with the control state of the driving circuit, which may affect the node connection line 119. The constant voltage power line 116 may be positioned between the node connection line 119 and the data signal line 112 to shield the node connection line 119 from the data signal line 112.
When the target conductive block is connected to the constant voltage power line from a side close to the node N1, it is necessary to bypass the node N1 and the node connecting line 119 and then connect to the constant voltage power line. Thus, the size of the driving circuit is increased, which is not favorable for the miniaturization of the array substrate.
Therefore, the target conductive shielding block can be connected to the constant voltage power supply line from the side away from the node N1, so that the size of the driving circuit can be made small.
In summary, the embodiment of the present application provides an array substrate including a substrate base plate and a driving circuit on the substrate base plate. The array substrate is provided with a display area and an opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece. The at least one target thin film transistor corresponds to the at least one target conductive blocking piece one to one. At least one target conductive blocking piece of the plurality of target conductive blocking pieces is electrically connected with at least one target constant voltage signal line. Through setting up the electrically conductive dog that hides of target constant voltage signal line and the target of being connected with the electrically connected of target constant voltage signal line to shelter from the active layer with the adjacent target thin film transistor in trompil district by the electrically conductive dog of target, so alright make this target thin film transistor's performance comparatively stable, solved the relatively poor problem of stability of the adjacent thin film transistor in trompil district edge among the correlation technique, realized improving the effect of the stability of the adjacent thin film transistor in trompil district edge.
Fig. 11 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application, which may be used to manufacture the array substrate according to the embodiment. As shown in fig. 11, the method includes:
The material of the substrate may include glass, polyimide, or the like.
Step 202 may include the steps of:
1) the active layer thin film may be formed on the base substrate by any of various means such as deposition, coating, and sputtering. And carrying out a composition process on the active layer film once to obtain the active layer pattern.
2) An insulating film may be formed on the substrate on which the active layer pattern is formed by any of various means such as deposition, coating, and sputtering to form a gate insulating layer. Alternatively, the material of the insulating film may include: and inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride.
3) The first conductive film may be formed by any of various means such as deposition, coating, and sputtering on the substrate on which the insulating film is formed. And carrying out a composition process on the first conductive film to obtain a first conductive pattern. Wherein the first conductive pattern may include: the first polar plate, the grid line and the grid of the capacitor structure. Alternatively, the material of the first conductive pattern may include a metal material such as metallic aluminum, metallic silver, metallic molybdenum, or an alloy.
First, a first insulating layer is formed by any of various means such as deposition, coating, and sputtering on a substrate on which a first conductive pattern is formed. Optionally, the material of the first insulating layer may include: silicon nitride, silicon oxide, or silicon oxynitride.
Then, a second conductive film may be formed on the substrate on which the first insulating layer is formed by any of various means such as deposition, coating, and sputtering. And carrying out a composition process on the second conductive film to obtain a second conductive pattern. The second conductive pattern may include: the second polar plate of the capacitor structure, the target conductive blocking piece and the reference signal line. The orthographic projection of the target conductive blocking block on the substrate base plate is overlapped with the orthographic projection of the active layer of the corresponding target thin film transistor on the substrate base plate.
Optionally, the material of the first conductive pattern may include: metal materials such as metal aluminum, metal silver, metal molybdenum or alloy.
And 204, sequentially forming a dielectric layer and a third conductive pattern on one side of the second conductive pattern, which is far away from the substrate base plate.
And a via hole communicated with the second conductive pattern and the third conductive pattern is formed on the dielectric layer. The second conductive pattern may include: power signal line, node connection line, source and drain.
First, a dielectric layer is formed by any of various means such as deposition, coating, and sputtering on a substrate on which a first conductive pattern is formed. And carrying out a one-time composition process on the dielectric layer to form a via hole for lapping the target conductive blocking block and the power signal line.
Then, the third conductive film may be formed on the substrate on which the dielectric layer is formed by any of various means such as deposition, coating, and sputtering. And carrying out a composition process on the third conductive film once to obtain a third conductive pattern.
Optionally, the material of the third conductive pattern may include: metal materials such as metal aluminum, metal silver, metal molybdenum or alloy.
It should be noted that the one-time patterning process in the embodiment of the present application may include: photoresist coating, exposure, development, etching and photoresist stripping.
In summary, the present application provides a method for manufacturing an array substrate. The array substrate in the method comprises a substrate and an array substrate of a driving circuit positioned on the substrate. The array substrate is provided with a display area and an opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece. The at least one target thin film transistor corresponds to the at least one target conductive blocking piece one to one. At least one target conductive blocking piece of the plurality of target conductive blocking pieces is electrically connected with at least one target constant voltage signal line. Through setting up the electrically conductive dog that hides of target constant voltage signal line and the target of being connected with the electrically connected of target constant voltage signal line to shelter from the active layer with the adjacent target thin film transistor in trompil district by the electrically conductive dog of target, so alright make this target thin film transistor's performance comparatively stable, solved the relatively poor problem of stability of the adjacent thin film transistor in trompil district edge among the correlation technique, realized improving the effect of the stability of the adjacent thin film transistor in trompil district edge.
According to another aspect of the present application, there is provided a display panel including the array substrate in any one of the above embodiments. The array substrate may include a substrate and a driving circuit on the substrate. The array substrate is provided with a display area and an opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece. The at least one target thin film transistor corresponds to the at least one target conductive blocking piece one to one. At least one target conductive blocking piece of the plurality of target conductive blocking pieces is electrically connected with at least one target constant voltage signal line. By locating at least one target conductive blocking piece at the side of the corresponding target thin film transistor far away from the substrate base plate, the orthographic projection of the at least one target conductive blocking piece on the substrate base plate is overlapped with the orthographic projection of the active layer of the corresponding target thin film transistor on the substrate base plate. The stability of the target thin film transistor may be improved, and the target thin film transistor includes at least one thin film transistor adjacent to the opening region among the plurality of thin film transistors. Therefore, the stability of the target thin film transistor on the array substrate adjacent to the opening area can be improved.
Optionally, the display panel further includes a plurality of light emitting units on the array substrate. The array substrate includes a driving circuit, and the driving circuit may include a plurality of pixel circuits, at least one of which is electrically connected to at least one of the light emitting cells. The display panel may also include a display area and an opening area, and the positions of the display area and the opening area on the display panel may correspond to the positions of the display area and the opening area on the array substrate.
The array substrate can enable the brightness of at least one light-emitting unit adjacent to the opening area to be normal, and further can improve the display effect of the display panel adjacent to the opening area.
In summary, the present application provides a display panel including an array substrate. The array substrate may include a substrate and a driving circuit on the substrate. The array substrate is provided with a display area and an opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece. The at least one target thin film transistor corresponds to the at least one target conductive blocking piece one to one. At least one target conductive blocking piece of the plurality of target conductive blocking pieces is electrically connected with at least one target constant voltage signal line. Through setting up the electrically conductive dog that hides of target constant voltage signal line and the target of being connected with the electrically connected of target constant voltage signal line to shelter from the active layer with the adjacent target thin film transistor in trompil district by the electrically conductive dog of target, so alright make this target thin film transistor's performance comparatively stable, solved the relatively poor problem of stability of the adjacent thin film transistor in trompil district edge among the correlation technique, realized improving the effect of the stability of the adjacent thin film transistor in trompil district edge.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
In this application, the terms "first," "second," "third," "fourth," "fifth," "sixth," and "seventh" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.
The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (13)
1. An array substrate, comprising: the drive circuit comprises a substrate base plate and a drive circuit positioned on the substrate base plate;
the array substrate is provided with a display area and an opening area, the display area at least partially surrounds the opening area, and the driving circuit comprises a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive blocking piece which are positioned in the display area;
the plurality of thin film transistors comprise at least one target thin film transistor, the at least one target thin film transistor corresponds to the at least one target conductive shielding block in a one-to-one mode, and the target thin film transistor comprises at least one thin film transistor which is adjacent to the opening area in the plurality of thin film transistors;
many constant voltage signal lines include an at least target constant voltage signal line section, the electrically conductive stop dog of at least one target in the electrically conductive stop dog of a plurality of targets with at least one the electrically connected of target constant voltage signal line section, the electrically conductive stop dog of at least one target is located corresponding target thin film transistor and keeps away from one side of substrate base plate, the electrically conductive stop dog of at least one target is in orthographic projection on the substrate base plate is in with the active layer of the target thin film transistor that corresponds orthographic projection on the substrate base plate exists the overlap.
2. The array substrate of claim 1, wherein the at least one target constant voltage signal line segment is located on a target side of the target thin film transistor, and the target thin film transistor is a thin film transistor whose target side is adjacent to the opening region.
3. The array substrate of claim 2, wherein the number of the target thin film transistors is plural, the plural target thin film transistors are arranged in plural rows on the substrate, and at least one row of the plural rows of the target thin film transistors includes at least two of the target thin film transistors;
the number of the target constant voltage signal line segments is multiple, the multiple target constant voltage signal line segments correspond to multiple columns of the target thin film transistors one to one, and the target conductive blocking blocks corresponding to at least two target thin film transistors of at least one column of the target thin film transistors are electrically connected with the target constant voltage signal line segments corresponding to at least one column of the target thin film transistors.
4. The array substrate of claim 3, wherein the at least one column of target constant voltage signal line segments is electrically connected to at least one other constant voltage signal line segment of the driving circuit except the at least one target constant voltage signal line segment.
5. The array substrate of claim 4, wherein a plurality of the target constant voltage signal line segments are electrically connected.
6. The array substrate of claim 3, wherein a plurality of the target constant voltage signal line segments are located outside the first area of the opening area;
the opening area is divided into the first area and the second area by a first straight line, and the first straight line passes through the center of the opening area and is parallel to the arrangement direction of the at least one row of target thin film transistors.
7. The array substrate of claim 6, wherein the opening area is circular, and the first line passes through a center of the opening area.
8. The array substrate of any one of claims 1 to 7, wherein the array substrate further comprises a source drain metal layer, and the at least one target constant voltage signal line segment is located on the source drain metal layer.
9. The array substrate of any one of claims 1 to 7, wherein the array substrate further comprises a dielectric layer, the target conductive block and the target constant voltage signal line segment are respectively located on two sides of the dielectric layer in a direction perpendicular to the substrate, at least one of the target conductive block and at least one of the target constant voltage signal line segments are electrically connected through a via, and the via penetrates through the dielectric layer.
10. The array substrate of any one of claims 1 to 7, wherein the target thin film transistor is a double-gate thin film transistor, the double-gate thin film transistor comprises two gates, and an orthographic projection of the target conductive block on the substrate overlaps with an orthographic projection of a channel region between the two gates on the substrate.
11. The array substrate of any of claims 1-7, wherein the target constant voltage signal line segment comprises a constant voltage power line.
12. A display panel comprising the array substrate according to any one of claims 1 to 11.
13. The display panel of claim 12, further comprising a plurality of light emitting cells on the array substrate, the array substrate comprising a driving circuit comprising a plurality of pixel circuits, at least one of the pixel circuits being electrically connected to at least one of the light emitting cells.
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| CN202110872576.7A CN113611713A (en) | 2021-07-30 | 2021-07-30 | Array substrate and display panel |
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| CN202110872576.7A CN113611713A (en) | 2021-07-30 | 2021-07-30 | Array substrate and display panel |
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| CN110265470A (en) * | 2019-07-01 | 2019-09-20 | 京东方科技集团股份有限公司 | Display device, display panel and its manufacturing method |
| WO2020228205A1 (en) * | 2019-05-16 | 2020-11-19 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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| CN1900801A (en) * | 1997-02-27 | 2007-01-24 | 精工爱普生株式会社 | Device comprising display region, liquid crystal apparatus and projecting display unit |
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