CN113611595B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000005530 etching Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 51
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- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000007423 decrease Effects 0.000 claims description 4
- HJUGFYREWKUQJT-UHFFFAOYSA-N tetrabromomethane Chemical compound BrC(Br)(Br)Br HJUGFYREWKUQJT-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 349
- 230000008569 process Effects 0.000 description 26
- 230000007547 defect Effects 0.000 description 15
- 150000002902 organometallic compounds Chemical class 0.000 description 10
- 239000000203 mixture Substances 0.000 description 7
- 238000001451 molecular beam epitaxy Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 6
- 238000005019 vapor deposition process Methods 0.000 description 6
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- 238000006243 chemical reaction Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
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- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000035772 mutation Effects 0.000 description 3
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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Abstract
The invention provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: providing a semiconductor substrate layer; forming a first strain layer on the semiconductor substrate layer; forming a first lattice matching layer on the semiconductor substrate layer, the first lattice matching layer having at least first and second atoms therein; and etching the first lattice matching layer to enable the first lattice matching layer to form a first strained layer, wherein the etching rate of the first atoms is higher than that of the second atoms, and the molar ratio of the first atoms to the second atoms in the first strained layer is smaller than that of the first atoms to the second atoms in the first lattice matching layer. The preparation method of the semiconductor structure enables the quality of the first strain layer to be better.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
A superlattice is a special semiconductor structure and is widely used in many semiconductor optoelectronic devices, such as semiconductor lasers, photodetectors, and avalanche diodes. Among them, the strained superlattice is an important ring in the superlattice system. The strain superlattice is a superlattice structure which is prepared by adjusting the atomic distance of two materials with certain lattice mismatch degrees by elastic deformation when a heterostructure is prepared by utilizing ultrathin layer epitaxial growth technologies such as Molecular Beam Epitaxy (MBE) and Metal Organic Compound Vapor Deposition (MOCVD), and finally, the two materials reach interface atomic arrangement and still keep lattice match.
The occurrence of the strain superlattice increases the degree of freedom and flexibility of superlattice material selection, and the energy band structure of the material can be tailored by independently adjusting the parameters of components, stress, layer thickness, number, doping and the like, thereby opening up an important way for designing and manufacturing various new solid-state electronic devices. Taking the epitaxial structure of the mid-far infrared quantum cascade laser as an example, the epitaxial growth is carried out on an InP substrate, and an InP buffer layer, an active region and an InP upper limiting layer are sequentially grown. Wherein the substrate and InP buffer layer function as a lower confinement layer, and the active region is composed of a series of In with specific composition and thicknessxGa1-xAs/InyAl1- yAs strain superlattice layers are alternately combined. In order to improve the performance of the devicexGa1-xAs has a lattice constant larger than that of InP, and exhibits compressive strain InyAl1-yThe lattice constant of As is smaller than that of InP, which exhibits tensile strain.
It is to be noted here that InxGa1-xThe lattice constant of As varies with the content of the In component In the material, and the higher the In component, the larger the lattice constant. When the In component content is x =0.53, InxGa1-xThe lattice constant of As is identical to that of the InP substrate. InyAl1-yThe lattice constant of As varies with the content of the In component In the material, and the higher the In component, the larger the lattice constant. When the In component content is y =0.52, InyAl1-yThe lattice constant of As is identical to that of the InP substrate. Thus, In is compressively strainedxGa1-xAn As material having an In component greater than 0.53; in of tensile strainyAl1-yAs material having an In component of less than 0.52.
There is a limit to the growth of the strained superlattice, most typically the growth temperature, which should not be too high. The higher the growth temperature, the greater the strain energy accumulated by lattice mismatchThe more easily the material relaxes. However, when the growth temperature is too low, the quality of the MOCVD grown material cannot be ensured. Growth of In by MOCVDxGa1-xAs/InyAl1-yAs strained superlattice As an example, let In be assumedxGa1-xAs、InyAl1-yAs has a single layer thickness of 3nm and InxGa1-xAs exhibits a compressive strain of 1% relative to the substrate, InyAl1-yAs exhibits a tensile strain of 1% relative to the substrate. MOCVD growth of In due to strain limitationxGa1-xAs/InyAl1- yThe growth temperature of the As strained superlattice should not be too high, otherwise material relaxation may occur. At this temperature, if In with 1% compressive strain is grownxGa1-xAs, In atom and Ga atom have good mobilityxGa1-xThe growth quality of As material is better; if In with 1% tensile strain is grownyAl1-yAs, In because of high Al content and poor Al mobilityyAl1-yAs materials have poor growth quality and easily coarsened surfaces. Eventually lead to InxGa1-xAs/InyAl1-yThe quality of the As strain superlattice interface is reduced, and the surface is coarsened.
While for a single layer of highly strained InyAl1-yAs, when a higher growth temperature is used, thermal degradation is likely to occur during growth, and the material is more likely to relax As the accumulated strain energy of lattice mismatch increases, and InyAl1-yAs introduces defects, the growth quality is poor.
Whether a compressively strained material or a tensile strained material, further improvements in formation quality are desired.
Disclosure of Invention
Therefore, the present invention is directed to overcome the problem of poor growth quality of high-strain semiconductor materials in the prior art, and to provide a semiconductor structure and a method for fabricating the same.
The invention provides a preparation method of a semiconductor structure, which comprises the following steps: providing a semiconductor substrate layer; forming a first strain layer on the semiconductor substrate layer; forming a first lattice matching layer on the semiconductor substrate layer, the first lattice matching layer having at least first and second atoms therein; and etching the first lattice matching layer to enable the first lattice matching layer to form a first strained layer, wherein the etching rate of the first atoms is higher than that of the second atoms, and the molar ratio of the first atoms to the second atoms in the first strained layer is smaller than that of the first atoms to the second atoms in the first lattice matching layer.
Optionally, the mobility of the second atom is smaller than the mobility of the first atom.
Optionally, the material of the first strained layer includes InyAl1-yAs, the first atoms are In atoms, the second atoms are Al atoms, and the material of the first lattice matching layer comprises In0.52Al0.48As。
Optionally, the etching gas used for etching the first lattice matching layer includes CBr4。
Optionally, in a direction from a side of the first strained layer facing the semiconductor substrate layer to a side of the first strained layer facing away from the semiconductor substrate layer, a molar ratio of the first atoms to the second atoms in the first strained layer decreases.
Optionally, the semiconductor substrate layer includes an InP substrate layer.
Optionally, the method further includes: forming a superlattice cell on the semiconductor substrate layer, the forming the superlattice cell comprising: and forming a first strain layer to an Nth strain layer on the semiconductor substrate layer, wherein N is an integer greater than or equal to 2.
Optionally, N is equal to 2, and a second lattice matching layer is formed on the semiconductor substrate layer before the first lattice matching layer is formed; before the first lattice matching layer is formed, forming a second strain layer on the surface of one side, facing away from the semiconductor substrate layer, of the second lattice matching layer; when the first strain layer is a compressive strain layer, the second strain layer is a tensile strain layer, and when the first strain layer is a tensile strain layer, the second strain layer is a compressive strain layer.
Optionally, the material of the second strained layer comprises InxGa1-xAs, the material of the second lattice matching layer includes In0.53Ga0.47As。
Optionally, the step of forming the superlattice units is repeated to form a plurality of superlattice units, and the plurality of superlattice units form a superlattice structure.
Optionally, the method further includes: and forming a lattice matching cover layer on the surface of one side of the superlattice structure, which faces away from the semiconductor substrate layer.
Optionally, the material of the lattice matching cap layer comprises In0.53Ga0.47As。
Optionally, the method further includes: and forming a main cover layer on the surface of one side, which faces away from the semiconductor substrate layer, of the lattice matching cover layer.
Optionally, the host layer comprises an InP layer.
Optionally, the method further includes: and forming a buffer layer on the surface of the semiconductor substrate layer before forming the first strain layer.
The invention also provides a semiconductor structure formed by the preparation method of the semiconductor structure.
The technical scheme of the invention has the following beneficial effects:
according to the preparation method of the semiconductor structure, the crystal lattice of the first crystal lattice matching layer is matched with the crystal lattice of the semiconductor substrate layer, only mutation of material components but no mutation of stress exists at the bottom interface of the first crystal lattice matching layer, and the probability of forming defects at the bottom interface position of the first crystal lattice matching layer is greatly reduced, so that the defect density in the first crystal lattice matching layer is very low. And etching the first lattice matching layer, wherein the etching rate of the first atoms is higher than that of the second atoms, so that the molar ratio of the first atoms to the second atoms in the formed first strained layer is smaller than that of the first atoms to the second atoms in the first lattice matching layer, and the stress is generated in the first strained layer and meets the requirement of the first strained layer on the stress. Even though a few defects may be introduced during the etching of the first lattice matching layer, the density of defects formed during the etching of the first lattice matching layer is much less than that produced by growing the first strained layer directly on the semiconductor substrate layer. The first strained layer has a good quality because of its low defect density and low defects introduced during the etching of the first lattice matching layer, and the first strained layer is formed by etching the first lattice matching layer. In conclusion, the preparation method of the semiconductor structure enables the quality of the first strain layer to be better.
Further, the mobility of the second atoms is smaller than the mobility of the first atoms. The less the second atomic proportion that is less mobile, the lower the growth temperature required. Even if the mobility of the second atoms is smaller than that of the first atoms, the mole ratio of the first atoms to the second atoms in the first lattice matching layer is larger, namely the second atoms occupy less, so that the first lattice matching layer can be grown and formed at a lower temperature and has better quality, and the growth of the first lattice matching layer is prevented from being limited by the growth temperature. And the first strained layer is formed by etching the first lattice matching layer, so that the formation of the first strained layer avoids being limited by the growth temperature.
Further, in a direction from a side of the first strained layer facing the semiconductor substrate layer to a side of the first strained layer facing away from the semiconductor substrate layer, a molar ratio of the first atoms to the second atoms in the first strained layer decreases. Therefore, the molar ratio of the first atoms to the second atoms in the first strain layer is unevenly distributed, the molar ratio of the first atoms to the second atoms in the first strain layer can meet the requirement that the first strain layer has certain strain, and the forbidden bandwidth of the first strain layer can be adjusted at the same time, so that the application of the first strain layer is expanded.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment of the present invention;
fig. 2 to 8 are structural diagrams of a manufacturing process of a semiconductor structure according to an embodiment of the invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a method for manufacturing a semiconductor structure, referring to fig. 1, including the following steps:
s1, providing a semiconductor substrate layer;
s2, forming a first strain layer on the semiconductor substrate layer; forming a first lattice matching layer on the semiconductor substrate layer, the first lattice matching layer having at least first and second atoms therein; and etching the first lattice matching layer to enable the first lattice matching layer to form a first strained layer, wherein the etching rate of the first atoms is higher than that of the second atoms, and the molar ratio of the first atoms to the second atoms in the first strained layer is smaller than that of the first atoms to the second atoms in the first lattice matching layer.
In this embodiment, the method for manufacturing a semiconductor structure further includes: and forming a superlattice cell on the semiconductor substrate layer. The step of forming the superlattice cell includes: and forming a first strain layer to an Nth strain layer on the semiconductor substrate layer, wherein N is an integer greater than or equal to 2. That is, the step of forming the first strained layer is performed as one of the steps of forming the superlattice cell. This case will be taken as an example below. It should be noted that in other embodiments, the first strained layer having one strain type may be formed without forming the superlattice cell.
In the following embodiments, N is equal to 2 as an example, and in other embodiments, N may also be an integer greater than or equal to 3.
The following describes the preparation process of the embodiment of the present invention in detail with reference to fig. 2 to 8.
Referring to fig. 2, a semiconductor substrate layer 100 is provided.
In this embodiment, the semiconductor substrate layer 100 is an InP substrate layer. It should be noted that, in other embodiments, the semiconductor substrate layer may also be a substrate layer of other materials.
Referring to fig. 3, a buffer layer 110 is formed on a surface of the semiconductor substrate layer 100.
In this embodiment, the material of the buffer layer 110 includes an InP buffer layer.
The thickness of the buffer layer 110 is 180nm to 220nm, for example, 200 nm.
The buffer layer 110 is formed by a process including a Molecular Beam Epitaxy (MBE) process or a Metal Organic Compound Vapor Deposition (MOCVD) process.
In the present embodiment, the first and second electrodes are,the process of forming the buffer layer 110 is a metal organic compound vapor deposition process, and the parameters of forming the buffer layer 110 include: the gas introduced comprises pH3And TMIn (trimethyl indium) at a temperature of 590-610 degrees celsius, such as 600 degrees celsius.
Referring to fig. 4, a second lattice matching layer 120 is formed on the semiconductor substrate layer 100; a second strained layer 130 is formed on a surface of the second lattice matching layer 120 facing away from the semiconductor substrate layer 100.
The second lattice matching layer 120 is located on a side surface of the buffer layer 110 facing away from the semiconductor substrate layer 100.
In one embodiment, the material of the second lattice matching layer 120 includes In0.53Ga0.47As, the semiconductor substrate layer 100 is an InP substrate layer such that the second lattice matching layer 120 is lattice matched to the semiconductor substrate layer 100.
In one embodiment, the second lattice matching layer 120 has a thickness of 190nm to 210nm, such as 200 nm.
The second lattice matching layer 120 is formed by a process including a Molecular Beam Epitaxy (MBE) process or a Metal Organic Compound Vapor Deposition (MOCVD) process.
In this embodiment, the process of forming the second lattice matching layer 120 is a metal organic compound vapor deposition process, and the parameters of forming the second lattice matching layer 120 include: the gas introduced comprises AsH3TMGa (trimethyl gallium) and TMIn (trimethyl indium) at a temperature of 590-610 degrees Celsius, such as 600 degrees Celsius.
The second lattice matching layer 120 serves as a growth substrate of the second strained layer 130, and the growth quality of the second strained layer 130 is improved. It should be noted that, in other embodiments, the second lattice matching layer 120 may not be formed.
In one embodiment, the second strained layer 130 is a compressively strained layer, and the material of the second strained layer 130 includes InxGa1-xAs, x is greater than 0.53, e.g., x = 0.677. In when x =0.677xGa1-xAs exhibits a compressive strain of +1% with respect to the InP substrate layer。
In one embodiment, the second strained layer 130 has a thickness of 2.5nm to 3.5nm, such as 3 nm.
It should be noted that in other embodiments, the second strained layer 130 may also be a tensile strained layer.
The process for forming the second strained layer 130 includes a Molecular Beam Epitaxy (MBE) process or a Metal Organic Compound Vapor Deposition (MOCVD) process.
In one embodiment, the process of forming the second strained layer 130 is a metal organic compound vapor deposition process, when the material of the second strained layer 130 is InxGa1-xAs, the parameters for forming the second strained layer 130 include: the gas introduced comprises AsH3TMGa (trimethyl gallium) and TMIn (trimethyl indium) at a temperature of 590-610 degrees Celsius, such as 600 degrees Celsius.
Referring to fig. 5, a first lattice matching layer 140 is formed on the semiconductor substrate layer 100, and the first lattice matching layer 140 has at least a first atom and a second atom therein.
Specifically, a first lattice matching layer 140 is formed on a surface of the second strained layer 130 facing away from the semiconductor substrate layer 100.
In one embodiment, the second atoms have a mobility less than the mobility of the first atoms. The mole ratio of the first atoms to the second atoms in the first lattice matching layer is relatively large, and the mobility of the first atoms is larger than that of the second atoms, so that the first lattice matching layer 140 with better quality can be grown at a lower temperature.
In a specific embodiment, the material of the first lattice matching layer 140 includes In0.52Al0.48As, the semiconductor substrate layer 100 is an InP substrate layer such that the second lattice matching layer 120 is lattice matched to the semiconductor substrate layer 100. The first atom is an In atom and the second atom is an Al atom.
The first lattice matching layer 140 may be formed by a Molecular Beam Epitaxy (MBE) process or a Metal Organic Chemical Vapor Deposition (MOCVD) processA process for preparing the composite material. In this embodiment, the process of forming the first lattice matching layer 140 is a metal organic compound vapor deposition process, and when the material of the first lattice matching layer 140 is In0.52Al0.48As, AsH is introduced during the growth of the first lattice matching layer 1403TMAl (trimethyl aluminum) and TMIn (trimethyl indium), at a temperature of 560 ℃ to 630 ℃, for example 600 ℃.
Due to In0.52Al0.48As relative to In0.375Al0.625As has less Al component and In0.52Al0.48As is lattice-matched to the InP substrate layer, so In is grown under the same growth conditions0.52Al0.48As has better material quality, small surface roughness and is not easy to relax.
In one embodiment, the first lattice matching layer 140 has a thickness of 3nm to 6 nm.
Referring to fig. 6, the first lattice matching layer 140 is etched such that the first lattice matching layer 140 forms a first strained layer 150 having a greater etch rate for the first atoms than for the second atoms, and having a molar ratio of the first atoms to the second atoms that is less than the molar ratio of the first atoms to the second atoms in the first lattice matching layer.
In this embodiment, the method further includes: after the first lattice matching layer 140 is formed, a growth interruption process is performed, which is performed to replace the atmosphere in the reaction chamber and desorb the residual source material, reaction residue, and the like on the wafer surface from the wafer surface. After the growth interruption process is performed, the first lattice matching layer 140 is etched such that the first lattice matching layer 140 forms a first strained layer 150.
When the first lattice matching layer 140 is grown, AsH is introduced3TMAl and TMIn, in the interruption process of growth, the gas source of TMAl and TMIn are closed, and AsH is retained3The gas source of (2).
When the material of the first lattice matching layer 140 is In0.52Al0.48As, etching gas used for etching the first lattice matching layer 140Comprising CBr4. It should be noted that the AsH may be continuously introduced during the etching of the first lattice matching layer 1403。
In one embodiment, the first strained layer 150 is a tensile strained layer, and the material of the first strained layer 150 includes InyAl1-yAs, y is less than 0.52, e.g. y equals 0.375, In when y =0.375yAl1-yAs exhibits a tensile strain of-1% relative to the InP substrate layer.
In the process of etching the first lattice matching layer 140, the etching rate of the first atoms is greater than the etching rate of the second atoms, specifically, CBr4The etching action is selective to In atoms and Al atoms, i.e., the etching rate of In atoms is higher than that of Al atoms, so that the composition of the first atoms and the second atoms In the first lattice matching layer 140 is changed to become the first strained layer 150, specifically, by controlling CBr4Flow rate and passage time of In0.52Al0.48The composition of In atoms and Al atoms In As is changed to In0.375Al0.625As。
The thickness of the first strained layer 150 may also vary with respect to the first lattice matching layer 140. in one embodiment, the thickness of the first strained layer 150 is controlled to be 3nm to 3.5nm, such as 3 nm.
It should be noted that in this embodiment, N is equal to 2, that is, the superlattice cell includes a first strained layer and a second strained layer, where the second strained layer is a tensile strained layer when the first strained layer is a compressive strained layer, and the second strained layer is a compressive strained layer when the first strained layer is a tensile strained layer.
In other embodiments, the superlattice cell includes a first strained layer through an Nth strained layer, N is an integer greater than or equal to 3, a portion of the strained layers in the superlattice cell are compressive strained layers, and a portion of the strained layers are tensile strained layers.
The total strain of the first strained layer to the nth strained layer in the superlattice cell is 0 with respect to the semiconductor substrate layer.
In this embodiment, the second strained layer is formed before the first strained layer is formed, and in other embodiments, the second strained layer is formed after the first strained layer is formed.
When N is an integer of 3 or more, some of the second to nth strained layers are formed before the first strained layer, and some of the second to nth strained layers are formed after the first strain; the second strained layer to the Nth strained layer are formed before the first strained layer; it is also possible that the second to nth strained layers are all formed after the first strained layer.
It should be noted that in other embodiments, during the etching of the first lattice matching layer 140 to form the first strained layer 150 from the first lattice matching layer 140, the etching gas may etch the second strained layer 130 under the first lattice matching layer 140, so that the composition of the first atoms in the second strained layer 130 is reduced, and the thickness of the second strained layer 130 is reduced, and if the second strained layer 130 under the first lattice matching layer 140 is etched, the composition of the first atoms in the second strained layer 130 and the thickness of the second strained layer 130 should be increased during the formation of the second strained layer 130, so as to compensate for the etching of the second strained layer 130 during the etching of the first lattice matching layer 140. That is, if it is desired to form the second strained layer 130 in the superlattice structure with a target thickness and a target ratio of the first atoms to the second atoms of the second strained layer 130 in the superlattice structure, then in the step of forming the second strained layer 130, the thickness of the second strained layer needs to be greater than the target thickness and the ratio of the first atoms to the second atoms in the second strained layer needs to be greater than the target ratio.
It should be noted that, in other embodiments, the mobility of the second atom may be greater than the mobility of the first atom. In this case, it is also possible to form the first lattice matching layer first and then etch the first lattice matching layer so that the first lattice matching layer forms the first strained layer.
In this embodiment, in a direction from a side of the first strained layer facing the semiconductor substrate layer to a side of the first strained layer facing away from the semiconductor substrate layer, a molar ratio of the first atoms to the second atoms in the first strained layer decreases. Therefore, the molar ratio of the first atoms to the second atoms in the first strain layer is unevenly distributed, the molar ratio of the first atoms to the second atoms in the first strain layer can meet the requirement that the first strain layer has certain strain, and the forbidden bandwidth of the first strain layer can be adjusted at the same time, so that the application of the first strain layer is expanded.
Referring to fig. 7, the step of forming the superlattice cell is repeated to form a number of superlattice cells, which constitute the superlattice structure.
In this embodiment, N is equal to 2, the steps of forming the second strained layer 130, forming the first lattice matching layer 140, and etching the first lattice matching layer 140 are repeated to form a plurality of first strained layers 150 and a plurality of second strained layers 130, where the plurality of first strained layers 150 and the plurality of second strained layers 130 form the superlattice structure 160.
In one embodiment, the number of repetitions for repeating the formation of the superlattice unit is 3 to 1000 times, for example 100 times.
In a specific embodiment, the total thickness (i.e., the period thickness) of the second strained layer 130 and the first strained layer 150 is 2nm to 10nm, for example, 6nm, and the second strained layer 130 and the first strained layer 150 form a period.
When the total thickness of one second strained layer 130 and one first strained layer 150 is 6nm and the number of cycles of the second strained layer 130 and the first strained layer 150 is 100, the total thickness of the superlattice structure 160 is 600 nm.
The superlattice structure 160 is a strained superlattice structure.
Referring to fig. 8, a lattice-matching cap layer 170 is formed on a surface of the superlattice structure 160 facing away from the semiconductor substrate layer 100.
In this embodiment, the material of the lattice matching cap layer 170 is the same as the material of the second lattice matching layer 120. When the material of the second lattice matching layer 120 includes In0.53Ga0.47As, the lattice is matchedThe material of the cap layer 170 includes In0.53Ga0.47As. In other embodiments, the lattice matching cap layer 170 has a thickness greater than the thickness of a single layer of the second strained layer 130 and greater than the thickness of a single layer of the first strained layer 150.
In one embodiment, the lattice matching cap layer 170 has a thickness of 8nm to 12nm, such as 10 nm.
The lattice matching cap layer 170 may be formed by a process including a Molecular Beam Epitaxy (MBE) process or a Metal Organic Chemical Vapor Deposition (MOCVD) process.
In this embodiment, the process of forming the lattice matching cap layer 170 is a metal organic compound vapor deposition process, and the parameters of forming the lattice matching cap layer 170 include: the gas introduced comprises AsH3TMGa (trimethyl gallium) and TMIn (trimethyl indium) at a temperature of 590-610 degrees Celsius, such as 600 degrees Celsius.
The role of the lattice matching cap layer 170 includes: and covering the surface of the high-strain material with a lattice-matched cover layer to reduce the possibility of relaxation of the high-strain material.
With continued reference to fig. 8, a primary cap layer 180 is formed on a side surface of the lattice matching cap layer 170 facing away from the semiconductor substrate layer 100.
The material of the main cap layer 180 is the same as that of the buffer layer 110. The host cap layer 180 comprises an InP cap layer.
The main cap layer 180 may be formed by a Molecular Beam Epitaxy (MBE) process or a Metal Organic Chemical Vapor Deposition (MOCVD) process.
In this embodiment, the process of forming the main cap layer 180 is a metal organic compound vapor deposition process, and the parameters of forming the main cap layer 180 include: the gas introduced comprises pH3And TMIn (trimethyl indium) at a temperature of 590-610 degrees celsius, such as 600 degrees celsius.
In a specific embodiment, the thickness of the main cap layer 180 is 8nm to 12nm, such as 10 nm.
The main cap layer 180 functions as: by growing the main cap layer, the atmosphere of the reaction chamber can be filled with AsH3Is adjusted to fill the atmosphere of (2) with pH3Of the atmosphere (c). From practical observation, fill with pH3The atmosphere of (a) contributes to an increase in the stability of the reaction chamber.
In the method for manufacturing the semiconductor structure provided by this embodiment, the lattice of the first lattice matching layer is matched with the lattice of the semiconductor substrate layer, only a sudden change of material composition exists at the bottom interface of the first lattice matching layer, and there is no sudden change of stress, and the probability of forming defects at the bottom interface position of the first lattice matching layer is greatly reduced, so the defect density in the first lattice matching layer is very low. And etching the first lattice matching layer, wherein the etching rate of the first atoms is higher than that of the second atoms, so that the molar ratio of the first atoms to the second atoms in the formed first strained layer is smaller than that of the first atoms to the second atoms in the first lattice matching layer, and the stress is generated in the first strained layer and meets the requirement of the first strained layer on the stress. Even though a few defects may be introduced during the etching of the first lattice matching layer, the density of defects formed during the etching of the first lattice matching layer is much less than that produced by growing the first strained layer directly on the semiconductor substrate layer. The first strained layer has a good quality because of its low defect density and low defects introduced during the etching of the first lattice matching layer, and the first strained layer is formed by etching the first lattice matching layer. In conclusion, the preparation method of the semiconductor structure enables the quality of the first strain layer to be better.
Further, the mobility of the second atoms is smaller than the mobility of the first atoms. The less the second atomic proportion that is less mobile, the lower the growth temperature required. Even if the mobility of the second atoms is smaller than that of the first atoms, the mole ratio of the first atoms to the second atoms in the first lattice matching layer is larger, namely the second atoms occupy less, so that the first lattice matching layer can be grown and formed at a lower temperature and has better quality, and the growth of the first lattice matching layer is prevented from being limited by the growth temperature. And the first strained layer is formed by etching the first lattice matching layer, so that the formation of the first strained layer avoids being limited by the growth temperature.
It should be noted that the conventional growth method is to grow the first strained layer directly on the semiconductor substrate layer. Due to the fact that the difference between the lattice constants of the first strain layer and the semiconductor substrate layer is large, the first strain layer changes the longitudinal lattice constant and the transverse lattice constant in a lattice stretching mode, the transverse lattice constant of the first strain layer is matched with the transverse lattice constant of the semiconductor substrate layer, but the longitudinal lattice constant of the first strain layer is not matched with the longitudinal lattice constant of the semiconductor substrate layer, and stress is generated inside the first strain layer. The key to growing the first strained layer on the semiconductor substrate layer is the nucleation growth process at the interface. The conventional growth method is to grow a first strained layer directly on a semiconductor substrate layer. Thus, at the interface of the first strained layer and the semiconductor substrate layer, there is not only a sudden change in material composition, but also a sudden change in stress. Due to the presence of these two mutations, when the first strained layer is grown directly on the semiconductor substrate layer, defects such as point defects, dislocations, etc. are easily formed at the interface position and propagate upwards in the growth direction, affecting the material quality of the entire first strained layer.
Correspondingly, the invention also provides a semiconductor structure formed by the preparation method of the semiconductor structure.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (16)
1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate layer;
forming a first strain layer on the semiconductor substrate layer;
the step of forming the first strained layer comprises:
forming a first lattice matching layer on the semiconductor substrate layer, the first lattice matching layer having at least first and second atoms therein;
and etching the first lattice matching layer to enable the first lattice matching layer to form a first strained layer, wherein the etching rate of the first atoms is higher than that of the second atoms, and the molar ratio of the first atoms to the second atoms in the first strained layer is smaller than that of the first atoms to the second atoms in the first lattice matching layer.
2. The method of claim 1, wherein the second atoms have a mobility less than the mobility of the first atoms.
3. The method of claim 2, wherein the material of the first strained layer comprises InyAl1-yAs, the first atoms are In atoms, the second atoms are Al atoms, and the material of the first lattice matching layer comprises In0.52Al0.48As。
4. The method of claim 3, wherein the etching gas used to etch the first lattice matching layer comprises CBr4。
5. The method of claim 1, wherein a molar ratio of the first atoms to the second atoms in the first strained layer decreases in a direction from a side of the first strained layer facing the semiconductor substrate layer to a side of the first strained layer facing away from the semiconductor substrate layer.
6. The method of fabricating a semiconductor structure according to claim 1, wherein the semiconductor substrate layer comprises an InP substrate layer.
7. The method of fabricating a semiconductor structure according to any one of claims 1 to 6, further comprising: forming a superlattice cell on the semiconductor substrate layer, the forming the superlattice cell comprising: and forming a first strain layer to an Nth strain layer on the semiconductor substrate layer, wherein N is an integer greater than or equal to 2.
8. The method of fabricating a semiconductor structure according to claim 7, wherein N is equal to 2, and a second lattice matching layer is formed on the semiconductor substrate layer before the first lattice matching layer is formed; before the first lattice matching layer is formed, forming a second strain layer on the surface of one side, facing away from the semiconductor substrate layer, of the second lattice matching layer; when the first strain layer is a compressive strain layer, the second strain layer is a tensile strain layer, and when the first strain layer is a tensile strain layer, the second strain layer is a compressive strain layer.
9. The method of claim 8, wherein the material of the second strained layer comprises InxGa1-xAs, the material of the second lattice matching layer includes In0.53Ga0.47As。
10. The method of claim 7 wherein the step of forming the superlattice cell is repeated to form a plurality of superlattice cells, said plurality of superlattice cells forming the superlattice structure.
11. The method of claim 10, further comprising: and forming a lattice matching cover layer on the surface of one side of the superlattice structure, which faces away from the semiconductor substrate layer.
12. The method of claim 11, wherein the material of the lattice-matched cap layer comprises In0.53Ga0.47As。
13. The method of claim 11, further comprising: and forming a main cover layer on the surface of one side, which faces away from the semiconductor substrate layer, of the lattice matching cover layer.
14. The method of claim 13, wherein the host cap layer comprises an InP cap layer.
15. The method of claim 1, further comprising: and forming a buffer layer on the surface of the semiconductor substrate layer before forming the first strain layer.
16. A semiconductor structure formed by the method of any one of claims 1 to 15.
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| CN110491965A (en) * | 2019-07-25 | 2019-11-22 | 中山德华芯片技术有限公司 | A kind of five-junction solar cell of lattice mismatch and preparation method thereof |
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| WO2008026542A1 (en) * | 2006-08-28 | 2008-03-06 | Mitsubishi Chemical Corporation | Etchant and etching process |
| JP2018201009A (en) * | 2017-05-25 | 2018-12-20 | 昭和電工株式会社 | Light-emitting diode and method for manufacturing tunnel junction layer |
| CN109285909A (en) * | 2018-09-29 | 2019-01-29 | 扬州乾照光电有限公司 | A kind of multijunction solar cell and preparation method thereof |
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