CN113609038A - Interrupt processing method and device and electronic equipment - Google Patents
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Abstract
The application provides an interrupt processing method and device and electronic equipment. The method comprises the following steps: the method comprises the steps that an interrupt distributor receives an interrupt request from an interrupt source and sends the interrupt request to one of a plurality of interrupt controllers according to interrupt routing information corresponding to the interrupt source, wherein the number of the interrupt sources is multiple; the interrupt controller sends a received interrupt request to a corresponding processing unit, records an interrupt source ID corresponding to the interrupt request, and enables the processing unit to execute an interrupt processing program according to the interrupt request and the interrupt source ID, wherein the interrupt controller corresponds to the processing unit one by one, and the interrupt route information can be updated by the processing unit. The method improves the safety and flexibility of interrupt processing.
Description
Technical Field
The application belongs to the technical field of computers, and particularly relates to an interrupt processing method and device and electronic equipment.
Background
A plurality of sub-engines are usually provided in the independent graphics card, and each sub-engine processes a type of task. Common sub-engines are, for example, Graphics Processors (GPUs), video codecs, display controllers, audio controllers, and the like. Each sub-engine is an interrupt source and may generate an interrupt request (in the form of a level signal or a pulse signal) at any time. These interrupt requests may be processed by a programmable processor (e.g., a micro processing unit (MCU)) in the independent graphics card, or may be reported to a system processor (CPU) for processing through a system bus interface (e.g., a PCIe interface). The entity that runs the interrupt handler (i.e., the aforementioned programmable processor or system processor) is referred to herein as a processing unit.
Referring to fig. 1, in the related art, a single interrupt controller is used to route interrupt requests from various interrupt sources and to interact with information of a processing unit. This structure causes various problems: a plurality of processing units can compete for the same interrupt request, and the safety of the system is influenced; or a certain processing unit in the system encounters security attack, the attacked processing unit may forcibly intercept all the interrupt requests. Some processing units (such as general purpose CPUs) can only receive interrupt requests, some processing units (such as some MCUs) can simultaneously receive interrupt requests and interrupt source IDs, and since the interrupt controller does not determine which processing unit the current interrupt request is specifically processed by, only transmits the interrupt request to the processing unit, and cannot reflect the difference of different processing units when receiving interrupt related information; the policy of each processing unit in handling the interrupt priority is different, and if a single interrupt controller manages all interrupt requests, it is difficult to achieve differential setting of priority policies of different processing units.
Disclosure of Invention
The present application is directed to provide an interrupt processing method, apparatus and electronic device, to at least partially solve the problems in the prior art.
In order to solve the technical problem, the following technical scheme is adopted in the application: an interrupt handling method comprising: the method comprises the steps that an interrupt distributor receives an interrupt request from an interrupt source and sends the interrupt request to one of a plurality of interrupt controllers according to interrupt routing information corresponding to the interrupt source, wherein the number of the interrupt sources is multiple; the interrupt controller sends a received interrupt request to a corresponding processing unit, records an interrupt source ID corresponding to the interrupt request, and enables the processing unit to execute an interrupt processing program according to the interrupt request and the interrupt source ID, wherein the interrupt controller corresponds to the processing unit one by one, and the interrupt route information can be updated by the processing unit.
In order to solve the technical problem, the following technical scheme is adopted in the application: an interrupt handling apparatus comprising: the interrupt distributor is used for receiving an interrupt request from an interrupt source and sending the interrupt request to one of a plurality of interrupt controllers according to interrupt routing information corresponding to the interrupt source, wherein the number of the interrupt sources is multiple; and the interrupt controller is used for sending the received interrupt request to a corresponding processing unit and recording an interrupt source corresponding to the interrupt request so that the processing unit can execute an interrupt processing program according to the interrupt request and the interrupt source ID, wherein the interrupt controller is in one-to-one correspondence with the processing unit, and the interrupt route information can be updated by the processing unit.
In order to solve the technical problem, the following technical scheme is adopted in the application: an electronic device comprising a plurality of interrupt sources and a plurality of processing units and the aforementioned interrupt handling apparatus, an interrupt distributor in the interrupt handling apparatus being connected to the plurality of interrupt sources to receive interrupt requests from the plurality of interrupt sources; the interrupt controllers in the interrupt processing device correspond to the processing units one by one, so that the processing units execute interrupt processing programs according to the interrupt requests and the interrupt source IDs.
Compared with the prior art, the beneficial effect of this application is: each interrupt request is only sent to one interrupt controller by the interrupt distributor, so that the interrupt request is only sent to one processing unit, multiple processing units are prevented from competing for the same interrupt request, and the safety of the system is improved. Further, when a processing unit is unable to process an interrupt request it receives, it may be forwarded to other processing units. Thereby improving flexibility in interrupt handling.
Drawings
Fig. 1 is a block diagram of an existing electronic device including a separate graphics card.
Fig. 2 is a flowchart of an interrupt processing method according to an embodiment of the present application.
Fig. 3 is a flowchart of an interrupt processing method according to an embodiment of the present application.
Fig. 4 is a block diagram of an electronic device including an interrupt processing apparatus according to an embodiment of the present application.
Detailed Description
In this application, it will be understood that terms such as "including" or "having," or the like, are intended to indicate the presence of the disclosed features, integers, steps, acts, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, acts, components, parts, or combinations thereof.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
The application is further described with reference to examples of embodiments shown in the drawings.
As shown in fig. 2, an embodiment of the present application provides an interrupt processing method, including the following steps.
Referring to fig. 4, the graphics rendering sub-engine 31, the video codec sub-engine 32, the display control sub-engine 33, the audio sub-engine 34, the first programmable processor 41, and the second programmable processor 42 are components of a separate graphics card. The PCIe bus 5 is used for communication between the system processor 43 and the independent graphics card.
Graphics rendering sub-engine 31 may be used for 3D image rendering. The video codec sub-engine 32 may be used for video codec. The display control sub-engine 33 may be used to transfer display data in a frame buffer in a display memory (not shown) in a separate graphics card to the video codec 32 for video encoding. The audio sub-engine 34 is used for processing of audio data. The above are all common functional modules in the independent graphics card, and the function and structure of these functional modules are not limited in this application.
The interrupt sources are, for example, the graphics rendering sub-engine 31, the video codec sub-engine 32, the display control sub-engine 33, and the audio sub-engine 34 in fig. 4.
And 102, the interrupt controller sends the received interrupt request to a corresponding processing unit, records an interrupt source ID corresponding to the interrupt request, and enables the processing unit to execute an interrupt processing program according to the interrupt request and the interrupt source ID, wherein the interrupt controller corresponds to the processing unit one by one, and the interrupt route information can be updated by the processing unit.
The processing units are, for example, a first programmable processor 41, a second programmable processor 42 and a system processor 43 in fig. 4. The first programmable processor 41 and the second programmable processor 42 may be one processing module in separate graphics cards, both processing different types of tasks. The first programmable processor 41 is responsible for task scheduling of the independent graphics card, for example, and the second programmable processor 42 is responsible for state control (e.g., reset) of each functional module in the independent graphics card, for example. The system processor 43 is, for example, a CPU in the electronic device.
Each interrupt request is only sent to one interrupt controller by the interrupt distributor, so that the interrupt request is only sent to one processing unit, multiple processing units are prevented from competing for the same interrupt request, and the safety of the system is improved. Further, when a processing unit cannot process an interrupt request it currently receives, it may be forwarded to other processing units. Thereby improving flexibility in interrupt handling.
The complete flow of the interrupt processing method is described below with reference to fig. 4. The arrows in fig. 4 represent the leads used to transmit interrupt requests. The leads for transmitting other information are not shown.
In the first step, the graphics rendering sub-engine 31 issues an interrupt request (specifically, a level signal or a pulse signal) to the interrupt distributor 1 through a specific pin.
In a second step, the interrupt distributor 1 queries which of the interrupt controllers 21, 22, 23 the interrupt request should be sent to based on the interrupt routing information (which may specifically be an interrupt routing table stored in an internal memory of the interrupt distributor 1, or an interrupt routing register internal to the interrupt distributor 1). For example to the interrupt controller 22 of figure 4.
Third, the interrupt controller 22 sends an interrupt request to the system processor 43 (e.g., CPU) via the PCIe bus 5 (Generation I/O Interconnect).
Fourth, the system processor 43 accesses the interrupt controller 22 via the PCIe bus 5, thereby querying and determining that the interrupt source of the interrupt request is the graphics-rendering sub-engine 31.
Fifth, the system processor 43 accesses the graphics rendering sub-engine 31 via the PCIe bus 5, determines the cause of the interrupt request, and runs the corresponding interrupt handler.
Sixth, after the system processor 43 finishes processing the event of the interrupt request, it accesses the graphics-rendering sub-engine 31 and sets a specific register in the graphics-rendering sub-engine 31, thereby allowing the graphics-rendering sub-engine 31 to issue a new interrupt request.
Seventh, system processor 43 notifies interrupt controller 22 that the current interrupt request has been processed by setting a specific register within interrupt controller 22, i.e., allows interrupt controller 22 to send a new interrupt request to system processor 43.
Eighth, system processor 43 exits the interrupt handler and returns to its business process prior to processing the interrupt request.
Obviously, the first programmable processor 41 and the second programmable processor 42 do not contend for the interrupt request throughout the processing flow.
Further, the interrupt information can be updated by the processing unit.
For example, the second programmable processor 42 finding itself unable to process a currently accepted interrupt request would first mask the interrupt in the interrupt distributor 1, then modify the interrupt routing information of the interrupt source in the interrupt distributor 1 that issued the current interrupt request so that the interrupt information is directed to the system processor 43, and then open the interrupt. At this time, the interrupt request is sent to the interrupt controller 22 corresponding to the system processor 43, so that the forwarding of the interrupt is realized.
In some embodiments, referring to fig. 3, the interrupt handling method further comprises: step 201, an interrupt distributor receives an encryption key and locking information sent by a processing unit, stores the encryption key and locks the interrupt routing information corresponding to an interrupt source of an interrupt request currently processed by the processing unit when the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit is not locked; step 202, when receiving an encryption key sent by any processing unit and a request for modifying the interrupt routing information, the interrupt distributor compares the newly received encryption key with the stored encryption key corresponding to the interrupt routing information requested to be modified, and if the two are the same, allows the modification request of the interrupt routing information at this time; step 203, the interrupt distributor compares the newly received encryption key with the stored encryption key corresponding to the interrupt routing information requested to be modified, if the newly received encryption key and the stored encryption key are different, the interrupt distributor rejects the modification request of the interrupt routing information.
The interrupt routing information is locked, meaning that it can only be modified by the processing unit holding the same key, and cannot be modified if the other processing unit holds the wrong key.
When one processing unit is processing an interrupt request, other processing units cannot modify the interrupt routing information without knowing the current encryption key, and thus cannot contend for the interrupt request. This further improves the security of the system operation.
For example, when an attacker attempts to modify the interrupt routing information in a hacking attack, the attacker cannot modify the interrupt routing information because the attacker does not know what the current encryption key is.
Optionally, the interrupt processing method further includes: the interrupt distributor receives an encryption key and locking information sent by the processing unit, stores the encryption key under the condition that the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit is not locked, and locks the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit; the interrupt distributor receives an unlocking instruction which is sent by the processing unit and carries an encryption key, releases the locking state of the interrupt routing information under the condition that the received encryption key is the same as the stored encryption key corresponding to the interrupt routing information which is requested to be modified, and keeps the locking state of the interrupt routing information under the condition that the received encryption key is not the same as the stored encryption key.
For example, when a processing unit currently processing an interrupt request finds itself unable to process the interrupt request or should not process the interrupt request, it may actively unlock the interrupt routing information and modify it, so that other processing units may process the interrupt request.
For example, the system is hacked, and the control unit may fail to release the lock state of the interrupt routing information.
When the interrupt distributor rejects the modification of the intermediate disconnection routing information, it may choose to send the reject reason to the processing unit that initiated the modification, or may choose not to send the reject reason. It is more advantageous to defend against hacking if the reason for denial is not sent. Whether the processing unit attempting to modify the interrupt routing information sends a rejection reason may be configured in advance by the user.
The complete process of locking, unlocking and modifying the interrupt routing information is described below in conjunction with fig. 4.
First, the first programmable processor 41 receives an interrupt request from the graphics rendering sub-engine 31, locks an interrupt routing table (located in the interrupt distributor 1) corresponding to the graphics rendering sub-engine, and fills the interrupt distributor 1 with an encryption key. An interrupt routing table and a data bit indicating whether the interrupt routing table is locked are provided in the interrupt distributor 1 corresponding to the first programmable processor 41.
In the second step, the first programmable processor 41 enters an interrupt handler, and finds that the interrupt belongs to an abnormal interrupt and should be processed by the system processor.
Third, the first programmable processor 41 masks the interrupt in the interrupt distributor 1.
Fourth, the first programmable processor 41 uses its own encryption key to change the routing of the interrupt to the PCIe bus 5 and will modify the data bits indicating whether the routing information is locked, clearing the encryption key.
Fifth, the first programmable processor 41 enables the interrupt in the interrupt distributor 1 and the interrupt level will be forwarded to the PCIe bus 5.
Sixth, the first programmable processor 41 completes setting the interrupt controller 2 specific register (i.e., allows the interrupt controller 21 to send a new interrupt request to the first programmable processor 41), exiting the interrupt handler.
Seventh, the PCIe bus 5 receives the interrupt request, forwards it to the system processor 43, and the system processor 42 enters an interrupt processing flow.
In some embodiments, at least one interrupt controller simultaneously sends an interrupt request and an interrupt source ID of the interrupt request to a corresponding processing unit over different pins, respectively.
For example, referring to fig. 4, the interrupt controller 21 sends an interrupt request to the first programmable processor 41 while sending the corresponding interrupt source ID to the first programmable processor 41 through a separate pin, so that the first programmable processor 41 does not need to query the interrupt controller 21 for the interrupt source ID any more. The interrupt controller 22 needs to first send an interrupt request to the system processor 43 over the PCIe bus, and then the system processor 43 queries the interrupt controller 22 over the PCIe bus for which the interrupt source is.
In this manner, the manner in which each interrupt controller operates may be adaptively configured with the corresponding processing unit. Flexibility in the design of each interrupt controller is improved.
In some embodiments, the interrupt controller is also used for interrupt priority management. I.e. the interrupt controller will receive a plurality of interrupt requests in succession. The processing unit sets the priority of the interrupt source for the corresponding interrupt controller. The interrupt controller determines which of a plurality of interrupt requests input simultaneously is to be preferentially sent to the processing unit or determines a priority order of interrupt preemption based on the priority information.
Based on the same inventive concept as the foregoing embodiments, embodiments of the present application further provide an interrupt processing apparatus, referring to fig. 4, which includes: the interrupt distributor 1 is used for receiving an interrupt request from an interrupt source and sending the interrupt request to one of a plurality of interrupt controllers according to interrupt routing information corresponding to the interrupt source, wherein the number of the interrupt sources is multiple; the interrupt controllers 21, 22, and 23 are configured to send the received interrupt request to the corresponding processing units, and record an interrupt source corresponding to the interrupt request, so that the processing units execute an interrupt handler according to the interrupt request and an interrupt source ID, where the interrupt controllers correspond to the processing units one to one, and the interrupt route information can be updated by the processing units.
In some embodiments, the interrupt distributor 1 is further configured to: receiving an encryption key and locking information sent by a processing unit, storing the encryption key under the condition that interrupt routing information corresponding to an interrupt source of an interrupt request currently processed by the processing unit is not locked, and locking an interrupt routing register corresponding to the interrupt source of the interrupt request currently processed by the processing unit; and under the condition of receiving the encryption key sent by any processing unit and the request for modifying the interrupt routing information, comparing the newly received encryption key with the stored encryption key corresponding to the interrupt routing information requested to be modified, if the newly received encryption key and the stored encryption key are the same, allowing the modification request of the interrupt routing information at this time, and otherwise rejecting the modification request of the interrupt routing information at this time.
In some embodiments, the interrupt distributor 1 is further configured to: receiving an encryption key and locking information sent by the processing unit, storing the encryption key and locking an interrupt routing register corresponding to an interrupt source of an interrupt request currently processed by the processing unit under the condition that the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit is not locked; and receiving an unlocking instruction which is sent by the processing unit and carries an encryption key, releasing the locking state of the interrupt routing information under the condition that the received encryption key is the same as the stored encryption key corresponding to the interrupt routing information which is requested to be modified, and keeping the locking state of the interrupt routing information under the condition that the received encryption key is not the same as the stored encryption key corresponding to the interrupt routing information which is requested to be modified.
In some embodiments, at least one interrupt controller 21, 22, 23 is configured to: at least one interrupt controller simultaneously sends an interrupt request and an interrupt source ID of the interrupt request to a corresponding processing unit through different leads, respectively.
In some embodiments, the interrupt controllers 21, 22, 23 are also used for interrupt priority management.
Referring to fig. 4, an embodiment of the present application further provides an electronic device, including a plurality of interrupt sources and a plurality of processing units, and the interrupt handling apparatus of the foregoing embodiment, wherein an interrupt distributor 1 in the interrupt handling apparatus is connected to the plurality of interrupt sources to receive interrupt requests from the plurality of interrupt sources; the interrupt controllers 21, 22, 23 in the interrupt processing device correspond to the processing units one by one, so that the processing units execute interrupt processing programs according to the interrupt requests and the interrupt source IDs.
In some embodiments, the electronic device includes a separate graphics card, the plurality of interrupt sources are respectively different sub-engines (for example, the graphics rendering sub-engine 31, the video codec sub-engine 32, the display control sub-engine 33, and the audio sub-engine 34) in the separate graphics card, and the plurality of processing units include a general-purpose CPU connected to the separate graphics card and a programmable processor in the separate graphics card.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments.
The protective scope of the present application is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present application by those skilled in the art without departing from the scope and spirit of the present application. It is intended that the present application also include such modifications and variations as come within the scope of the appended claims and their equivalents.
Claims (14)
1. An interrupt processing method, comprising:
the method comprises the steps that an interrupt distributor receives an interrupt request from an interrupt source and sends the interrupt request to one of a plurality of interrupt controllers according to interrupt routing information corresponding to the interrupt source, wherein the number of the interrupt sources is multiple;
the interrupt controller sends a received interrupt request to a corresponding processing unit, records an interrupt source ID corresponding to the interrupt request, and enables the processing unit to execute an interrupt processing program according to the interrupt request and the interrupt source ID, wherein the interrupt controller corresponds to the processing unit one by one, and the interrupt route information can be updated by the processing unit.
2. The interrupt processing method of claim 1, further comprising:
the interrupt distributor receives an encryption key and locking information sent by the processing unit, stores the encryption key under the condition that the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit is not locked, and locks the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit;
and the interrupt distributor compares the newly received encryption key with the stored encryption key corresponding to the interrupt routing information requested to be modified under the condition of receiving the encryption key sent by any processing unit and the request for modifying the locked interrupt routing information, if the newly received encryption key and the stored encryption key are the same, the request for modifying the interrupt routing information at the current time is allowed, and otherwise, the request for modifying the interrupt routing information at the current time is rejected.
3. The interrupt processing method according to claim 2, wherein it is configurable whether or not the interrupt distributor sends back the reply information to the processing unit which issued the present interrupt route information modification request after rejecting the modification request of the present interrupt route information.
4. The interrupt processing method of claim 1, further comprising:
the interrupt distributor receives an encryption key and locking information sent by the processing unit, stores the encryption key under the condition that the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit is not locked, and locks the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit;
the interrupt distributor receives an unlocking instruction which is sent by the processing unit and carries an encryption key, releases the locking state of the interrupt routing information under the condition that the received encryption key is the same as the stored encryption key corresponding to the interrupt routing information which is requested to be modified, and keeps the locking state of the interrupt routing information under the condition that the received encryption key is not the same as the stored encryption key corresponding to the interrupt routing information which is requested to be modified.
5. The interrupt processing method according to claim 1, wherein at least one interrupt controller simultaneously sends an interrupt request and an interrupt source ID of the interrupt request to the corresponding processing unit through different wires, respectively.
6. The interrupt processing method of claim 1, wherein the interrupt controller is further configured for interrupt priority management.
7. An interrupt processing apparatus, comprising:
the interrupt distributor is used for receiving an interrupt request from an interrupt source and sending the interrupt request to one of a plurality of interrupt controllers according to interrupt routing information corresponding to the interrupt source, wherein the number of the interrupt sources is multiple;
and the interrupt controller is used for sending the received interrupt request to a corresponding processing unit and recording an interrupt source corresponding to the interrupt request so that the processing unit can execute an interrupt processing program according to the interrupt request and the interrupt source ID, wherein the interrupt controller is in one-to-one correspondence with the processing unit, and the interrupt route information can be updated by the processing unit.
8. The interrupt handling apparatus of claim 7, wherein the interrupt distributor is further configured to:
receiving an encryption key and locking information sent by the processing unit, storing the encryption key and locking an interrupt routing register corresponding to an interrupt source of an interrupt request currently processed by the processing unit under the condition that the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit is not locked;
and under the condition of receiving the encryption key sent by any processing unit and a request for modifying the locked interrupt routing information, comparing the newly received encryption key with the stored encryption key corresponding to the interrupt routing information requested to be modified, if the two are the same, allowing the modification request of the interrupt routing information at this time, and otherwise rejecting the modification request of the interrupt routing information at this time.
9. The interrupt processing apparatus according to claim 8, wherein it is configurable whether or not the interrupt distributor sends back the reply information to the processing unit which issued the present interrupt route information modification request after rejecting the modification request of the present interrupt route information.
10. The interrupt handling apparatus of claim 7, wherein the interrupt distributor is further configured to:
receiving an encryption key and locking information sent by the processing unit, storing the encryption key and locking an interrupt routing register corresponding to an interrupt source of an interrupt request currently processed by the processing unit under the condition that the interrupt routing information corresponding to the interrupt source of the interrupt request currently processed by the processing unit is not locked;
and receiving an unlocking instruction which is sent by the processing unit and carries an encryption key, releasing the locking state of the interrupt routing information under the condition that the received encryption key is the same as the stored encryption key corresponding to the interrupt routing information which is requested to be modified, and keeping the locking state of the interrupt routing information under the condition that the received encryption key is not the same as the stored encryption key corresponding to the interrupt routing information which is requested to be modified.
11. The interrupt processing apparatus of claim 7, wherein at least one interrupt controller is configured to: and simultaneously sending the interrupt request and the interrupt source ID of the interrupt request to the corresponding processing unit through different leads respectively.
12. The interrupt processing apparatus of claim 7, wherein the interrupt controller is further configured for interrupt priority management.
13. An electronic device comprising a plurality of interrupt sources and a plurality of processing units and an interrupt handling apparatus according to any of claims 7 to 12, an interrupt distributor in the interrupt handling apparatus connecting the plurality of interrupt sources to receive interrupt requests from the plurality of interrupt sources; the interrupt controllers in the interrupt processing device correspond to the processing units one by one, so that the processing units execute interrupt processing programs according to the interrupt requests and the interrupt source IDs.
14. The electronic device according to claim 13, wherein the electronic device comprises an independent graphics card, the plurality of interrupt sources are respectively different sub-engines in the independent graphics card, and the plurality of processing units comprise a general-purpose CPU connected to the independent graphics card and a programmable processor in the independent graphics card.
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| CN103765376A (en) * | 2011-06-16 | 2014-04-30 | 柯斯提克绘图公司 | Graphics processor with non-blocking concurrent architecture |
| CN110659458A (en) * | 2019-10-10 | 2020-01-07 | 陈昶宇 | Central processor design method supporting software code data secret credible execution |
| CN113238802A (en) * | 2021-05-28 | 2021-08-10 | 上海阵量智能科技有限公司 | Interrupt distributor, data processing chip, interrupt distribution method and data processing method |
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| CN1589431A (en) * | 2001-11-15 | 2005-03-02 | 英特尔公司 | Method and system for concurrent handler execution in a SMI and PMI-based dispatch-execution framework |
| US20080040524A1 (en) * | 2006-08-14 | 2008-02-14 | Zimmer Vincent J | System management mode using transactional memory |
| CN103765376A (en) * | 2011-06-16 | 2014-04-30 | 柯斯提克绘图公司 | Graphics processor with non-blocking concurrent architecture |
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