CN113608785A - Processor core, processor and instruction processing method - Google Patents
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
Abstract
The application discloses a processor core, a processor and an instruction processing method. The processor core includes: the instruction fetching unit is used for obtaining an instruction, and the instruction at least comprises a first operation code; a decode unit to decode the instruction; and the execution unit is used for executing the instruction according to the decoding result of the decoding unit, wherein the decoding unit converts the first operation code based on at least one lookup table to obtain a second operation code, and each lookup table represents the corresponding relation between the first operation code and at least one bit of data in the second operation code. In a plurality of different processor cores, different first operation codes and lookup tables can be used for obtaining the same second operation code, so that the data confidentiality is greatly improved, and the data is prevented from being decompiled.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a processor core, a processor, and an instruction processing method.
Background
A Central Processing Unit (CPU) is one of the main devices in a computer, and is used for performing tasks such as data Processing, computer instruction Processing, and program Processing. The CPU architecture is a specification to which the CPU complies, and in a general CPU architecture, execution of an instruction generally includes processes of fetch (fetch), Decode (Decode), Execute (Execute), and Write back (Write back).
The existing CPU architecture still needs to be improved to further improve its security.
Disclosure of Invention
The present disclosure is directed to a processor core, a processor and an instruction processing method.
According to a first aspect of the present invention, there is provided a processor core comprising: the instruction fetching unit is used for obtaining an instruction, and the instruction at least comprises a first operation code; a decode unit to decode the instruction; and the execution unit is used for executing the instruction according to the decoding result of the decoding unit, wherein the decoding unit converts the first operation code based on at least one lookup table to obtain a second operation code, and each lookup table represents the corresponding relation between the first operation code and at least one bit of data in the second operation code.
Optionally, the number of the lookup tables is related to the number of bits of the second operation code and the corresponding relationship between at least one bit of data in the first operation code and the second operation code.
Optionally, when the lookup table represents a corresponding relationship between one bit of data in the first operation code and the second operation code, the number of the lookup table is the same as the number of bits of the second operation code.
Optionally, the decoding unit includes: the lookup table module comprises a storage module and a logic module, the storage module stores at least one lookup table, the logic module is used for receiving the first operation code and converting the first operation code based on the at least one lookup table to obtain the second operation code, and the first operation code and the second operation code are in one-to-one correspondence; and the decoding module is used for decoding the second operation code.
Optionally, each of the lookup tables is not identical, so that the correspondence between the at least one bit of data of the first operation code and the at least one bit of data of the second operation code included in each of the lookup tables are not identical.
Optionally, the at least one lookup table is selected from a predetermined combination table, and the number of kinds of the predetermined combination table is related to the number of bits of the second operation code, the number of kinds of the used second operation code, and the correspondence between at least one bit of data in the first operation code and the second operation code.
Optionally, the lookup table module is configured to be programmable, the at least one lookup table is written to the lookup table module via a fuse, and the fuse is blown after all of the at least one lookup table is written to the memory module.
Optionally, each lookup table in the storage module represents a corresponding relationship between different bits of data in the second operation code obtained by the first operation code, and the logic module integrates the different bits of data obtained based on each lookup table to obtain the second operation code.
Optionally, the number of bits of the first operation code and the second operation code is N, each of the lookup tables in the storage module is binary data representing a correspondence between one-bit data in the first operation code and one-bit data in the second operation code, the logic module includes N-level data selectors, where a first-level data selector selects half of the binary data as output data based on the first-bit data of the first operation code, and each subsequent-level data selector outputs half of output data of a previous-level data selector as output data of the previous-level data selector based on corresponding bit data of the first operation code until an nth-level data selector outputs one-bit data in the second operation code.
Optionally, the method further includes: a selection unit, connected to the processor cores, wherein when the processor cores are multiple, the selection unit of each processor core is configured to select a non-repeating one of predetermined combination tables as the at least one lookup table, so that when multiple processor cores obtain the same second operation code, the selection unit receives different first operation codes; and/or when a plurality of the processor cores receive the same first operation code, the processor cores acquire different second operation codes.
According to a second aspect of the invention, there is provided a processor comprising: a processor core as described above.
According to a third aspect of the present invention, there is provided an instruction processing method comprising: receiving an instruction, wherein the instruction at least comprises a first operation code; converting the first operation code based on at least one lookup table to obtain a second operation code, and decoding the second operation code; and executing the instruction according to the decoding result, wherein each lookup table represents the corresponding relation between at least one bit of data in the first operation code and the second operation code.
Optionally, the number of the lookup tables is related to the number of bits of the second operation code and the corresponding relationship between at least one bit of data in the first operation code and the second operation code.
Optionally, when the lookup table represents a corresponding relationship between one bit of data in the first operation code and the second operation code, the number of the lookup table is the same as the number of bits of the second operation code.
Optionally, the lookup tables are not identical, so that the correspondence between the first operation code and the at least one bit of data of the second operation code included in each lookup table is not identical.
Optionally, the at least one lookup table is selected from a predetermined combination table, the number of the predetermined combination table is related to the number of bits of the second operation code, the number of kinds of the used second operation code, and the correspondence between at least one bit of data in the first operation code and the second operation code.
Optionally, when the plurality of processor cores execute the instruction processing method, each processor core selects a non-repeating one of the predetermined combination tables as at least one lookup table when executing the instruction processing method, and when the plurality of processor cores obtain the same second operation code, each processor core receives different first operation codes; and/or when a plurality of processor cores receive the same first operation code, each processor core acquires a different second operation code.
By adopting the technical scheme of the application, different coding modes can be customized in different devices, the decompiling of the instructions can be avoided, and the confidentiality and the safety of the computer are greatly improved.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic diagram of a computer system according to an embodiment of the present disclosure;
FIG. 2 shows a schematic diagram of a processor core, according to an embodiment of the present disclosure;
FIG. 3 illustrates a schematic diagram of an exemplary lookup table module in accordance with embodiments of the present disclosure;
FIG. 4 shows a flow diagram of an instruction processing method according to an embodiment of the disclosure.
Detailed Description
The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
It should be understood that, in the embodiments of the present application, a and B are connected, which means that a and B may be connected in series or in parallel, or a and B are connected through other devices, and the embodiments of the present application are not limited thereto.
A Central Processing Unit (CPU) is one of the main devices in a computer, and is used for performing tasks such as data Processing, computer instruction Processing, and program Processing. The CPU architecture is a specification to which the CPU complies, and in a general CPU architecture, an execution instruction generally includes processes of fetch (fetch), Decode (Decode), Execute (Execute), and Write back (Write back). Specifically, fetching is a process of fetching an instruction from a memory to an instruction register, decoding is a process of parsing the instruction into information that can be executed by a computer execution logic unit, executing is a process of loading the information acquired in the decoding stage to the execution logic unit for execution, and writing back is a process of putting back the processing result data of the execution stage to a place (for example, a certain memory module) designated by the instruction.
The instructions executed by the CPU generally include an opcode portion, an operand portion, and the like, where the opcode portion is used to express operations of the instruction that need to be performed, such as addition, subtraction, data movement, and the like, and the length of the opcode portion in the instruction is fixed, that is, the number of bits (bits) of the opcode portion is the same for different instructions. In the related art CPU implementation logic, the operation code part is generally processed by a decoding module (e.g., a decoder) to convert the operation code into a selection signal of the arithmetic logic unit of the processor, so as to implement the control from the operation code to the arithmetic processing unit.
In the related art, for the decoding modules of computers with the same architecture (for example, x86 architecture, ARM architecture, etc.), the encoding manner of the opcodes of the instruction set that can be analyzed is fixed, that is, only one type of opcode corresponds to one type of function instruction, and cannot be changed. For example, if the opcode of the add instruction is binary 0110 and the opcode of the subtract instruction is 1001 for a CPU of a certain architecture, then all machines using the CPU will perform the operations of adding the instruction receiving the binary 0110 opcode and subtracting the instruction receiving the binary 1001 opcode, which is fixed. This results in a computer software binary in which all the instructions and code correspondences are open, and thus the binary is easily decompiled, i.e., reverse engineered. By reverse engineering, a competitor or hacker can obtain the internal logic of the software, so that the software is easy to copy and even hack. Even though privacy is improved in some related art CPU architectures, which typically employ an improved way of software programming, there is still a risk of decompilation.
The inventors of the present application have found the above-mentioned problems of the computer and have provided a further improved processor core, processor, and instruction processing method.
The processor core, the processor and the instruction processing method provided by the application can be applied to various CPU architectures, such as an X86 architecture, an ARM architecture and the like, and can basically realize that each computer executes different operation code encoding modes. Taking the addition operation as an example, the opcode may be binary 0110, 1001, or 1100, as long as the opcodes satisfying different instructions are not duplicated.
Embodiments of a processor core, a processor, and an instruction processing method provided in the present application will be described below with reference to the accompanying drawings.
FIG. 1 shows a schematic diagram of a computer system according to an embodiment of the present disclosure.
The computer system comprises, for example, a processor 10 and a memory 20, which are connected via a data bus between the processor 10 and the memory 20. Processor 10 includes a processor core 100, and processor core 100 is a core component for computing, receiving instructions, and processing data, the instructions being stored in memory 20, for example. Processor core 100 includes an instruction fetch unit 110, a decode unit 120, and an execution unit 130.
Instruction fetch unit 110 is configured to receive an instruction, which includes, for example, an operand and a first opcode. The decoding unit 120 is configured to decode the instruction, and during the decoding process, the decoding unit 120 converts the first operation code based on at least one lookup table to obtain a second operation code, where each lookup table represents a corresponding relationship between at least one bit of data in the first operation code and the second operation code. The execution unit 130 is used for executing instructions according to the decoding result of the decoding unit 120.
In the embodiment of the present disclosure, the "first operation code" included in the instruction adopts a specially-made encoding manner of the present disclosure, the decoding unit 120 converts the specially-made "first operation code" into a "second operation code", and the "second operation code" adopts a conventional operation code encoding manner, thereby improving the security and confidentiality of the computer system. Furthermore, each first operation code and each second operation code in the embodiments of the present disclosure correspond to each other one to one, the corresponding relationship between the first operation code and the second operation code is stored in a lookup table, the lookup table is stored in a hardware memory, and the hardware memory further enhances the security and the confidentiality of the computer system compared to software programming.
In other embodiments, similarly, the lookup table may also store a tailored encoding of the relevant operand. For example, during the manufacturing process of the processor core, the corresponding relation between the second operand of the conventional encoding mode and the first operand of the characteristic encoding mode is stored in the lookup table, and during the later decoding process, the instruction containing the first operand is received, and the first operand in the instruction is converted into the second operand, so that the confidentiality of the computer system can be further improved.
The present disclosure provides a processor 10 that is suitable for use in a variety of processor architectures, such as the X86 architecture, the ARM architecture, and the like, and has good security and safety. In the manufacturing process of the processor, at least one lookup table is written into the processor by using the fuse in the programming channel, and after the writing of the lookup table is completed, the fuse is blown. The processor includes, for example, a processor core shown in fig. 2 (only the decoding unit 120 included in the processor core is shown in fig. 2) or a device for executing the instruction processing method shown in fig. 4, and details of the processor core 100 and the instruction processing method are not described herein again.
It should be understood that in other embodiments of the present disclosure, some of the components shown in fig. 1 may be omitted or the connections between the components may be implemented in different architectures, and some hardware and/or software modules not shown in fig. 1 may also be included, for example, components such as an instruction prefetch module may also be included, and two or more components shown in fig. 1 may also be combined into one component on a software architecture and/or a hardware architecture.
FIG. 2 shows a schematic diagram of a processor core, according to an embodiment of the present disclosure; FIG. 3 illustrates a schematic diagram of an exemplary lookup table module in accordance with embodiments of the present disclosure. For clarity, only a schematic diagram of the decode module 122 in the processor core is shown in fig. 2.
In the disclosed embodiments, processor core 100 is configured to receive an instruction, decode the instruction, and execute the instruction according to the decoded result. Specifically, in the process of decoding the first operation code included in the instruction, the second operation code is obtained according to the first operation code, and the second operation code is decoded. The first operation code adopts a specially-made coding mode in the disclosure, the second operation code adopts a conventional operation code coding mode, each first operation code corresponds to each second operation code one by one, and the corresponding relation of the first operation code and the second operation code is stored in a lookup table. For the same second opcode, the first opcode corresponding to the same second opcode in each processor core 100 is unique, for example, the conventional second opcode representing an add instruction is 0110, the first opcode corresponding to the second opcode 0110 in the first processor core provided by the present application is 1100, the first opcode corresponding to the second opcode 0110 in the second processor core provided by the present application is 1010, the first opcode corresponding to the second opcode 0110 in the third processor core provided by the present application is 1001, and so on, the first opcode corresponding to the second opcode 0110 in each processor core is different.
The following takes the processor core 100 shown in fig. 2 as an example to describe in detail a specific implementation of the processor core according to the embodiment of the present disclosure.
The processor core 100 includes a lookup table module 121 and a decoding module 122, where the lookup table module 121 stores at least one lookup table, and the lookup table module 121 is configured to receive the first operation code and convert the first operation code based on the at least one lookup table to obtain a second operation code; and the decoding module 122 is configured to perform decoding processing on the second operation code. In each lookup table module 121, each lookup table represents a corresponding relationship between at least one bit of data in the first operation code and the second operation code. The method and the device utilize a plurality of lookup tables to represent the corresponding relation between at least one bit of data in the first operation code and the second operation code, so that the same second operation code can correspond to a plurality of different combinations of the first operation code and the lookup tables, different coding modes can be customized in different processor cores 100, and the confidentiality and the safety of a computer are greatly improved.
The lookup table module comprises at least one lookup table selected from a predetermined combination table, wherein the type number of the predetermined combination table is related to the bit number of the second operation code, the type number of the second operation code, and the corresponding relationship between at least one bit of data in the first operation code and the second operation code. The processor provided by the embodiment of the disclosure further comprises a selection unit, the selection unit is connected to the processor cores, the number of the selection unit corresponds to the number of the processor cores, when the processor comprises a plurality of processor cores, the processing unit of each processor core selects a non-repeating one of the predetermined combination tables as at least one lookup table of the processor core, so that when the plurality of processor cores acquire the same second operation code, the processor receives different first operation codes; and/or when multiple processor cores receive the same first opcode, they obtain a different second opcode.
Taking RISC-V32 instruction set as an example, the number of bits of the operation code (equivalent to the second operation code mentioned in the present disclosure) of the instruction is 7 bits, that is, the instruction set theoretically supports 128 kinds of operation codes, and then in the processor core 100 provided in the present disclosure, if 128 kinds of second operation codes are used and the lookup table represents the corresponding relationship between the first operation code and the one-bit data in the second operation code, the predetermined combination table of the present disclosure will have 128 factorial combinations, which reaches 125 th power order of 10, the cracking difficulty is quite large, and the encoding modes of each processor core 100 are basically different.
Optionally, the number of the lookup tables is related to the number of bits of the second operation code and a corresponding relationship between at least one bit of data in the first operation code and the second operation code, and when the lookup tables represent the corresponding relationship between one bit of data in the first operation code and the second operation code, the number of the lookup tables stored in the lookup table module 121 is the same as the number of bits of the second operation code. For example, if the bit number of the second operation code is 4 bits, and the first operation code corresponds to one bit of data in the second operation code, 4 lookup tables are stored in the lookup table module 121; if the bit number of the second operation code is 4 bits and the first operation code corresponds to two bits of data in the second operation code, 2 lookup tables are stored in the lookup table module 121. It should be understood that the smaller the number of data bits in the first opcode corresponding to the second opcode, the better the security of the processor core 100, and in practical operation, for example, to take into account parameters such as operating speed, each lookup table may also represent the corresponding relationship between the multiple bits of data in the first opcode and the second opcode.
As an example, the lookup table module 121 provided by the embodiment of the present disclosure is configured to be programmable, at least one lookup table is written into the lookup table module 121 via a fuse, and after all of the at least one lookup table is written into the lookup table module 121, the fuse is blown. Furthermore, the fuse is unrecoverable after being fused, so that the fuse cannot be accessed by any other method of the system except the processor core 100 (decoder) after the writing of the lookup table is completed, and the confidentiality and the safety of the device are further improved.
In this example, the look-up table module 121 includes, for example: a storage module 121a, configured to store at least one lookup table; and a logic module 121b, configured to receive the first operation code, and convert the first operation code based on at least one lookup table to obtain a second operation code, where the first operation code and the second operation code correspond to each other one to one. For example, each lookup table in the storage module 121a represents the first operation code to obtain the corresponding relationship of different bits of data in the second operation code, and the logic module 123 integrates the different bits of data obtained based on each lookup table to obtain the second operation code.
Optionally, the lookup tables included in the storage module 121a are not identical, so that the corresponding relationship between at least one bit of data of the first operation code and the second operation code included in each lookup table is not identical. For example, the first lookup table included in the memory module 121a is as shown in fig. 3, and the first lookup table is "1110010100011001", then the truth table (i.e. the corresponding relationship between one bit of data of the first operation code and the second operation code) of the first lookup table is as shown in table 1.
Table 1:
if the second lookup table is set to "1100011101100011", it corresponds to a truth table different from table 1, and so on, and the respective lookup tables included in the memory module 121a are not set to be identical, the correspondence relationship between at least one bit of data of the first operation code and the second operation code included in the respective lookup tables is not identical.
The storage module 121a is, for example, selected from any One of a One Time Programmable (OTP) Memory, a non-volatile Electrically Erasable Programmable Read-Only Memory (EEPROM), a non-volatile flash Memory (flash) or a Random Access Memory (RAM).
The logic module 121b includes, for example, a multi-stage data selector, and the plurality of lookup tables in the memory module 121a may share the multi-stage data selector in one logic module 121b, for example, the logic module 121b receives different lookup tables at different stages by using an enable signal. For example, referring to fig. 3, when the number of bits of the first operation code is N, in order to characterize the corresponding relationship between the one-bit data of the first operation code and the one-bit data of the second operation code, the lookup table includes 2NIf the logic module 121b contains N levels of data selectors, the enable terminals of the data selectors at each level respectively receive each bit of data of the first operation code, so as to complete the data selection function, and finally output the one-bit data of the second operation code corresponding to the first operation code. Specifically, the first level data selector includes 2N-1A plurality of data selectors, each of the data selectors receiving in sequence 2NBinary number of digits, 2 in the second level data selectorN-2And each data selector receives the data selected by the first-stage data selector in sequence, and so on until outputting the one-bit data of the second operation code corresponding to the first operation code.
Taking a 4-bit opcode instruction system as an example, assuming that the opcode of the original normal add instruction is binary 0110 in the CPU architecture followed by the processor core, after processing by the encoding method provided by the present disclosure, the lookup table module 121 may convert the first opcode 1100 into the second opcode 0110 if the binary 1100 is assigned to the first opcode of the add instruction on the processor core 100 shown in fig. 2. Specifically, in this example, the number of bits of the first operation code and the second operation code is 4, and each lookup table represents a corresponding relationship between one bit of data of the first operation code and one bit of data of the second operation code, so that the storage module 121a includes the first to fourth lookup tables. In the first lookup table (as shown in fig. 3), the first operation code 1100 corresponds to the first bit data 0 of the second operation code, in the second lookup table, the first operation code 1100 corresponds to the second bit data 1 of the second operation code, in the third lookup table, the first operation code 1100 corresponds to the third bit data 1 of the second operation code, and in the fourth lookup table, the first operation code 1100 corresponds to the fourth bit data 0 of the second operation code. The logic module 121b integrates the first to fourth bits of data obtained from the lookup table, so as to obtain the complete second opcode 0110.
The processor core of the embodiment of the disclosure utilizes the plurality of lookup tables to represent the corresponding relationship between at least one bit of data in the first operation code and the second operation code, so that the random encoding of the computer instruction can be realized in different processor cores, the confidentiality and the safety of the computer are greatly improved, and the decompilation of the computer is avoided. Furthermore, the safety problem of computer software is solved by using a hardware scheme, the uniqueness of the circuit board can be ensured, the same technical effect as the embodiment of the disclosure cannot be achieved even if the circuit board is copied, the safety of the computer can be further ensured, and the copyright of the circuit can be effectively protected.
Some examples of the processor core of the embodiments of the present disclosure are described above, however, the embodiments of the present disclosure are not limited thereto, and there may be other extensions and variations.
For example, the processor core 100 may further include a receiving unit (not shown) for receiving data, and the receiving unit 100 receives a computer instruction, divides the computer instruction into an operand and a first opcode, and sends the first opcode to the lookup table module 121 for further processing.
For another example, the processor core 100 may be a discrete device, may be a circuit unit, or may be a module in a computer. In other implementations, the aforementioned processor core 100 may be packaged in a device.
FIG. 4 shows a flow diagram of an instruction processing method according to an embodiment of the disclosure. The instruction processing method includes steps S1 to S3.
In step S1, an instruction is received, the instruction including at least a first opcode. In this step, optionally, after receiving the computer instruction, the computer instruction is divided into an operand and a first opcode.
In step S2, the first operation code is converted based on at least one lookup table to obtain a second operation code, and the second operation code is decoded, wherein each lookup table represents a corresponding relationship between the first operation code and at least one bit of data in the second operation code.
The method and the device utilize a plurality of lookup tables to represent the corresponding relation between at least one bit of data in the first operation code and the second operation code, so that the same second operation code can correspond to the first operation code and the lookup tables of a plurality of different combinations, thereby realizing different coding modes customized in different devices for executing instruction processing methods, and greatly improving the confidentiality and the safety of a computer.
The at least one lookup table used in this step is selected from a predetermined combination table, the number of types of the predetermined combination table being related to the number of bits of the second operation code, the number of types of the second operation code used, and a correspondence between at least one bit of data in the first operation code and the second operation code. When the instruction processing method is executed in a plurality of devices, at least one lookup table in the instruction processing method executed by the plurality of devices is selected from a non-repeating one in a preset combination table, and when the same second operation code is obtained, different first operation codes are received; and/or obtain a different second opcode when the same first opcode is received.
Optionally, the number of the lookup tables is related to the number of bits of the second operation code and a corresponding relationship between at least one bit of data in the first operation code and the second operation code, for example, the number of the lookup tables is the same as the number of bits of the second operation code. When the lookup table represents the corresponding relation between the first operation code and the one-bit data in the second operation code, the number of the lookup table is the same as the number of bits of the second operation code. For example, if the bit number of the second operation code is 4 bits, and the first operation code corresponds to one bit of data in the second operation code, 4 lookup tables are stored in the lookup table module 121; if the second opcode has 4 bits and the first opcode corresponds to two bits of data in the second opcode, then 2 lookup tables are used in this step. It should be understood that the smaller the number of data bits in the first opcode corresponding to the second opcode, the better the security of the instruction processing method, and in actual operation, for example, in order to take into account parameters such as operating speed, each lookup table may also represent the corresponding relationship between the multiple bits of data in the first opcode and the second opcode.
Optionally, the lookup tables used in this step are not identical, so that the correspondence between at least one bit of data of the first operation code and at least one bit of data of the second operation code included in each lookup table are not identical.
Taking an instruction system with 4-bit operation codes as an example, assuming that in a CPU architecture followed by the instruction processing method, the operation code of the original normal addition instruction is binary 0110, after being processed by the encoding method provided by the present disclosure, the binary 1100 allocated to the first operation code of the addition instruction is converted into the second operation code 0110 by this step. Specifically, in this example, the number of bits of the first operation code and the second operation code is 4, and each lookup table represents a corresponding relationship between one bit of data of the first operation code and one bit of data of the second operation code, this step includes the first to fourth lookup tables. In the first lookup table (as shown in fig. 3), the first operation code 1100 corresponds to the first bit data 0 of the second operation code, in the second lookup table, the first operation code 1100 corresponds to the second bit data 1 of the second operation code, in the third lookup table, the first operation code 1100 corresponds to the third bit data 1 of the second operation code, and in the fourth lookup table, the first operation code 1100 corresponds to the fourth bit data 0 of the second operation code. Then, the first to fourth bits of data obtained from the lookup table are integrated, so as to obtain the complete second operation code 0110.
The instruction processing method of the embodiment of the disclosure uses the plurality of lookup tables to represent the corresponding relationship between at least one bit of data in the first operation code and the second operation code, so that the random encoding of the computer instruction can be realized in different devices for executing the instruction processing method, the confidentiality and the security of the computer are greatly improved, and the decompilation of the computer is avoided.
And then, decoding the second operation code. Since the first operation code customized by the present disclosure has been converted into the second operation code of the conventional encoding manner, the second operation code can be decoded in the conventional manner, and the present disclosure does not limit the decoding manner of the second operation code.
In step S3, the instruction is executed according to the decoding result.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the disclosed embodiments, as described above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, to thereby enable others skilled in the art to best utilize the disclosure and various modifications as are suited to the particular use contemplated. The present disclosure is to be limited only by the claims and their full scope and equivalents.
Claims (17)
1. A processor core, comprising:
the instruction fetching unit is used for obtaining an instruction, and the instruction at least comprises a first operation code;
a decode unit to decode the instruction; and
an execution unit to execute the instruction according to a decoding result of the decoding unit,
the decoding unit converts the first operation code based on at least one lookup table to obtain a second operation code, wherein each lookup table represents a corresponding relationship between the first operation code and at least one bit of data in the second operation code.
2. The processor core of claim 1, wherein the number of lookup tables is related to the number of bits of the second opcode and the correspondence between the at least one bit of data in the first opcode and the second opcode.
3. The processor core of claim 3, wherein the number of the lookup tables is the same as the number of bits of the second opcode when the lookup tables characterize a correspondence between one bit of data in the first opcode and the second opcode.
4. The processor core of claim 1, wherein the decode unit comprises:
the lookup table module comprises a storage module and a logic module, the storage module stores at least one lookup table, the logic module is used for receiving the first operation code and converting the first operation code based on the at least one lookup table to obtain the second operation code, and the first operation code and the second operation code are in one-to-one correspondence; and
and the decoding module is used for decoding the second operation code.
5. The processor core of claim 4,
each of the look-up tables is not identical, so that the correspondence relationship between the at least one bit of data of the first operation code and the second operation code contained in each of the look-up tables is not identical.
6. The processor core of claim 4, wherein at least one lookup table is selected from a predetermined combination table, the number of categories of the predetermined combination table being related to the number of bits of the second opcode, the number of categories of the second opcode, and the correspondence between at least one bit of data in the first opcode and the second opcode.
7. The processor core of claim 4, wherein the lookup table module is configured to be programmable, wherein the at least one lookup table is written to the lookup table module via a fuse, and wherein the fuse is blown after the at least one lookup table is all written to the memory module.
8. The processor core of claim 4, wherein each lookup table in the storage module represents a correspondence relationship of different bits of data in the second operation code obtained by the first operation code, and wherein the logic module integrates the different bits of data obtained based on each lookup table to obtain the second operation code.
9. The processor core of claim 4 or 8, wherein the first operation code and the second operation code have N bits, wherein each of the look-up tables in the storage module is binary data representing a correspondence between one bit of data in the first operation code and the second operation code, wherein the logic module comprises an N-level data selector,
and the first-stage data selector selects half of the binary data as output data based on the first bit data of the first operation code, and each stage of data selector outputs half of the output data of the previous-stage data selector as the stage of output data based on the corresponding bit data of the first operation code until the Nth-stage data output device outputs one bit of data in the second operation code.
10. The processor core of claim 6, further comprising: a selection unit for selecting the selection unit,
when the processor cores are multiple, the selection unit of each processor core is used for selecting a non-repeated one of the preset combination tables as the at least one lookup table, so that when the processor cores acquire the same second operation code, each processor core receives different first operation codes; and/or
When the processor cores receive the same first operation code, the processor cores acquire different second operation codes.
11. A processor, comprising:
the processor core of any one of claims 1 to 10.
12. An instruction processing method, comprising:
receiving an instruction, wherein the instruction at least comprises a first operation code;
converting the first operation code based on at least one lookup table to obtain a second operation code, and decoding the second operation code; and
the instruction is executed according to the result of the decoding,
wherein each lookup table represents a correspondence between at least one bit of data in the first operation code and the second operation code.
13. The method of claim 12, wherein the number of lookup tables is related to the number of bits of the second opcode and the correspondence between the first opcode and at least one bit of data in the second opcode.
14. The method of claim 13, wherein the number of the lookup tables is the same as the number of bits of the second operation code when the lookup tables represent a correspondence between one bit of data in the first operation code and the second operation code.
15. The instruction processing method according to claim 12, wherein the respective lookup tables are not identical, so that the correspondence between the at least one bit of data of the first operation code and the at least one bit of data of the second operation code included in each of the lookup tables is not identical.
16. The method of claim 12, wherein the at least one lookup table is selected from a predetermined combination table, the number of predetermined combination tables being related to the number of bits of the second opcode, the number of categories of the second opcode, and the correspondence between the first opcode and at least one bit of data in the second opcode.
17. The instruction processing method according to claim 12, wherein when a plurality of processor cores execute the instruction processing method, each processor core selects a non-duplicate one of the predetermined combination tables as at least one lookup table when executing the instruction processing method,
when a plurality of processor cores acquire the same second operation code, each processor core receives different first operation codes; and/or
And when the plurality of processor cores receive the same first operation code, each processor core acquires a different second operation code.
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