CN113608769B - Method for parallel processing and self-upgrading based on multiple single-chip microcomputer - Google Patents
Method for parallel processing and self-upgrading based on multiple single-chip microcomputer Download PDFInfo
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Abstract
The invention provides a method based on multi-singlechip parallel processing and self-upgrading, which comprises the steps that after a self-checking flow program is confirmed, a main processor sends a query instruction to each auxiliary processor, the state of a program written in each auxiliary processor is sequentially queried, whether the current state of a system accords with upgrading standards is judged according to related data replied by the auxiliary processors, if yes, the main processor enters the upgrading flow, the upgrading program is sequentially written in each auxiliary processor through a data serial bus, after the success of writing the upgrading program in all the auxiliary processors is confirmed, the main processor enters the self-upgrading flow, after the main processor finishes writing the upgrading program, the auxiliary processors execute detection, and the whole upgrading flow can be finished after the writing of the upgrading program is confirmed to be correct. The invention can improve the stability of the software upgrading process of the modularized numerical control system, has high success rate of writing the system chip program, and reduces the complicated maintenance operation of the system user in the upgrading process.
Description
Technical Field
The invention relates to the technical field of industrial control, in particular to a method based on multi-singlechip parallel processing and self-upgrading.
Background
Along with the development of scientific information technology, the remote monitoring of the Internet of things is gradually and widely applied to various fields, and the working state of field equipment can be monitored at any time and any place through the technology of the Internet of things without field checking, so that the remote monitoring of the Internet of things is gradually and widely applied as a convenient and rapid communication mode. Meanwhile, due to the development and updating of technology, an unattended modern monitoring mode is gradually favored by customers, however, the systems are required to be updated and maintained regularly, the on-site updating can consume time and labor, and particularly, the construction is difficult due to high working strength and difficulty, and the problem is well solved by remote automatic updating.
Currently, with development of microcomputer technology and diversification of application functions, a single MCU (Micro Control Unit ) cannot meet the function or performance requirements, and most products currently choose to achieve higher performance and requirements by adopting a master-slave MCU (possibly including a plurality of slaves, which control multi-stage connection of a plurality of slaves).
However, when an upgrade is required to be performed on a program of the slave controller, the prior art cannot meet the upgrade requirement, and restricts the development of products. In particular, in the field of industrial control, a digital control system capable of flexibly configuring an upgrade function has not yet appeared, and no design scheme capable of optimizing and guaranteeing the system chip writing software upgrade process has been found.
Disclosure of Invention
The invention mainly aims to provide a multi-singlechip-based parallel processing and self-upgrading method which can improve the stability of a modularized numerical control system software upgrading process, can not cause downtime of equipment due to unexpected faults such as power failure and the like, and can ensure that the success rate of system chip program writing basically reaches 99.99% in principle, thereby reducing complicated maintenance operation in the system user upgrading process.
In order to achieve the main purpose, the invention provides a method based on parallel processing and self-upgrading of multiple single-chip microcomputer, which comprises that after determining to enter a self-checking flow program, a main processor sends a query instruction to each slave processor, sequentially queries the state of a program written in each slave processor, and judges whether the current state of a system meets upgrading standards according to relevant data replied by the slave processor; if the judgment result is yes, the main processor enters a writing upgrading flow, and upgrading programs are written into the slave processors in sequence through the data serial bus; after confirming that the writing of the upgrade program by all the slave processors is successful, the master processor enters a self-upgrade flow, the slave processor performs detection after the writing of the upgrade program by the master processor is finished, and the whole upgrade flow can be finished after the writing of the upgrade program is confirmed to be correct; if the fault occurs in the upgrading process, the program of the slave processor is wrong, the slave processor can be simply upgraded again, if the fault occurs in the master processor, the master processor cannot be guided into the upgrading process correctly, the manual forced upgrading mode is adopted, the forced upgrading process is carried out on the master processor, and then the normal upgrading process is restored.
In a further scheme, when a self-checking flow program is entered, a main processor sends a query instruction through a communication data interface under the guidance of the program, the state of each slave processor writing the program is sequentially queried, and after the slave processor receives the query instruction sent by the main processor, the slave processor replies corresponding parameter values within a specified time and reports the information of the integrity, writing time, version and the like of the program in the current processor; wherein, judging whether the current system state accords with the upgrading standard comprises the following steps: and judging the current state of the system to determine whether the system enters an automatic upgrading process or normally enters the system.
In a further scheme, if the system enters an automatic upgrading process, reading data transmitted by an external data unit through a data communication interface, checking the read data, and temporarily storing the data in a RAM/FLASH ROM area of a main processor; after the external data is read, the main processor enters a downward writing upgrading flow, and the mode of simultaneously reading the upgrading data and upgrading the slave processor can be adopted in the processor of the low-capacity ROM/RAM; after the main processor enters a downward writing upgrading process, the output pin signal of the main processor resets a slave processor, so that the slave processor enters a writing process of an upgrading program, and the upgrading program is written into the slave processor through a data serial bus; after the upgrade program of the slave processor is written, a confirmed flag bit is replied through a data serial bus according to the program requirement, and after the confirmed flag bit is received by the master processor, the slave processor can be confirmed to be successfully upgraded, and the next upgrade writing flow of the slave processor is entered; if the main processor does not receive the determination flag bit, the main processor determines that the upgrade program writing fails, and the main processor writes the upgrade program for the slave processor again.
In a further scheme, after the first slave processor writes the upgrade program successfully, the master processor writes the upgrade program for the subsequent slave processors in turn, and after the last slave processor is upgraded successfully, the master processor jumps to the corresponding guide area and enters a self-upgrade flow; under the self-upgrading process, the main processor firstly performs erasing and writing work of the program area, and after ensuring that the writing of the program area is correct, performs program erasing and writing process in the boot area.
In a further scheme, the self-upgrade process specifically includes: after entering the self-upgrading process, the main processor sets an upgrading identifier, the identifier indicates that the self-upgrading program data of the data communication interface is required to be upgraded according to the program requirement in the guiding area, the self-upgrading program data is divided into two areas of guiding and program, the guiding area is upgraded firstly, the guiding area data is temporarily stored in the program area firstly, the guiding area is upgraded by a specific program preset in the program, after the guiding area is upgraded, the processor returns to the new guiding area, then the upgrading data of the program area is obtained, the program area is upgraded, and finally, after verification is completed, the upgrading identifier is cleared, so that the upgrading process of the whole system is completed.
In a further scheme, all the upgrade data can be encrypted in various ways and verified, decryption is carried out in the processor, and the consistency and confidentiality requirements of the data can be ensured;
If the main processor makes errors in the process of writing into the program area when the main processor performs self-upgrading, the system automatically gives an alarm, the whole system needs to be reset manually, when the system is powered on again, a boot area program in the main processor checks the integrity of the program area according to requirements, after confirming that the program writing fails, the self-upgrading process is performed again, the content of the upgrading program is read from the data communication interface, and the program area is erased and written again.
In a further scheme, if the upgrade slave processor makes errors in the process of writing the original boot area of the upgrade slave processor, the upgrade slave processor enters an abnormal mode, and executes a manual forced upgrade process to execute upgrade for the master processor again.
In a further scheme, after determining that the writing of the main processor fails and cannot be automatically recovered, entering a manual forced upgrade process: the equipment is powered off firstly, a reset key of the equipment is pressed, meanwhile, in order to ensure the accuracy of the forced state, an external key is pressed, the system is powered on again, and meanwhile, the system is kept for 3-5 seconds, at the moment, the main processor is in a reset state, and meanwhile, a reset pin of the main processor and a start pin of the auxiliary processor are triggered, so that the auxiliary processor judges that the main processor is forced to be reset and enters a take-over, and a manual forced upgrading process is entered.
In a further scheme, the slave processor obtains an upgrade program of the master processor through a communication data interface shared with the master processor, performs a mode similar to the master processor for upgrading the slave processor, performs forced upgrade on the master processor, takes over necessary hardware resources of the original master processor at the moment, and performs man-machine interaction processing through the slave processor.
Therefore, the invention adopts the multiprocessor sequential upgrade scheme to implement the upgrade process, one main flow processor in the multiprocessor is responsible for allocating upgrade resources, and the upgrade process can be ensured to be stable according to the capability of upgrading corresponding software by hardware functions for other slave processors.
If the program of the slave processor of the system is erased and written into the upgrading process, the upgrading interrupt is caused by the unexpected situation, the master processor can record an upgrading log, when the user upgrades the system again, the slave breakpoint is realized to continue upgrading the system, the master processor can perform self-upgrading only after all the slave processors are upgraded, and if the master processor is in error in the upgrading process, the slave processor which has completed upgrading can reversely take over the upgrading resource allocation task, and the upgrading process of the master processor is controlled again. Therefore, under the design of mutually taking over the upgrading task scheme, the brick changing condition caused by the failure of the system upgrading process can be completely eradicated.
Therefore, the method provided by the invention can effectively reduce the probability of system paralysis caused by chip writing failure due to unexpected power failure, circuit interference and the like in the upgrading process, greatly increase the convenience of maintenance of the modular numerical control system and reduce the maintenance cost.
In addition, the invention adopts the multiprocessor parallel working type design, so the capability of upgrading the corresponding software according to the hardware function can be realized, and all MCUs needing to be upgraded can be automatically upgraded only by providing an upgrade file for the main processor, each MCU does not need to be independently upgraded, the working time of operators is saved, and the time cost of the upgrade is reduced.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for parallel processing and self-upgrade based on multiple singlechips according to the present invention.
FIG. 2 is a schematic circuit diagram of an embodiment of a method for parallel processing and self-upgrade based on multiple singlechips.
The invention is further described below with reference to the drawings and examples.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, the following detailed description of the technical solution of the present invention refers to the accompanying drawings and specific embodiments. It should be noted that the described embodiments are only some embodiments of the present invention, and not all embodiments, and that all other embodiments obtained by persons skilled in the art without making creative efforts based on the embodiments in the present invention are within the protection scope of the present invention.
Referring to fig. 1 and 2, the method based on multi-singlechip parallel processing and self-upgrading comprises the following steps:
Firstly, executing step S1, entering a self-checking procedure, after determining that the self-checking procedure is entered, executing step S2, sending a query command to each slave processor by the master processor, sequentially querying the status of each slave processor in which the procedure is written, and executing step S3 according to the relevant data returned from the slave processor, to determine whether the current status of the system meets the upgrade standard.
If yes, executing step S4, enabling the main processor to enter a writing upgrading process, and sequentially writing upgrading programs for all the slave processors through the data serial bus.
After confirming that the writing of the upgrade program by all the slave processors is successful, executing step S5, enabling the master processor to enter a self-upgrade flow, executing detection by the slave processors after the writing of the upgrade program by the master processor is completed, and completing the whole upgrade flow after confirming that the writing of the upgrade program is correct.
If the fault occurs in the upgrading process, the program of the slave processor is wrong, the slave processor can be simply upgraded again, if the fault occurs in the master processor, the master processor cannot be guided into the upgrading process correctly, the manual forced upgrading mode is adopted, the forced upgrading process is carried out on the master processor, and then the normal upgrading process is restored. Therefore, the design mode can ensure 99.99% of successful upgrading of the processor.
Before executing step S1, after the system is powered on, the main processor enters the beginning section part of the corresponding boot zone searching program according to physical setting, relevant jump addresses are set in the beginning section part, the boot program enters the self-detection flow program, whether the running program verification codes of the program zones of the auxiliary processors are complete or not is checked, and the next step is executed according to judging results.
In this embodiment, after entering the self-checking procedure, the main processor sends a query instruction through a communication data interface (USB, SPI, serial, CAN, I2C, bluetooth, network, etc.) under the guidance of the procedure, sequentially queries the status of each slave processor for writing the procedure, and after receiving the query instruction sent by the main processor, the slave processor replies the corresponding parameter value within a specified time, and reports the integrity, writing time, version, etc. of the current procedure in the processor.
In the step S3, determining whether the current system state meets the upgrade standard includes: judging the current state of the system to determine whether the system enters an automatic upgrading process, a manual forced upgrading process or normally enters the system.
In this embodiment, the execution of the manual forced upgrade procedure includes: the master processor reset pin and the slave processor start pin are triggered simultaneously through the two input signal switches, so that the slave processor judges that the master processor is forcedly reset and enters the takeover, and the manual forced upgrading process is entered.
In the step S3, if the system enters an automatic upgrade process, the main processor queries a bootstrap program under a corresponding address, starts to read data input by an external data unit through a data communication interface (USB, SPI, serial, CAN, I2C, bluetooth, network, etc.), and temporarily stores the read data in a RAM/FLASH ROM area of the main processor after verification; after the external data is read, the main processor enters a downward writing upgrading flow, and the upgrading data can be read in the processor of the low-capacity ROM/RAM, and meanwhile, the slave processor can be upgraded (the slave processor can be upgraded while the data is read in, which is particularly important for the processor of the low-capacity ROM/RAM): after the main processor enters a downward writing upgrading process, the output pin signal of the main processor resets a slave processor, so that the slave processor enters a writing process of an upgrading program, and the upgrading program is written into the slave processor through a data serial bus; after the upgrade program of the slave processor is written, a confirmed flag bit is replied through a data serial bus according to the program requirement, and after the confirmed flag bit is received by the master processor, the slave processor can be confirmed to be successfully upgraded, and the next upgrade writing flow of the slave processor is entered; if the main processor does not receive the determination flag bit, the main processor determines that the upgrade program writing fails, and the main processor writes the upgrade program for the slave processor again.
After the main processor enters a downward writing upgrade process, a corresponding upgrade object is selected according to a chip selection signal, one slave processor is selected through pulling Gao Yinjiao P62, a pin P54 of the slave processor is pulled down, a writing process of the slave processor upgrade program is performed, and the slave processor is written with the upgrade program through a data communication interface.
After the upgrade program of the slave processor is written, a confirmed flag bit is replied through a data serial bus according to the program requirement, and after the confirmed flag bit is received by the master processor, the slave processor can be confirmed to be successfully upgraded, and the next upgrade writing flow of the slave processor is entered; if the main processor does not receive the determination flag bit, the main processor determines that the upgrade program writing fails, and the main processor writes the upgrade program for the slave processor again.
In this embodiment, after the first slave processor writes the upgrade program successfully, the master processor writes the upgrade program for the subsequent slave processors in turn, and after the last slave processor is successfully upgraded, the master processor jumps to the corresponding boot area and enters the self-upgrade process; under the self-upgrading process, the main processor firstly performs erasing and writing work of the program area, and after ensuring that the writing of the program area is correct, performs program erasing and writing process in the boot area.
The self-upgrading process specifically comprises the following steps: after entering the self-upgrading process, the main processor sets an upgrading identifier, the identifier indicates that the self-upgrading program data of the data communication interface is required to be upgraded according to the program requirement in the guiding area, the self-upgrading program data is divided into two areas of guiding and program, the guiding area is upgraded firstly, the guiding area data is temporarily stored in the program area firstly, the guiding area is upgraded by a specific program preset in the program area, after the guiding area is upgraded, the processor returns to the new guiding area, then the upgrading data of the program area is obtained, the program area is upgraded, and finally, after verification is completed, the upgrading identifier is cleared, so that the upgrading process of the whole system is completed.
Specifically, after entering the self-upgrade process, the main processor erases the memory program storage area of the chip according to the program requirement in the boot area, reads the SPI serial port of pins P13-P16 to obtain the self-upgrade program, and writes the part of the program into the memory area of the chip again, wherein the tail part of the upgrade program is provided with the same check bit, the boot program in the boot area verifies the correctness of the written program after the writing is completed, and the upgrade process of the boot area program is entered after the correctness is determined.
The method comprises the steps that the rear part of a main program of a program area after self-upgrading is finished is provided with a corresponding standby guide program, when a main processor confirms that the program area is finished to be upgraded, the main processor automatically jumps to a process of reading the content of the program area, the standby guide program at the tail part of the upgraded program in the program area is transferred to erasure, the process of writing the standby guide program into an original guide area is started, and the guide area program of the main processor is upgraded; after the upgrade writing of the boot area of the main processor is completed, the process jumps to the end of the related flow so as to complete the upgrade process of the whole system.
In this embodiment, if the main processor makes an error in the process of writing into the program area when performing self-upgrade, the system will automatically issue an alarm and needs to manually reset the whole system, when the system is powered on again, the boot-strap program in the main processor checks the integrity of the program area as required, and after confirming that the program fails to be written, the self-upgrade process is performed again, the content of the upgrade program is read from the data communication interface, and erasing and writing are performed again in the program area.
Furthermore, if the upgrade slave processor makes errors in the process of writing the original boot area of the upgrade slave processor, the upgrade slave processor enters an abnormal mode, and the manual forced upgrade process is executed to execute the upgrade for the master processor again.
Further, after determining that the main processor fails to write and cannot be automatically recovered, entering a manual forced upgrade process: the device is powered off firstly, a device reset key (a reset end of the main processor) is pressed, meanwhile, in order to ensure the accuracy of the forced state, an external key is pressed (the other input signal is communicated), the system is powered on again, and meanwhile, the system is kept for 3-5 seconds, at the moment, the main processor is in a reset state, and a reset pin of the main processor and a start pin of the auxiliary processor are triggered, so that the auxiliary processor judges that the main processor is forced to be reset and enters a connecting pipe, and a manual forced upgrading process is entered. The reset key and the external key are pressed down to electrify the main processor, and the reset pin and the starting pin of the slave processor are simultaneously pulled down to enter a manual forced upgrading process; the slave processor determines the state of the reset pin of the main processor by reading the pin P37 of the slave processor, reads the state of the starting pin of the slave processor after confirming that the reset pin of the main processor is pulled down for a long time for resetting, and executes a manual forced upgrading process through a program after confirming that the starting pin is pulled down.
Further, the slave processor obtains the upgrade program of the master processor through the communication data interface shared with the master processor, performs a mode similar to the master processor for upgrading the slave processor, and performs forced upgrade on the master processor, and at this time, the slave processor takes over necessary hardware resources (display, keyboard, flashRom, communication data interface and the like) of the original master processor, and performs man-machine interaction processing through the slave processor.
In this embodiment, the manual forced upgrade procedure for entering the slave processor to take over specifically includes: the slave processor selects a corresponding USB interface through pins P32/P33, reads the upgrade program content transmitted externally through an SPI bus, and stores the upgrade program content in a chip RAM temporarily; after the temporary storage and verification of the upgrade program are completed, the slave processor executes a cut-off reset process for the main processor through a signal of a pull-up pin P37, and then executes a program data writing process for the main processor through a data serial bus; after the writing upgrade of the main processor is finished, the confirmed flag bit of the upgrade is fed back through the SPI bus and is read by the auxiliary processor, after the auxiliary processor confirms that the flag bit data is correct, the auxiliary processor enters an upgrade finishing process, at the moment, the system is powered off and then is powered on, and the upgrade process taken over by the main processor is restored.
In practical application, after the system is powered on, the main processor firstly enters the beginning section part of the corresponding boot storage area searching program according to physical setting, and sets the relevant jump address, so that the boot program enters a self-detection flow.
Entering a self-checking flow program, the main processor sequentially queries the state of each slave processor in a mode of transmitting a query instruction through serial port connection pins TXD and RXD under the guidance of the program, and after receiving the transmitted query instruction, the slave processor replies corresponding parameter values within a specified time to report the information such as the integrity, writing time, version and the like of the program in the current processor.
Then, the master processor determines the current state of the system according to the responsive data value to determine whether to automatically enter the program upgrading process or normally enter the system, and at this time, the master processor reset pin P54 and the slave processor start pin P10 can be triggered simultaneously by two external input signal switches, so that the slave processor determines that the master processor has been forcibly reset to enter the takeover, and enters the manual forced upgrading process.
If the system enters an automatic upgrading flow, the main processor firstly inquires a bootstrap program under a corresponding address according to a program requirement, starts to read data input by an external data unit through an SPI bus of pins P13-P16, and stores the data temporarily in a RAM area of the main processor after checking after the data is read.
After the external data is read, the main processor enters a downward writing upgrading process, as a plurality of slave processors are communicated on the bus, a corresponding upgrading object is needed to be selected according to a chip selection signal, a slave processor A is selected through a pull Gao Yinjiao P62, a pin P54 of the slave processor A is pulled down, the writing upgrading process is entered, and the upgrading process is written into the slave processor A through a data serial port bus P46 and a data serial port bus P47 connected with the slave processor A.
After the writing of the slave processor A is completed, a certain flag bit is replied through serial port data according to the program requirement, the slave processor A is confirmed to be successfully upgraded only after the main processor receives the flag, the next upgrading writing process of the slave processor is started, if the flag cannot be received, the upgrading program writing failure is considered, and the main processor enters the process of upgrading the slave processor again.
According to the above flow, the master processor writes the upgrade program for the subsequent slave processors in turn until all slave processors are upgraded.
When the last slave processor is successfully upgraded, the master processor jumps to the corresponding guide area according to the program flow and enters the self-upgrading flow. Under the process, the main processor firstly sets an upgrade identification, and the identification is withdrawn only after all upgrades are correctly completed; the method comprises the steps that upgrade data of a new boot area are read in through a data communication interface, data verification and decryption are carried out, the upgrade data are temporarily stored in a specific position of a main program area, a main processor is transferred into a standby boot program inlet in the new boot area, data upgrade coverage is carried out on an original boot area, and finally after the correctness of the data in the boot area is verified, the main processor enters a main program area upgrade flow
After entering the main program upgrading flow, the main processor firstly erases the ROM data of the main program area, then reads the content of the new main program area through the data communication interface, writes the decrypted content into the main program area, verifies the correctness of the main program area, finally eliminates the upgrading identification, and completes the upgrading flow of the whole main processor.
After the main program upgrade writing of the main processor is completed, the main program upgrade writing is skipped to finish the related flow, and the upgrade process of the whole system is completed.
Furthermore, if the main processor encounters accidents in the process of writing into the program area during self-upgrade, the system automatically gives an alarm, the whole system needs to be reset manually at the moment, when the main processor is powered on again, the program in the boot area checks the integrity of the program area according to the requirement, after confirming that the program fails to be written into, the self-upgrade process is carried out again, the upgrade program content is read from the SPI serial port of the pins P13-P16, and the program area is erased and written again.
If the main processor encounters unexpected interruption during the writing process of the original boot area, the boot area based on the bottom layer of the chip is destroyed, and the chip cannot find the program entry address after power-on, so that the main processor enters an abnormal mode, and the manual forced upgrading process needs to be executed to execute upgrading for the main processor again.
When the writing failure of the main processor is determined and the automatic recovery is not possible, the main processor is powered on again by pressing a reset key and an external key, and simultaneously the reset pin P54 of the main processor and the start pin P10 of the slave processor are pulled down to enter a manual forced upgrade mode. The slave processor can determine the reset pin state of the main processor by reading the pin P37 of the slave processor, when the reset pin of the main processor is confirmed to be pulled down for a long time and reset, the state of the slave processor starting pin is read, after the reset pin P36 is confirmed to be pulled down, the manual forced upgrade process is executed through a program, and all functions including reading data and refreshing display are taken over.
Then, the manual forced upgrade process is carried out, the corresponding USB interface is selected from the processor through the P32/P33 pin, the upgrade program content transmitted from the SPI bus of the corresponding USB module pin P13-P16 is read, and the upgrade program content is temporarily stored in the chip RAM (for small-capacity CPU, a sector can be read, and a sector can be written).
After the temporary storage and verification of the program are completed, the slave processor executes a cut-off reset process for the master processor through a signal of a pull-up pin P37, and then independently executes a program data writing process for the master processor through serial communication buses of pins P46 and P47.
When the upgrade program of the main processor is written, the relevant mark data is fed back from the SPI bus and read by the auxiliary processor, and after the mark data is confirmed to be correct, the auxiliary processor enters an upgrade ending flow, and the system is powered off and then is powered on, so that the logic of the main processor for taking over all flows is restored. If the feedback of the written mark is abnormal, the default upgrading is unsuccessful, and the upgrading process of the main processor is entered again.
Therefore, the invention adopts the multiprocessor sequential upgrade scheme to implement the upgrade process, one main flow processor in the multiprocessor is responsible for allocating upgrade resources, and the upgrade process can be ensured to be stable according to the capability of upgrading corresponding software by hardware functions for other slave processors.
If the program of the slave processor of the system is erased and written into the upgrading process, the upgrading interrupt is caused by the unexpected situation, the master processor can record an upgrading log, when the user upgrades the system again, the slave breakpoint is realized to continue upgrading the system, the master processor can perform self-upgrading only after all the slave processors are upgraded, and if the master processor is in error in the upgrading process, the slave processor which has completed upgrading can reversely take over the upgrading resource allocation task, and the upgrading process of the master processor is controlled again. Therefore, under the design of mutually taking over the upgrading task scheme, the brick changing condition caused by the failure of the system upgrading process can be completely eradicated.
Therefore, the method provided by the invention can effectively reduce the probability of system paralysis caused by chip writing failure due to unexpected power failure, circuit interference and the like in the upgrading process, greatly increase the convenience of maintenance of the modular numerical control system and reduce the maintenance cost.
In addition, the invention adopts the multiprocessor parallel working type design, so the capability of upgrading the corresponding software according to the hardware function can be realized, and all MCUs needing to be upgraded can be automatically upgraded only by providing an upgrade file for the main processor, each MCU does not need to be independently upgraded, the working time of operators is saved, and the time cost of the upgrade is reduced.
It should be noted that references in the specification to "one embodiment," "another embodiment," "an embodiment," "a preferred embodiment," etc., indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application in general description. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is intended to be within the scope of the application to implement such feature, structure, or characteristic in connection with other embodiments. Although the application has been described herein with reference to a number of illustrative examples thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope and spirit of the principles of this disclosure. More particularly, other uses will be apparent to those skilled in the art from consideration of the specification, drawings and claims in connection with the disclosed subject matter and/or other variations and modifications of the component parts and/or arrangements of the subject matter.
Claims (4)
1. A method for parallel processing and self-upgrading based on multiple single-chip microcomputer is characterized by comprising the following steps:
After the system is powered on, the main processor enters the beginning section part of the corresponding boot zone searching program according to physical setting, relevant jump addresses are set in the beginning section part, the boot program enters a self-detection flow program, whether the running program verification codes of all the slave processor program zones are complete or not is checked, and the next step is executed according to a judging result;
After determining to enter the self-checking flow program, the main processor sends a query instruction to each auxiliary processor, sequentially queries the state of the program written in each auxiliary processor, and judges whether the current state of the system meets the upgrading standard according to the related data replied by the auxiliary processor;
If the judgment result is yes, the main processor enters a writing upgrading flow, and upgrading programs are written into each slave processor in sequence through the data communication interface;
after confirming that the writing of the upgrade program by all the slave processors is successful, the master processor enters a self-upgrade flow, the slave processor performs detection after the writing of the upgrade program by the master processor is finished, and the whole upgrade flow can be finished after the writing of the upgrade program is confirmed to be correct;
If the fault occurs in the upgrading process, the program of the slave processor is wrong, the slave processor can be simply upgraded again, if the fault occurs in the master processor, the master processor cannot be guided into the upgrading process correctly, a manual forced upgrading mode is adopted, the forced upgrading process is carried out on the master processor, and then the normal upgrading process is restored;
After entering a self-checking flow program, a main processor sends a query instruction through a data communication interface under the guidance of the program, sequentially queries the state of a program written in each slave processor, and after receiving the query instruction sent by the main processor, the slave processor replies corresponding parameter values within a specified time to report the integrity, writing time and version information of the program in the current slave processor;
Wherein, judging whether the current state of the system meets the upgrade standard comprises: judging the current state of the system to determine whether the system enters an automatic upgrading process or normally enters the system;
If the system enters an automatic upgrading flow, starting to read data transmitted by an external data unit through a data communication interface, checking the read data, and temporarily storing the data in a RAM/FLASH ROM area of a main processor; after the external data is read, the main processor enters a downward writing upgrading flow;
After the main processor enters a downward writing upgrading process, the output pin signal of the main processor resets a slave processor, so that the slave processor enters a writing process of an upgrading program, and the upgrading program is written into the slave processor through a data communication interface;
After the upgrade program of the slave processor is written, a confirmed flag bit is replied through a data communication interface according to the program requirement, after the confirmed flag bit is received by the master processor, the slave processor can be confirmed to be successfully upgraded, and the next upgrade writing flow of the slave processor is entered;
If the main processor does not receive the determination flag bit, determining that the writing of the upgrade program fails, and writing the upgrade program for the slave processor again by the main processor;
After the first slave processor writes the upgrade program successfully, the master processor writes the upgrade program for the subsequent slave processors in turn, and after the last slave processor is upgraded successfully, the master processor jumps to the corresponding guide area and enters the self-upgrade flow;
under the self-upgrading process, the main processor firstly erases and writes the program area, and after ensuring that the program area is correctly written, the main processor erases and writes the program in the guide area;
The self-upgrading process specifically comprises the following steps: after entering the self-upgrading flow, the main processor sets an upgrading identifier, the identifier indicates that the self-upgrading program data of the data communication interface is required to be upgraded according to the program requirement in the guiding area, the self-upgrading program data is divided into two areas of guiding and program, the guiding area is firstly upgraded, the read guiding area data is firstly placed in the program area, the guiding area is upgraded by the preset program, after the guiding area is upgraded, the main processor returns to the new guiding area, the upgrading data of the program area is obtained, the program area is upgraded, and finally, after the verification is finished, the upgrading identifier is cleared, so that the upgrading process of the whole system is finished;
The slave processor obtains an upgrade program of the master processor through a data communication interface shared with the master processor, executes a mode similar to the upgrade of the slave processor by the master processor, carries out forced upgrade on the master processor, takes over hardware resources of the original master processor at the moment, and carries out man-machine interaction processing through the slave processor;
When the write failure of the main processor is determined and the main processor cannot be automatically recovered, the method enters a manual forced upgrading flow taken over by the slave processor, and specifically comprises the following steps: the slave processor selects a corresponding USB interface through pins P32/P33, reads the upgrade program content transmitted externally through an SPI bus, and stores the upgrade program content in a chip RAM temporarily; after the temporary storage and verification of the upgrade program are completed, the slave processor executes a cut-off reset process for the main processor through a signal of a pull-up pin P37, and then executes a program data writing process for the main processor through a data serial bus; after the writing upgrade of the main processor is finished, the confirmed flag bit of the upgrade is fed back through the SPI bus and is read by the auxiliary processor, after the auxiliary processor confirms that the flag bit data is correct, the auxiliary processor enters an upgrade finishing process, at the moment, the system is powered off and then is powered on, and the upgrade process taken over by the main processor is restored.
2. The method according to claim 1, characterized in that:
If the main processor makes errors in the process of writing into the program area when the main processor performs self-upgrading, the system automatically gives an alarm, the whole system needs to be reset manually, when the system is powered on again, a boot area program in the main processor checks the integrity of the program area according to requirements, after confirming that the program writing fails, the self-upgrading process is performed again, the content of the upgrading program is read from the data communication interface, and the program area is erased and written again.
3. The method according to claim 2, characterized in that:
if the upgrade slave processor makes errors in the process of writing the original boot area of the upgrade slave processor, entering an abnormal mode, and executing a manual forced upgrade flow to execute upgrade for the master processor again.
4. A method according to claim 3, characterized in that:
And after determining that the writing of the main processor fails and cannot be automatically recovered, entering a manual forced upgrading flow: the equipment is powered off firstly, a reset key of the equipment is pressed, meanwhile, in order to ensure the accuracy of the forced state, an external key is pressed, the system is powered on again, and meanwhile, the system is kept for 3-5 seconds, at the moment, the main processor is in a reset state, and meanwhile, a reset pin of the main processor and a start pin of the auxiliary processor are triggered, so that the auxiliary processor judges that the main processor is forced to be reset and enters a take-over, and a manual forced upgrading process is entered.
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