CN113608607B - Multi-node server control method and multi-node server - Google Patents
Multi-node server control method and multi-node server Download PDFInfo
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Abstract
The embodiment of the application provides a multi-node server control method and a multi-node server, which are applied to a programmable chip arranged on a power supply board in the multi-node server, wherein the multi-node server comprises a plurality of server nodes and a plurality of power supply modules, the plurality of server nodes are respectively connected with different interfaces of the programmable chip through a first bus, and the plurality of power supply modules are connected to the same target interface of the programmable chip. The method comprises the following steps: receiving a power access request triggered by a target server node, wherein the target server node is any one of a plurality of server nodes; and if the target interface is determined to be in an idle state, connecting links between the target server node and the plurality of power modules so that the target server node acquires power supply information of the plurality of power modules through the connecting links. The multi-node server control method and the multi-node server control system can achieve control over the multi-node server with low cost and simplified design.
Description
Technical Field
The present application relates to the field of computing device technologies, and in particular, to a multi-node server control method and a multi-node server.
Background
With the development of cloud computing and big data, the computing power requirement on a computer is higher and higher, and the higher the computing power that a single computer can provide and the lower the Cost are in consideration of the Total Cost of Ownership (TCO). Based on this, the multi-node server can improve the computation density of a single computer and increase the cost benefit by stacking a plurality of server nodes (namely a plurality of CPU computation mainboards).
In a multi-node server, for the design of heat dissipation and Power Supply, a centralized heat dissipation and Power Supply manner is mostly adopted, that is, a plurality of server nodes collectively share a Power Supply Unit (PSU) and a fan. Of course, a distributed architecture implementation manner of independent power supply and heat dissipation is also provided for each server node, and only a distributed architecture is adopted, so that the cost is high.
At present, an independent control system needs to be additionally arranged under the architecture of centralized power supply and heat dissipation, and is used for controlling power supply and heat dissipation of a plurality of server nodes, so that the cost is increased, and the realization is complex.
Disclosure of Invention
The embodiment of the application provides a multi-node server control method and a multi-node server, and management and control of the multi-node server can be realized with low cost and simplified design.
In a first aspect, an embodiment of the present application provides a method for controlling a multi-node server, which is applied to a programmable chip disposed on a power supply board in the multi-node server, where the multi-node server includes a plurality of server nodes and a plurality of power modules, the plurality of server nodes are respectively connected to different interfaces of the programmable chip through a first bus, and the plurality of power modules are connected to a same target interface of the programmable chip, where the method includes:
receiving a power access request triggered by a target server node, wherein the target server node is any one of the plurality of server nodes;
and if the target interface is determined to be in an idle state, connecting links between the target server node and the plurality of power modules so that the target server node acquires power supply information of the plurality of power modules through the connecting links.
In a second aspect, an embodiment of the present application provides a multi-node server, including:
the system comprises a programmable chip, a plurality of server nodes and a plurality of power modules, wherein the programmable chip is arranged on a power supply board;
the plurality of server nodes are respectively connected with different interfaces of the programmable chip through a first bus, and the plurality of power modules are connected to the same target interface of the programmable chip;
the programmable chip is used for receiving a power access request triggered by a target server node, and if the target interface is determined to be in an idle state, connecting connection links between the target server node and the plurality of power modules, wherein the target server node is any one of the plurality of server nodes;
and the target server node is used for acquiring the power supply information of the plurality of power supply modules through the connection link.
In the solution provided in the embodiment of the present application, a programmable chip is disposed on a power supply board, and a plurality of server nodes are respectively connected to different interfaces of the programmable chip through a first bus, so as to connect a plurality of power modules to a same target interface of the programmable chip. Aiming at the control of the power supply module, the programmable chip can maintain the state of the target interface, namely idle or busy, on the basis of which, when the programmable chip receives a power supply access request triggered by the target server node and determines that the target interface is in the idle state, the connection links between the target server node and the plurality of power supply modules are conducted, so that the target server node can directly access the plurality of power supply modules to obtain the power supply information of the target server node, and the programmable chip does not need to intervene in the transmission process of the information, thereby reducing the processing load of the programmable chip, and realizing the power supply control of the multi-node server by using the scheme provided by the application with lower cost and simplified design.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a multi-node server according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a multi-node server according to an embodiment of the present disclosure;
FIG. 3 is a flowchart of a multi-node server control method according to an embodiment of the present application;
fig. 4 is a flowchart of another multi-node server control method according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
With the development of cloud computing and big data, the computing power requirement on a computer is higher and higher, and the higher the computing power that a single computer can provide and the lower the Cost are in consideration of the Total Cost of Ownership (TCO). Based on this, the multi-node server can improve the computation density of a single computer and increase the cost benefit by stacking a plurality of server nodes (namely a plurality of CPU computation mainboards).
In some embodiments of the present application, a programmable chip may be disposed on a power supply board for controlling a power module, and a plurality of server nodes are respectively connected to different interfaces of the programmable chip through a first bus, and a plurality of power modules are connected to a same target interface of the programmable chip. The programmable chip is arranged on the power supply board to which all the devices are connected, so that the connection between a plurality of server nodes and a plurality of power modules and the programmable chip can be realized in a more simplified manner. Based on the connection mode of the plurality of power modules, the plurality of server nodes and the programmable chip, the programmable chip can arbitrate the access of the plurality of server nodes to the power modules, and the purpose that only a single server node can directly access the power modules at the same time is achieved.
The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a multi-node server according to an embodiment of the present disclosure. As shown in fig. 1, the multi-node server includes: a programmable chip 10 provided on the power supply board 1, a plurality of server nodes 20 (for example, 20A to 20N illustrated in the figure), and a plurality of power supply modules 30. The plurality of server nodes 20 are respectively connected to different interfaces of the programmable chip 10 through a first bus, and the plurality of power modules 30 are connected to the same target interface of the programmable chip 10.
In this embodiment, the above setting is mainly for controlling the plurality of power modules 30 in the multi-node server.
The plurality of power modules 30 are provided in the multi-node server, mainly to meet the power consumption requirements of the server nodes 20. Because the power output by each power module 30 is constant (e.g., 800W), if some server nodes 20 require 1800W of power for operation, a plurality of power modules 30 need to be combined to meet the requirements of the server node 20.
Optionally, the Programmable chip 10 may be a Complex Programmable Logic Device (CPLD), and may also be implemented as other Programmable Logic devices without being limited thereto.
As shown in fig. 1, since each server node 20 has a need to query the power supply information of a plurality of power modules 30 at the same time, each server node 20 is independently connected to a different interface on the programmable chip 10, and the plurality of power modules 30 are not necessarily connected to different interfaces on the programmable chip 10 independently, so that a plurality of power modules 30 can be connected to the same interface on the programmable chip, which is called a target interface.
In practical applications, suitable buses may be selected according to different data types of the power supply information to be transmitted, so as to implement connection between the server node 20 and the power supply module 30 and the programmable chip 10.
Alternatively, the first Bus for connecting server node 20 to programmable chip 10 may include a Power Management Bus (PMBUS), and may include a MISC Bus. Wherein, the PMBUS can transmit messages, namely information content. And binary signals such as 0 and 1 can be transmitted on the MISC bus. In practical applications, the power supply information of the power supply module 30 may include various information contents reflecting the operating condition of the power supply module 30, such as output power, power supply voltage, power supply current, remaining power, and may further include an indication signal reflecting whether the power supply module 30 is abnormal, where the indication signal may be embodied as: signal 0 indicates that the power module 30 is healthy and signal 1 indicates that the power module 30 is abnormal.
Correspondingly, the Bus for connecting the plurality of Power modules 30 to the programmable chip 10 may also include a Power Management Bus (PMBUS), and in addition, may also include a MISC Bus. However, a plurality of power modules 30 need to be connected to the same interface of the programmable chip 10 through a connection bus.
For the control of the plurality of power modules 30, the programmable chip 10 may be embodied as:
the programmable chip 10 receives a power access request triggered by a target server node, and if it is determined that the target interface is in an idle state, connects connection links between the target server node and the plurality of power modules 30, where the target server node is any one of the plurality of server nodes 20. Thus, the target server node can obtain the power supply information of the plurality of power supply modules 30 through the connected link.
When the multi-node server specifically works, each server node 20 may be configured to trigger a power access request to the programmable chip 10 every preset time period (every 3s, 5s, or 10s, etc.), where the power access request is to obtain power supply information of the plurality of power modules 30. In practical applications, the above time intervals configured for each server node 20 may be the same or different, and even if the time intervals are the same, in an actual operation process, the time for the power access request triggered by different server nodes 20 to reach the programmable chip 10 may be different due to factors such as low precision of timestamp synchronization or different transmission delays of different server nodes 20. Therefore, the programmable chip 10 may receive a power access request triggered by only one server node 20 or may receive power access requests triggered by several server nodes 20 at a certain time.
At the same time, a plurality of power modules 30 can be accessed by only one server node, for this reason, the programmable chip 10 needs to complete the access arbitration process for a plurality of server nodes 20, and at the same time, the programmable chip 10 needs to maintain the access states of a plurality of power modules 30.
Specifically, since a plurality of power modules 30 are connected to the same target interface of the programmable chip 10, if a certain server node 20 is accessing a plurality of power modules 30, the target interface will be in a busy state for transmitting data, so the programmable chip 10 can know whether a server node is accessing a plurality of power modules 30 currently by maintaining the busy and idle states of the target interface.
The access arbitration process of the programmable chip 10 to the plurality of server nodes 20 is mainly embodied as follows: after receiving a power access request triggered by a target server node, the programmable chip 10 determines whether a target interface connected to the plurality of power modules 30 is in an idle state, and if it is determined that the target interface is in the idle state, connects a connection link between the target server node and the plurality of power modules 30. At this time, the target server node may directly interact with the plurality of power modules 30 through the connection link to obtain the power supply information of the plurality of power modules 30.
If the programmable chip 10 receives a power access request triggered by a target server node, it finds that the target interface is in a busy state, which indicates that other server nodes are currently accessing multiple power modules 30, the programmable chip 10 may discard the power access request triggered by the target server node. The target server node may re-trigger the power access request upon arrival of the next cycle based on its configured access cycle.
It should be noted that, if the programmable chip 10 receives power information access requests sent by M (M > 1) server nodes 20 at the same time and determines that the target interfaces connected to the multiple power modules 30 are in the idle state, optionally, the currently-turned-on server nodes may be determined according to the number sequence of the M server nodes 20, for example, the numbers of the M server nodes 20 are 1, 2, 3, and 4, respectively, and then, the connection links between the server node with the currently-turned-on number of 1 and the multiple power modules 30 are determined.
Assuming that the programmable chip 10 has conducted the connection links between the target server node and the plurality of power modules 30, the conducting logic can be understood as: the programmable chip 10 is then used as a logic switch to close the circuit between the interface of the programmable chip 10 connected to another server node and the target interface, and only to conduct the link between the interface connected to the target server node and the target interface.
After the connection links between the target server node and the plurality of power modules 30 are connected, the target server node may interact with the plurality of power modules 30 to obtain the power supply information of each power module 30, and at this time, the programmable chip 10 is not required to collect the power supply information of each power module 30 and transmit the power supply information to the target server node. The power supply information of the power modules 30 may be specific information content reflecting specific operating conditions of the power modules 30, such as current, voltage, and power output by the power modules 30. As described above, these power information reflecting the particular operating conditions of the power module 30 may be transmitted via the PMBUS.
The purpose of acquiring the power supply information of the plurality of power modules 30 in the embodiment of the present application is described below by taking the output power of the plurality of power modules 30 as an example: after the target server node obtains the output power of the plurality of power modules 30, if it is found that the output power of all or most of the power modules 30 is greater than the preset threshold, the CPU down-conversion processing may be performed on the target server node to reduce the power consumption requirement thereof, thereby avoiding the damage caused by the continuous high-power output of the power modules 30.
As an alternative embodiment, the programmable chip 10 may also periodically collect the health status of a plurality of power modules 30, and send the indication signals reflecting the health status to a plurality of server nodes 20, respectively. In a specific implementation, for example, when an abnormality occurs in a certain power module 30, the corresponding MISC signal (i.e., the binary signal) is triggered and sent to the programmable chip 10. After receiving the MISC signal, the programmable chip 10 distributes the MISC signal to each server node 20, and triggers an alarm signal to a remote control platform through each server node 20, so that relevant personnel migrate each service deployed on the multi-node server to other multi-node servers.
In summary, in the above solution, the programmable chip 10 is disposed on the power supply board in the multi-node server to control the power module 30, on one hand, the programmable chip is disposed on the power supply board to which each device is connected, so that the bus connection between each power module 30, each server node 20 and the programmable chip 10 is conveniently achieved at a lower cost; on the other hand, by connecting the plurality of power modules 30 to the same interface of the programmable chip 10, maintaining the access state of the interface and implementing access arbitration for the plurality of server nodes 20 through the programmable chip 10, it can be ensured that only one server node is turned on at the same time to directly query the power supply information of the plurality of power modules 30, and in the process of acquiring and transmitting the power supply information, the programmable chip 10 does not need to intervene, which reduces the processing complexity of the programmable chip 10, because the acquisition and transmission of the plurality of specific power supply information of the plurality of power modules 30 need to consume a large processing resource.
In addition to the control requirements of the power supply module, the multi-node server also has a control requirement of heat dissipation, that is, a control requirement for a plurality of fans in the multi-node server.
Fig. 2 is a schematic structural diagram of a multi-node server according to an embodiment of the present disclosure. As shown in fig. 2, the multi-node server further includes: and the fans 40 are respectively connected with different interfaces of the programmable chip 10 through second buses.
Alternatively, the second bus may be I2And C, a bus.
As shown in fig. 2, in order to control the fans 40, the server nodes 20 also need to be connected to the programmable chip 10 by using the same second bus, and specifically, the server nodes 20 are connected to different interfaces of the programmable chip 10 by the second bus.
In the embodiment of the present application, the control of the plurality of fans 40 may be divided into two cases: one is that the programmable chip 10 controls the speed of the plurality of fans based on the fan speed demand of each server node 20; one is that the programmable chip 10 collects the actual rotational speeds of the plurality of fans 40 and sends them to the respective server nodes 20.
In general, to achieve the above control requirements, the plurality of server nodes 20 may be configured to send fan speed requirement information to the programmable chip 10 periodically or upon certain conditions being met. The programmable chip 10 receives the fan speed demand information sent by the plurality of server nodes 20, determines target speeds corresponding to the plurality of fans 40 according to the fan speed demand information sent by the plurality of server nodes 20, and sends control commands corresponding to the target speeds to the plurality of fans 40. The plurality of fans 40 adjust the rotation speed according to the control command.
In addition, the programmable chip 10 may periodically acquire actual rotation speeds of the plurality of fans 40, and transmit the actual rotation speeds of the plurality of fans 40 to the plurality of server nodes 20, respectively.
To implement the above fan control, optionally, as shown in fig. 2, a plurality of registers may be provided in the programmable chip 10, and the plurality of registers correspond to the plurality of fans 40 one to one.
Based on this, the programmable chip 10 writes the control command into a plurality of registers, so that the plurality of fans 40 can read the control command from the respective corresponding registers to complete the adjustment of the corresponding rotation speed.
Similarly, after acquiring the actual rotation speeds of the fans 40, the programmable chip 10 may correspondingly write the actual rotation speeds of the fans 40 into the corresponding registers. In this way, multiple server nodes 20 may read the actual speed of each fan 40 from multiple registers.
In specific implementation, the plurality of server nodes 20 send the fan rotation speed demand information to the programmable chip 10 at preset time intervals (every 3s, 5s, 10s, or the like) according to their own conditions. The fan speed requirement information is expressed in percentage form, for example, in the form of 30%, 50%, 70%, etc. After receiving the fan speed demand information sent by the plurality of server nodes 20, the programmable chip 10 determines target speeds corresponding to the plurality of fans 40 according to the fan speed demand information sent by the plurality of server nodes 20. Specifically, the highest percentage of speed demand (i.e., 70%) may be selected as the target speed (because the speeds of the plurality of fans 40 are to be controlled to meet the maximum demand among the plurality of server nodes 20). After that, the programmable chip 10 generates a control command corresponding to the target rotation speed. Specifically, the fan 40 generally performs the rotation speed adjustment according to a Pulse Width Modulation (PWM) duty ratio, so that the process of generating the control command by the programmable chip 10 actually needs to complete the data conversion from the rotation speed requirement represented by a percentage such as 70% to the PWM duty ratio, the converted PWM duty ratio may be written into a plurality of registers, and each fan 40 reads the PWM duty ratio from the corresponding register and then adjusts the rotation speed according to the duty ratio.
The plurality of server nodes 20 may determine whether the actual rotational speed matches their own demanded rotational speed by acquiring the actual rotational speeds of the plurality of fans 40 (the actual rotational speeds greater than or equal to their own demanded rotational speeds may all be considered as matching). Furthermore, by acquiring the actual rotation speeds of the plurality of fans 40, it can be determined whether a failure has occurred in a fan 40, for example, if the rotation speed of a certain fan 40 is lower than a preset threshold or the rotation speed is 0, it can be determined that the fan 40 has a failure.
Similarly to the process of issuing the control command to the fans 40, the representation of the actual rotation speeds of the fans 40 acquired by the programmable chip 10 may be in the form of PWM duty cycles, and after converting the PWM duty cycles into percentage form, the percentage is written into the corresponding registers. The plurality of server nodes 20 are configured to read the actual speed of each fan 40 from a plurality of registers.
In addition to the multi-node server embodiments provided in the above embodiments, the embodiments of the present application also provide a corresponding multi-node server control method. The multi-node server control method is exemplarily described below.
Fig. 3 is a flowchart of a multi-node server control method according to an embodiment of the present application, which is applied to a programmable chip disposed on a power supply board in a multi-node server, where the multi-node server includes a plurality of server nodes and a plurality of power modules, the plurality of server nodes are respectively connected to different interfaces of the programmable chip through a first bus, and the plurality of power modules are connected to a same target interface of the programmable chip. As shown in fig. 3, the method includes:
301. a power access request triggered by a target server node is received, the target server node being any one of a plurality of server nodes.
302. And if the target interface is determined to be in an idle state, connecting links between the target server node and the plurality of power modules so that the target server node acquires power supply information of the plurality of power modules through the connecting links.
Fig. 4 is a flowchart of another control method for a multi-node server according to an embodiment of the present disclosure, in which the multi-node server includes a plurality of fans, and the plurality of fans are respectively connected to different interfaces of a programmable chip. As shown in fig. 4, the method further includes:
401. and receiving fan rotating speed demand information sent by a plurality of server nodes.
402. And determining target rotating speeds corresponding to the fans according to the fan rotating speed requirement information sent by the server nodes.
403. And sending a control instruction corresponding to the target rotating speed to the fans so that the rotating speeds of the fans can be adjusted according to the control instruction.
404. Actual rotational speeds of the plurality of fans are acquired.
405. And respectively sending the actual rotating speeds of the fans to the server nodes.
In the embodiment of the present application, as an embodiment, a plurality of registers are arranged in a programmable chip, and the plurality of registers correspond to a plurality of fans one to one; sending control commands corresponding to the target rotating speeds to the fans, wherein the control commands comprise: and writing the control instruction into a plurality of registers so that the plurality of fans read the control instruction from the corresponding registers.
In the embodiment of the present application, as another embodiment, a plurality of registers are arranged in a programmable chip, and the plurality of registers correspond to a plurality of fans one to one; sending the actual rotational speeds of the plurality of fans to the plurality of server nodes respectively, including: and correspondingly writing the actual rotating speeds of the fans into the registers so that the actual rotating speeds are read from the registers by the server nodes.
For a specific implementation process of the scheme provided in the foregoing embodiment, reference may be made to relevant descriptions in the foregoing embodiment, which is not described herein again.
The above-described apparatus embodiments are merely illustrative, wherein the units described as separate components may or may not be physically separate. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by adding a necessary general hardware platform, and of course, can also be implemented by a combination of hardware and software. With this understanding in mind, the above-described technical solutions and/or portions thereof that contribute to the prior art may be embodied in the form of a computer program product, which may be embodied on one or more computer-usable storage media having computer-usable program code embodied therein (including but not limited to disk storage, CD-ROM, optical storage, etc.).
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (11)
1. A multi-node server control method is characterized in that the method is applied to a programmable chip arranged on a power supply board in a multi-node server, the multi-node server comprises a plurality of server nodes and a plurality of power modules, the plurality of server nodes are respectively connected with different interfaces of the programmable chip through a first bus, and the plurality of power modules are connected to the same target interface of the programmable chip through the first bus; the first bus comprises a PM bus and a MISC bus; the method comprises the following steps:
receiving a power access request triggered by a target server node through the PM bus, the target server node being any one of the plurality of server nodes;
if the target interface is determined to be in an idle state, connecting links between the target server node and the plurality of power modules so that the target server node can directly obtain power supply information of the plurality of power modules through the connecting links, wherein the connecting links correspond to the PM bus;
acquiring the health states of the plurality of power supply modules through the MISC bus, and transmitting the health states to the plurality of server nodes through the MISC bus, respectively.
2. The method of claim 1, wherein the multi-node server comprises a plurality of fans, and the plurality of fans are respectively connected to different interfaces of the programmable chip; the method further comprises the following steps:
receiving fan rotating speed requirement information sent by the plurality of server nodes;
determining target rotating speeds corresponding to the fans according to the fan rotating speed demand information sent by the server nodes;
and sending control instructions corresponding to the target rotating speed to the fans to enable the fans to adjust the rotating speed according to the control instructions.
3. The method of claim 2, further comprising:
acquiring actual rotating speeds of the fans;
and respectively sending the actual rotating speeds of the fans to the server nodes.
4. The method of claim 2, wherein a plurality of registers are provided in the programmable chip, the plurality of registers corresponding to the plurality of fans one-to-one; the sending of the control command corresponding to the target rotational speed to the plurality of fans includes:
writing the control instruction into the plurality of registers to enable the plurality of fans to read the control instruction from the respective corresponding registers.
5. The method of claim 3, wherein a plurality of registers are provided in the programmable chip, the plurality of registers corresponding to the plurality of fans one-to-one; the sending the actual rotational speeds of the plurality of fans to the plurality of server nodes, respectively, includes:
correspondingly writing the actual rotating speeds of the fans into the registers, so that the actual rotating speeds are read from the registers by the server nodes.
6. A multi-node server, comprising:
the system comprises a programmable chip, a plurality of server nodes and a plurality of power modules, wherein the programmable chip is arranged on a power supply board;
the plurality of server nodes are respectively connected with different interfaces of the programmable chip through a first bus, the plurality of power supply modules are connected to the same target interface of the programmable chip through the first bus, and the first bus comprises a PM bus and a MISC bus;
the programmable chip is used for receiving a power access request triggered by a target server node through the PM bus, conducting a connection link between the target server node and the plurality of power modules if the target interface is determined to be in an idle state, acquiring health states of the plurality of power modules through the MISC bus, and respectively sending the health states to the plurality of server nodes through the MISC bus; the target server node is any one of the plurality of server nodes, the connection link corresponding to the PM bus;
the target server node is used for directly acquiring power supply information of the plurality of power supply modules through the connecting link and receiving the health status through the MISC bus.
7. The multi-node server according to claim 6, wherein the multi-node server comprises a plurality of fans, and the plurality of fans are respectively connected with different interfaces of the programmable chip through a second bus;
the programmable chip is used for receiving fan rotating speed demand information sent by the plurality of server nodes, determining target rotating speeds corresponding to the plurality of fans according to the fan rotating speed demand information sent by the plurality of server nodes, and sending control instructions corresponding to the target rotating speeds to the plurality of fans;
and the fans are used for adjusting the rotating speed according to the control instruction.
8. The multi-node server of claim 7, wherein a plurality of registers are provided in the programmable chip, the plurality of registers corresponding to the plurality of fans one-to-one;
the programmable chip is used for writing the control instruction into the plurality of registers;
and the fans are used for reading the control instructions from the corresponding registers.
9. The multi-node server of claim 7, wherein the programmable chip is configured to obtain actual rotational speeds of the plurality of fans, and send the actual rotational speeds of the plurality of fans to the plurality of server nodes, respectively.
10. The multi-node server of claim 9, wherein a plurality of registers are provided in the programmable chip, the plurality of registers corresponding to the plurality of fans one-to-one;
the programmable chip is used for correspondingly writing the actual rotating speeds of the fans into the registers;
the server nodes are used for reading the actual rotating speed from the registers.
11. The multinode server of claim 6, wherein the programmable chip comprises: a complex programmable logic device.
Priority Applications (1)
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