CN113594253A - Method and system for dopant activation using microwave radiation - Google Patents
Method and system for dopant activation using microwave radiation Download PDFInfo
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- CN113594253A CN113594253A CN202110858421.8A CN202110858421A CN113594253A CN 113594253 A CN113594253 A CN 113594253A CN 202110858421 A CN202110858421 A CN 202110858421A CN 113594253 A CN113594253 A CN 113594253A
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- 230000005855 radiation Effects 0.000 title claims abstract description 58
- 230000004913 activation Effects 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000002019 doping agent Substances 0.000 title abstract description 61
- 239000004065 semiconductor Substances 0.000 claims abstract description 255
- 239000000463 material Substances 0.000 claims abstract description 95
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 54
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000011358 absorbing material Substances 0.000 claims description 68
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 60
- 229910052796 boron Inorganic materials 0.000 claims description 60
- 239000013078 crystal Substances 0.000 claims description 12
- 230000007547 defect Effects 0.000 claims description 12
- 150000001638 boron Chemical class 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 24
- 230000005684 electric field Effects 0.000 description 12
- 238000010521 absorption reaction Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 150000002290 germanium Chemical class 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 229910012990 NiSi2 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- VNQLBSAIKVNHFM-UHFFFAOYSA-N [W].[Hg] Chemical compound [W].[Hg] VNQLBSAIKVNHFM-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- 229910021354 zirconium(IV) silicide Inorganic materials 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66568—Lateral single gate silicon transistors
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Abstract
The semiconductor structure includes a substrate and a source/drain (S/D) junction. The S/D junction is associated with the substrate and includes a semiconductor material including germanium and having a germanium composition percentage between about 50% and about 95%. Embodiments of the invention also relate to methods and systems for dopant activation using microwave radiation.
Description
This application is a divisional application of an invention patent application entitled "method and system for dopant activation using microwave radiation" filed on 09.11.2015 under application number 201510754802.6.
Cross Reference to Related Applications
This application is a continuation-in-part application of U.S. patent application No. 13/963, 043 filed on 8/9/2013, the entire contents of which are incorporated herein by reference.
Technical Field
The technology described in this patent document relates generally to semiconductor materials and, more particularly, to the processing of semiconductor materials.
Background
The fabrication of semiconductor devices typically involves a number of process steps. For example, a process for fabricating a field effect transistor typically includes doping a semiconductor substrate (e.g., adding desired impurities into the substrate) to form source/drain junctions. Many different methods such as ion implantation, diffusion and epitaxial growth can be employed to dope the substrate. Furthermore, it is often necessary to electrically activate dopants introduced into a substrate before a semiconductor device can be fabricated on the substrate. Activation of the dopant typically includes dissolving the dopant clusters and transferring dopant atoms/molecules from interstitial sites to lattice sites of the lattice structure of the substrate. As an example, the dopant may be activated using Rapid Thermal Annealing (RTA) or millisecond thermal annealing (MSA).
In a particular case, the manufacturing process of semiconductor devices involves microwave radiation, which typically comprises electromagnetic waves with a wavelength in the range from 1m to 1mm (corresponding to a frequency between 0.3GHz and 300 GHz). When microwave radiation is applied to a particular material (e.g., a dielectric material) that includes an electric dipole, the dipoles change their orientation in response to an electric field that changes the microwave radiation and thus the material may absorb the microwave radiation to generate heat. The response of a material to the electric field of microwave radiation can be measured using a complex permittivity ∈ (ω), which depends on the frequency of the electric field:
ε(ω)*=ε(ω)'-iε(ω)”=ε0(εr(ω)'-iεr(ω)”) (1)
where ω denotes the frequency of the electric field, ε (ω) 'denotes the real part of the complex permittivity (i.e., the permittivity), and ε (ω)' denotes the dielectric loss factor. Furthermore,. epsilon0Denotes the dielectric constant, ε, of a vacuumr(ω)' represents a relative dielectric constant, and εr(ω) "represents the relative dielectric loss factor.
The loss tangent tan δ can be used to characterize whether a material can absorb microwave radiation:
where μ' represents the real part of the permeability of the material and μ ″ represents the magnetic loss factor. Assuming that the magnetic loss is negligible (i.e., μ ″ ═ 0), the loss tangent of the material is expressed as follows:
materials with low loss tangents (e.g., tan δ <0.01) allow microwaves to pass through and have very little absorption. Materials with extremely high loss tangents (e.g., tan δ >10) reflect microwaves and have little absorption. Materials with moderate loss tangents (e.g., 10. gtoreq. tan. delta. gtoreq. 0.01) can absorb microwave radiation.
Disclosure of Invention
In accordance with the teachings described herein, in one embodiment, a semiconductor structure is provided that includes a substrate and a source/drain (S/D) junction. The S/D junction is associated with the substrate and includes a semiconductor material including germanium and having a germanium composition percentage between about 50% and about 95%.
In another embodiment, a semiconductor structure is provided that includes a substrate and a source/drain (S/D) junction. The S/D junction is associated with the substrate and includes a semiconductor material. The semiconductor material has a lower layer comprising germanium and an upper layer doped with boron, the upper layer having a higher concentration of boron than the lower layer.
In another embodiment, a method is provided. The method includes receiving a substrate of a semiconductor structure and forming a source/drain (S/D) junction associated with the substrate. Forming the S/D junction includes forming a semiconductor material including germanium and doping the semiconductor material with boron such that a concentration of boron of an upper layer of the semiconductor material is higher than a concentration of boron of a lower layer of the semiconductor material.
Drawings
Fig. 1 shows an example diagram for dopant activation using microwave radiation.
Fig. 2 shows another exemplary diagram for dopant activation using microwave radiation.
Fig. 3 shows an example diagram of an apparatus for dopant activation using microwave radiation.
Fig. 4 shows an example diagram for dopant activation using microwave radiation.
Fig. 5 shows another exemplary diagram for dopant activation using microwave radiation.
Fig. 6 shows an example flow diagram for dopant activation using microwave radiation.
Fig. 7 illustrates another example flow diagram for dopant activation using microwave radiation.
Fig. 8 illustrates an example flow diagram of operation 770 of fig. 7.
Fig. 9 illustrates another example flow diagram of operation 770 of fig. 7.
FIG. 10 illustrates another example flow diagram of operation 770 of FIG. 7.
FIG. 11 illustrates another example flow diagram of operation 770 of FIG. 7.
FIG. 12 shows an example plot of concentration versus depth
Fig. 13 illustrates an exemplary diagram of a semiconductor structure.
Detailed Description
Conventional techniques for dopant activation (such as RTA and MSA) typically involve high processing temperatures. For example, RTA is typically carried out at a temperature above 950 ℃ and MSA is carried out at a temperature above 1050 ℃. Such high processing temperatures may not be suitable for some modern semiconductor devices. For example, certain materials (e.g., germanium, tin) used in modern Complementary Metal Oxide Semiconductor (CMOS) devices have low melting points, which limit the processing temperatures used to fabricate the devices.
Fig. 1 shows an example diagram for dopant activation using microwave radiation. As shown in fig. 1, the microwave-absorbing material 102 is placed at a distance (e.g., d) from the semiconductor structure 104, the semiconductor structure 104 including a dopant, wherein microwave radiation may be applied to the microwave-absorbing material 102 and the semiconductor structure 104 to activate the dopant in the semiconductor structure 104.
For example, the semiconductor structure 104 may include a junction having multiple dopants. The junction including the dopant may be formed on the substrate by epitaxial growth (e.g., by Chemical Vapor Deposition (CVD)) at an elevated temperature (e.g., in a range of about 300 ℃ to about 600 ℃). The microwave-absorbing material 102 enhances the electric field density over the semiconductor structure 104 in response to the applied microwave radiation. More and more dipoles associated with the dopants may be formed in the semiconductor structure 104, and these dipoles may vibrate and/or rotate in response to the applied microwave radiation. The semiconductor structure 104 may absorb more microwave radiation at increased electric field densities. Once the electric field density over the semiconductor structure 104 exceeds a threshold, dipole formation and dipole motion (e.g., vibration and/or rotation) may eventually break the bond between the dopant and the interstitial sites in the semiconductor structure 104, thereby enabling activation of the dopant. The distance between the microwave absorbing material 102 and the semiconductor structure 104 may be adjusted to improve dopant activation. For example, the dopant may include phosphorus, phosphorus-based molecules, germanium, helium, boron-based molecules, or combinations thereof.
In one embodiment, the microwave radiation applied to the microwave absorbing material 102 may have a frequency in the range of about 2GHz to about 10 GHz. For example, the microwave absorbing material 102 may include boron doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, or combinations thereof. The microwave-absorbing material 102 may have a much larger size than the semiconductor structure 104 so that the electric field density over the semiconductor structure 104 may be nearly uniform. By way of example, the semiconductor structure 104 may include a semiconductor substrate, a semiconductor-on-insulator structure, or a semiconductor thin film structure.
In another embodiment, the temperature of the semiconductor structure 104 may be maintained within a range of about 500 ℃ to about 600 ℃ in order to control dopant diffusion. For example, microwave radiation may be applied to the microwave-absorbing material 102 and the semiconductor structure 104 for a time period in a range of about 40 seconds to about 300 seconds.
Fig. 2 shows another exemplary diagram for dopant activation using microwave radiation. As shown in fig. 2, a semiconductor structure 202 including dopants is placed between two microwave-absorbing materials 204 and 206, wherein microwave radiation may be applied to the semiconductor structure 202 and the microwave-absorbing materials 204 and 206 to activate the dopants in the semiconductor structure 202. For example, the microwave absorbing materials 204 and 206 may have the same loss tangent or different loss tangents. As an example, the distance between microwave-absorbing material 204 and semiconductor structure 202 (e.g., d1) may be the same or different than the distance between microwave-absorbing material 206 and semiconductor structure 202 (e.g., d 2). The distances d1 and d2 may be adjusted to improve dopant activation. In one embodiment, microwave-absorbing material 204 may be placed above the top surface of semiconductor structure 202, and microwave-absorbing material 206 may be placed below the bottom surface of semiconductor structure 202. In another embodiment, the microwave-absorbing material 204 may be placed over a side of the semiconductor structure 202, and the microwave-absorbing material 206 may be placed over another side of the semiconductor structure 202. In yet another embodiment, a variety of microwave-absorbing materials may be placed above the top surface, below the bottom surface, and above one or more side surfaces of the semiconductor structure 202.
Fig. 3 shows an example diagram of an apparatus for dopant activation using microwave radiation. As shown in fig. 3, a semiconductor structure 302 including dopants may be placed between two microwave absorbing materials 304 and 306 within a shell 308. The housing 308 includes one or more microwave ports 310 through which microwave radiation may be introduced. For example, the shell 308 may be made of a metallic material. The microwave absorbing materials 304 and 306 may be preheated by heat sources 312 and 314, respectively, to a predetermined temperature (e.g., in the range of about 500 ℃ to about 600 ℃) to enhance absorption of microwave radiation by the microwave absorbing materials 304, 306. For example, heat sources 312 and 314 may include an Ar lamp, a xenon lamp, or a tungsten mercury lamp. In another example, heat sources 312 and 314 may include one or more power sources (e.g., silicon controlled rectifiers).
Fig. 4 shows an example diagram for dopant activation using microwave radiation. As shown in fig. 4, a microwave absorbing layer 402 may be formed on a semiconductor structure 404 including a dopant, wherein microwave radiation may be applied to the microwave absorbing layer 402 and the semiconductor structure 404. For example, microwave-absorbing layer 402 may be formed on semiconductor structure 404 by epitaxial growth (e.g., CVD). The thickness of the microwave absorbing layer 402 may be adjusted, for example, between about 30nm and about 250nm to improve dopant activation. For example, microwave-absorbing layer 402 may be formed on semiconductor structure 404 by epitaxial growth (e.g., CVD). For example, after dopant activation, the microwave absorbing layer 402 may be subsequently removed by etching (e.g., wet etching, dry etching) or chemical mechanical polishing.
Fig. 5 shows another exemplary diagram for dopant activation using microwave radiation. As shown in fig. 5, a microwave absorbing layer 502 may be formed on a top surface of a semiconductor structure 504 including a dopant, and another microwave absorbing layer 506 may be formed on a bottom surface of the semiconductor structure 504. Microwave radiation may be applied to the semiconductor structure 504 and the microwave absorbing layers 502 and 506 for dopant activation. In one embodiment, microwave absorbing layer 502 may be formed on a side of semiconductor structure 504, and microwave absorbing layer 506 may be formed on the other side of semiconductor structure 504. In another embodiment, a plurality of microwave absorbing layers may be formed on the top surface, on the bottom surface, and on one or more side surfaces of the semiconductor structure 504.
Fig. 6 shows an example flow diagram for dopant activation using microwave radiation. As shown in fig. 6, in operation 602, a semiconductor structure is provided, wherein the semiconductor structure includes a plurality of impurities, such as dopants. In an operation 604, one or more microwave absorbing materials are provided. The microwave absorbing material can increase the electric field density associated with the semiconductor structure. In operation 606, microwave radiation is applied to the microwave-absorbing material and the semiconductor structure to activate the plurality of dopants for fabricating the semiconductor device. The microwave absorbing material is configured to increase the electric field density in response to the microwave radiation to increase absorption of the microwave radiation by the semiconductor structure to activate the dopants.
Fig. 13 illustrates an example diagram of a semiconductor structure, such as a fin field effect transistor (FinFET). In one embodiment, at least one of the semiconductor structures 104, 202, 404, 504 is a FinFET, e.g., the FinFET of fig. 13. In another embodiment, at least one of the semiconductor structures 104, 202, 404, 504 is a planar FET.
Fig. 7 shows another example flow diagram for dopant activation using microwave radiation, i.e., interfacial polarization heating. As shown in fig. 7, in operation 710, a substrate (e.g., substrate 1310 of fig. 13) of a semiconductor structure (e.g., semiconductor structure 104 of fig. 1) is received. As shown in fig. 13, the substrate 1310 includes a surface 1310a and a fin 1310b extending upward from the surface 1310 a. In one embodiment, substrate 1310 comprises silicon, germanium, a III-V compound, or a combination thereof. For example, substrate 1310 comprises approximately 95% silicon.
In operation 720, a gate electrode, for example, gate electrode 1320 of the semiconductor structure of fig. 13, is formed over substrate 1310. In one embodiment, the gate electrode1320 is a dummy gate electrode. In another embodiment, the gate electrode 1320 is a functional gate electrode of a FinFET. As shown in fig. 13, the gate electrode 1320 includes a gate 1320a and spacers 1320b, the gate 1320a extending generally laterally to the fin 1310b, the spacers 1320b being provided on each side of the gate 1320 a. In one embodiment, the gate 1320a is made of polysilicon or any suitable metallic material. Examples of metallic materials include, but are not limited to, TiN, TaN, ZrSi2、MoSi2、TaSi2、NiSi2WN, and other suitable p-type work function metal materials.
In operation 730, a trench is formed that extends into the fin 1310b and is defined by a trench-defining wall (e.g., trench-defining wall 1330 of the semiconductor structure of fig. 13). In one embodiment, the trench has a depth between about 30nm and about 70nm from the surface of the fin 1310 b.
In operation 740, a semiconductor layer (e.g., semiconductor layer 1340 of the semiconductor structure of fig. 13) is formed on the trench-defining walls 1330 to partially fill the trench. For example, the semiconductor layer 1340 has a thickness between about 5nm and about 15 nm. In one embodiment, semiconductor layer 1340 includes germanium. The semiconductor layer 1340 may also include silicon, boron, or a combination thereof. For example, the semiconductor layer 1340 is made of silicon germanium or silicon germanium doped with boron. In some embodiments, the compositional percentage of germanium of the semiconductor layer 1340 is less than about 50%, for example, about 35%. In some embodiments, the concentration of boron in the semiconductor layer 1340 is between about 1E21 atoms/cm3And about 5E21 atoms/cm3E.g., about 3.7E21 atoms/cm3。
In one embodiment, operation 740 includes forming two or more sub-layers of the semiconductor layer 1340 such that the compositional percentage of germanium gradually increases from an outermost sub-layer of the two or more sub-layers to an innermost sub-layer of the two or more sub-layers. In another embodiment, operation 740 includes forming two or more sub-layers of the semiconductor layer 1340 such that the concentration of boron gradually decreases from an outermost sub-layer of the two or more sub-layers to an innermost sub-layer of the two or more sub-layers.
In operation 750, a semiconductor material is formed on the semiconductor layer 1340 (e.g., of fig. 13)Semiconductor material 1350 of the semiconductor structure) to substantially fill the trench. In one embodiment, semiconductor material 1350 includes germanium. Semiconductor material 1350 can also include silicon, boron, or a combination thereof. For example, semiconductor material 1350 is made of silicon germanium or silicon germanium doped with boron. In some embodiments, the compositional percentage of germanium of semiconductor material 1350 is greater than the compositional percentage of germanium of semiconductor layer 1340. For example, the compositional percentage of germanium for semiconductor material 1350 is between about 50% and about 95%. In some embodiments, the concentration of boron of the semiconductor material 1350 is less than the concentration of boron of the semiconductor layer 1340. For example, the semiconductor material 1350 has a boron concentration of between about 2E20 atoms/cm3And about 1E21 atoms/cm3In the meantime.
In operation 760, the semiconductor material 1350 is doped with boron such that an upper layer 1360 of the semiconductor material 1350 has a higher boron concentration than a lower layer of the semiconductor material 1350. For example, the upper layer 1360 has a boron concentration of about 1E21 atoms/cm3And about 5E21 atoms/cm3In the meantime. In one embodiment, the boron of upper layer 1360 has a depth of between about 5nm and about 15nm from the surface of fin 1310 b.
It should be noted that at least one of the trench defining walls 1330, the semiconductor layer 1340, and the semiconductor material 1350 constitute a source/drain (S/D) junction 1370 of the semiconductor structure 104. In one embodiment, the S/D junction 1370 and the gate 1320a define a distance therebetween of between about 1nm and about 9 nm.
In some embodiments, the S/D junction 1370 is formed above a substrate (e.g., a bulk substrate or a silicon-on-insulator (SOI) substrate). In other embodiments, the S/D junction 1370 extends from above the substrate into the substrate.
In operation 770, dopants, i.e., germanium and boron of the semiconductor material 1350, are activated in a manner to be described later.
Fig. 8 illustrates an example flow diagram of operation 770 of fig. 7. As shown in fig. 8, in operation 810, a microwave absorbing material, such as the microwave absorbing material 102 of fig. 1, is received. In operation 820, the distance (e.g., distance d as shown in fig. 1) of the microwave-absorbing material 102 from the semiconductor structure 104 is adjusted to improve dopant activation. In one embodiment, the distance d is between about 2mm and about 10 mm. In operation 830, microwave radiation is applied to the microwave-absorbing material 102 and the semiconductor structure 104 to activate the dopants.
During operation 830, the microwave absorbing material 102 increases the absorption of microwave radiation by the boron of the upper layer 1360 such that the boron of the upper layer 1360 generates heat at a temperature above, for example, 1100 ℃, thereby activating the boron of the upper layer 1360. As a result, a relatively high concentration of activated boron is obtained for the upper layer 1360 of semiconductor material 1350 of the S/D junctions 1370 of the inventive semiconductor structure 104, i.e., substantially the same as the concentration of boron in the upper layer 1360 prior to operation 770. FIG. 12 shows an example plot of concentration versus depth. As shown in fig. 12, in one embodiment, the activated boron concentration of the upper layer 1360 of the semiconductor material 1350 of the S/D junctions 1370 of the semiconductor structure 104 is between about 1E21 atoms/cm3And about 5E21 atoms/cm3In the meantime. In another embodiment, the activated boron of the underlying layer of semiconductor material 1350 has substantially the same concentration as the boron of the underlying layer of semiconductor material 1350 prior to operation 770. For example, the activated boron concentration of the underlying layer of semiconductor material 1350 is between about 2E20 atoms/cm3And about 1E21 atoms/cm3In the meantime. In yet another embodiment, the activated boron of semiconductor layer 1340 has substantially the same concentration as the boron of semiconductor layer 1340 prior to operation 770. For example, the activated boron concentration of the semiconductor layer 1340 is between about 1E21 atoms/cm3And about 5E21 atoms/cm3In the meantime.
Furthermore, during operation 830 (i.e., applying microwave radiation to the microwave-absorbing material 102 and the semiconductor structure 104), the activated germanium and activated boron for the semiconductor material 1350 of the S/D junction 1370 of the inventive semiconductor structure 104 reduces crystal defects resulting from previous operations and achieves a relatively low crystal defect density. In one embodiment, the activated germanium crystal defect density of the semiconductor material 1350 of the S/D junctions 1370 of the semiconductor structure 104 is less than about 1E12 atoms/cm3. For example, the crystal defect density of the activated germanium of semiconductor material 1350 of the S/D junction 1370 of semiconductor structure 104 is about 1E7 atoms/cm3. In another implementationIn one example, the activated boron of the upper layer 1360 of the semiconductor material 1350 of the S/D junction 1370 of the semiconductor structure 104 has a crystal defect density of between about 1E5 atoms/cm3And about 1E7 atoms/cm3In the meantime.
In some embodiments, the activated germanium of semiconductor layer 1340 has substantially the same compositional percentage as the germanium of semiconductor layer 1340 prior to operation 770, e.g., less than about 50%. In other embodiments, the activated germanium of semiconductor material 1350 has substantially the same compositional percentage as the germanium of semiconductor material 1350 prior to operation 770, e.g., between about 50% and 95%.
Further, during operation 830 (i.e., applying microwave radiation to the microwave-absorbing material 102 and the semiconductor structure 104), the substrate 1310 is maintained at a temperature between about 500 ℃ and about 600 ℃. Thus, unlike conventional techniques for dopant activation (e.g., RTA), in which the entire semiconductor structure is heated to a temperature above, for example, 950 ℃, the boron of the upper layer 1360 of the S/D junction 1370 of the semiconductor structure 104 is selectively heated to a higher temperature while the substrate 1310 of the semiconductor structure 104 is at a lower temperature. The substrate 1310 thus acts as a heat spreader and allows the temperature of the semiconductor structure 104 to drop at a faster rate. As a result, the activated boron of the upper layer 1360 of the semiconductor material 1350 of the S/D junctions 1370 of the inventive semiconductor structure 104 has a relatively shallow depth, i.e., substantially the same depth as the boron of the upper layer 1360 prior to operation 770. As shown in fig. 12, in one embodiment, the activated boron of the upper layer 1360 of the semiconductor material 1350 of the S/D junctions 1370 of the semiconductor structure 104 has a depth of between about 5nm and about 15nm from the surface of the S/D junctions 1370.
In an embodiment, after operation 770 (i.e., activation of the dopants), the S/D junctions 1370 have a depth of between about 30nm and about 70 nm. Further, after operation 770, the semiconductor layer 1340 maintains substantially the same thickness, e.g., between about 5nm and about 15 nm. Further, as shown in fig. 13, after operation 770, the S/D junction 1370 and the gate 1320a define a distance D3 between them of between about 1nm and about 9 nm.
Referring again to FIG. 7, in operation 780, S/D contacts, such as S/D contacts 1380 of the semiconductor structure of FIG. 13, are formed on the S/D junctions 1370. Examples of materials for the S/D contacts 1380 include, but are not limited to, tungsten, aluminum, titanium, nickel, cobalt, and the like.
It should be noted that because the semiconductor material 1350 of the S/D junction 1370 has a high compositional percentage of germanium, and because the boron of the upper layer 1360 of the semiconductor material 1350 of the S/D junction 1370 has a shallow depth and a high concentration, the S/D contacts 1380 and the S/D junction 1370 of the semiconductor structure 104 of the present invention have a relatively low contact resistivity therebetween. In one embodiment, the contact resistivity between the S/D contacts 1380 and the S/D junctions 1370 of the semiconductor structure 104 is less than about 5E-9 ohm-cm2. For example, the contact resistivity between the S/D contacts 1380 and the S/D junctions 1370 of the semiconductor structure 104 is about 8E-10 ohm-cm2。
Fig. 9 illustrates another example flow diagram of operation 770 of fig. 7. As shown in fig. 9, in operation 910, a pair of microwave-absorbing materials, e.g., microwave-absorbing materials 204, 206 of fig. 2, is received, and a semiconductor structure, e.g., semiconductor structure 202 of fig. 2, is placed between the microwave-absorbing materials 204, 206. In operation 920, the distance between the microwave-absorbing material 204 and the surface of the semiconductor structure 202 (e.g., distance d1 as shown in fig. 2) is adjusted to improve dopant activation. In one embodiment, distance d1 is between about 2mm and about 10 mm. In operation 930, the distance between the microwave-absorbing material 206 and the other surface of the semiconductor structure 202 (e.g., distance d2 as shown in fig. 2) is adjusted to improve dopant activation. In one embodiment, distance d2 is between about 2mm and about 10 mm. In operation 940, microwave radiation is applied to the microwave absorbing material 204, 206 and the semiconductor structure 202 to activate the dopants.
FIG. 10 illustrates another example flow diagram of operation 770 of FIG. 7. As shown in fig. 10, in an operation 1010, a microwave-absorbing material, such as the microwave-absorbing material 402 of fig. 4, is formed on a surface of (e.g., a compliant) semiconductor structure, such as the semiconductor structure 404 of fig. 4. In operation 1020, the thickness of the microwave absorbing material 402 is adjusted (e.g., between about 30nm and about 250 nm) to improve dopant activation. In operation 1030, microwave radiation is applied to the microwave absorbing material 402 and the semiconductor structure 404 to activate the dopants. In operation 1040, the microwave absorbing material 402 is removed from the semiconductor structure 404, for example, by wet etching, dry etching, chemical mechanical polishing, or a combination thereof.
FIG. 11 illustrates another example flow diagram of operation 770 of FIG. 7. As shown in fig. 11, in an operation 1110, a first microwave-absorbing material, e.g., microwave-absorbing material 502 of fig. 5, is formed on a surface of (e.g., a compliant) semiconductor structure, e.g., semiconductor structure 504 of fig. 5. In operation 1120, the thickness of the microwave absorbing material 502 is adjusted (e.g., between about 30nm and about 250 nm) to improve dopant activation. In an operation 1130, a second microwave-absorbing material, such as the microwave-absorbing material 506 of fig. 5, is formed on another surface of the (e.g., compliant) semiconductor structure 504. In operation 1140, the thickness of the microwave absorbing material 506 is also adjusted (e.g., between about 30nm and about 250 nm) to improve dopant activation. In operation 1150, microwave radiation is applied to the microwave absorbing material 502, 506 and the semiconductor structure 504 to activate the dopants. In operation 1160, the microwave absorbing material 502, 506 is removed from the semiconductor structure 504.
In one embodiment, a lightly doped S/D (LDD) is formed in relation to a substrate of a semiconductor structure. The formation of the LDD includes: doping a region of the semiconductor structure with a plurality of dopants; receiving a microwave absorbing material or forming a microwave absorbing material on a semiconductor structure; adjusting the distance between the microwave absorbing material and the semiconductor structure or adjusting the thickness of the microwave absorbing material; and applying microwave radiation to the microwave absorbing material and the semiconductor structure.
In the semiconductor structure, the germanium of the semiconductor material has less than about 1E12 atoms/cm3Crystal defect density of (2).
In a semiconductor structure, wherein the germanium of the semiconductor material has about 1E7 atoms/cm3Crystal defect density of (2).
In a semiconductor structure, wherein: the S/D junction further comprises a semiconductor layer comprising germanium; the semiconductor material is formed on the semiconductor layer; the compositional percentage of germanium of the semiconductor material is greater than the compositional percentage of germanium of the semiconductor layer.
In a semiconductor structure wherein the boron concentration of the upper layer is greater than about 1E21 atoms/cm3。
In the semiconductor structure, wherein the boron concentration of the upper layer is about 5E21 atoms/cm3。
In the semiconductor structure, further comprising: an S/D contact formed on the S/D junction, wherein a contact resistivity of the S/D contact and the S/D junction is less than about 5E-9 ohm-cm2。
In the semiconductor structure, further comprising: an S/D contact formed on the S/D junction, wherein a contact resistivity of the S/D contact and the S/D junction is about 8E-10 ohm-cm2。
In a semiconductor structure, wherein the boron of the upper layer has a depth of between about 5nm and about 15nm from a surface of the S/D junction.
In the semiconductor structure, wherein the boron of the upper layer has an atomic/cm of between about 1E53And about 1E7 atoms/cm3Crystal defect density in between.
In one approach, the boron concentration of the upper layer is greater than about 1E21 atoms/cm3。
In one method, the boron concentration of the upper layer is about 5E21 atoms/cm3。
In one method, wherein: forming the S/D junction further comprises forming a semiconductor layer comprising germanium and having a compositional percentage of germanium that is less than a compositional percentage of germanium of the semiconductor material; and the semiconductor material is formed on the semiconductor layer.
In one method, the compositional percentage of germanium of the semiconductor material is greater than about 50%.
In one method, the compositional percentage of germanium of the semiconductor material is about 95%.
In one method, further comprising: activating the germanium and boron of the semiconductor material by applying microwave radiation to the microwave absorbing material and the semiconductor structure, the microwave absorbing material configured to increase absorption of the microwave radiation by the germanium and boron of the semiconductor material.
In one method, further comprising: activating germanium and boron of the semiconductor material by applying microwave radiation to a microwave absorbing material and the semiconductor structure, the microwave absorbing material configured to increase absorption of the microwave radiation by the germanium and boron of the semiconductor material, wherein activating germanium and boron of the semiconductor material further comprises: forming the microwave absorbing material on the semiconductor structure; and adjusting the thickness of the microwave absorbing material.
In one method, further comprising: activating germanium and boron of the semiconductor material by applying microwave radiation to a microwave absorbing material and the semiconductor structure, the microwave absorbing material configured to increase absorption of the microwave radiation by the germanium and boron of the semiconductor material, wherein activating germanium and boron of the semiconductor material further comprises: receiving the microwave absorbing material; and adjusting the distance between the microwave absorbing material and the semiconductor structure.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples that occur to those skilled in the art. One skilled in the relevant art will recognize, however, that the various embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. Well-known structures, materials, or components are not shown or described in detail within the pit to avoid obscuring aspects of various embodiments of the invention. The various embodiments shown in the figures are representative of illustrative examples and are not necessarily drawn to scale. The particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. In other embodiments, various additional layers and/or structures may be included and/or described components may be omitted. Various operations may be described as discrete operations in turn, in a manner that is most helpful in understanding the present invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. The operations described herein may be performed in series or in parallel in a different order than the described embodiments. Various additional operations may be implemented and/or described. In additional embodiments, operations may be omitted.
This written description and the claims that follow may include terms, such as left, right, top, bottom, over, under, first, second, etc., that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical positions may refer to the case where the top side (or active surface) of a substrate or integrated circuit is the "top" face of the substrate; the substrate may be in virtually any orientation such that the "top" side of the substrate may be lower than the "bottom" side in a standard ground frame of a reference frame and may still fall within the meaning of the term "top". Unless expressly stated otherwise, the term "on" as used herein (including in the claims) may not mean that a first layer "on" a second layer is directly on and in direct contact with the second layer; there may be a third layer or other structure between the first layer and the second layer on the first layer. Unless expressly stated otherwise, the term "beneath" as used herein (including in the claims) may not mean that a first layer "beneath" a second layer is directly beneath and in direct contact with the second layer; there may be a third layer or other structure between the first layer and the second layer below the first layer. Embodiments of a device or article described herein may be manufactured, used, or shipped in a variety of positions and orientations. Those skilled in the art will recognize various equivalent combinations and substitutions for various components illustrated in the figures.
Claims (10)
1. A semiconductor structure, comprising:
a substrate;
a source/drain (S/D) junction associated with the substrate and including a semiconductor material and a semiconductor layer underlying the semiconductor material, the semiconductor material including germanium and the semiconductor materialBetween 50% and 95%, wherein the germanium of the semiconductor material has less than 1E12 atoms/cm3The crystal defect density of (3);
a source/drain contact over and in direct contact with the semiconductor material; and
a gate electrode over the substrate and disposed at one side of the source/drain junctions, wherein the gate electrode includes a gate and spacers disposed on each side of the gate, wherein sidewalls of source/drain contacts are in contact with a respective one of the spacers,
wherein the compositional percentage of germanium of the semiconductor material and the compositional percentage of germanium of the semiconductor layer increase from layer to layer in a direction toward the source/drain contact,
wherein the boron concentration of the semiconductor material in the depth range from the surface of the semiconductor material to between 5nm and 15nm is greater than 1E21 atoms/cm3,
Wherein the source/drain contact extends horizontally from the semiconductor layer on one side of the source/drain junction through the semiconductor material to the semiconductor layer on the other side of the source/drain junction and is in contact with the semiconductor layer.
2. The semiconductor structure of claim 1, wherein the germanium of the semiconductor material has 1E7 atoms/cm3Crystal defect density of (2).
3. The semiconductor structure of claim 1, wherein the semiconductor layer comprises boron.
4. The semiconductor structure of claim 1, wherein a contact resistivity of the source/drain contact and the source/drain junction is less than about 5E-9 ohm-cm2。
5. The semiconductor structure of claim 1, wherein the source/drain contactAnd the source/drain junction has a contact resistivity of 8E-10 ohm-cm2。
6. A semiconductor structure, comprising:
a substrate; and
a source/drain (S/D) junction associated with the substrate and including a semiconductor material and a semiconductor layer underlying the semiconductor material, the semiconductor material having:
a lower layer comprising germanium, and
an upper layer comprising germanium and doped with boron, the upper layer having a higher concentration of boron than the lower layer;
wherein a concentration of boron of an upper layer of the semiconductor material in a depth range from a surface of the semiconductor material to between 5nm and 15nm is greater than 1E21 atoms/cm3The germanium of the semiconductor material has less than 1E12 atoms/cm3The crystal defect density of (3);
a source/drain contact over and in direct contact with the semiconductor material; and
a gate electrode over the substrate and disposed at one side of the source/drain junctions, wherein the gate electrode includes a gate and spacers disposed on each side of the gate, wherein sidewalls of source/drain contacts are in contact with a respective one of the spacers,
wherein the compositional percentage of germanium of the semiconductor material and the compositional percentage of germanium of the semiconductor layer increase from layer to layer in a direction toward the source/drain contact,
wherein the source/drain contact extends horizontally from the semiconductor layer on one side of the source/drain junction through the semiconductor material to the semiconductor layer on the other side of the source/drain junction and is in contact with the semiconductor layer.
7. The semiconductor structure of claim 6, wherein the boron concentration of the upper layer is 5E21 atoms/cm3。
8. The semiconductor structure of claim 6, wherein a contact resistivity of the source/drain contact and the source/drain junction is less than 5E-9 ohm-cm2。
9. The semiconductor structure as set forth in claim 6,
wherein the source/drain contact and the source/drain junction have a contact resistivity of 8E-10 ohm-cm2。
10. A method of forming a semiconductor structure, comprising:
a substrate receiving a semiconductor structure;
forming a gate electrode over the substrate, wherein the gate electrode includes a gate and spacers disposed on each side of the gate,
forming a source/drain (S/D) junction associated with the substrate, wherein forming the source/drain junction comprises:
forming a semiconductor material comprising germanium, wherein the germanium of the semiconductor material has less than 1E12 atoms/cm3A crystal defect density of, and
doping the semiconductor material with boron such that the concentration of boron of an upper layer of the semiconductor material is higher than the concentration of boron of a lower layer of the semiconductor material, wherein the concentration of boron of the upper layer is greater than 1E21 atoms/cm in a depth range from the surface of the semiconductor material to between 5nm and 15nm3;
The composition percentage of germanium of the source/drain (S/D) junctions increases layer by layer in a direction away from the substrate,
activating germanium and boron of the semiconductor material by applying microwave radiation to the microwave absorbing material and the semiconductor structure such that the concentration of germanium and boron after activation is substantially the same as the concentration of germanium and boron at the same height before activation, and the microwave radiation causes boron of the upper layer to generate heat at a temperature above 1100 ℃ while the substrate is maintained between 500 ℃ and 600 ℃, thereby performing activation of boron; and
forming source/drain contacts on the source/drain junctions, wherein sidewalls of the source/drain contacts are in contact with a respective one of the spacers,
wherein a depth of activated boron of the upper layer is substantially the same as a depth of boron prior to the activation.
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