CN113590150A - Memory bank control method, program upgrading method and device - Google Patents

Memory bank control method, program upgrading method and device Download PDF

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Publication number
CN113590150A
CN113590150A CN202110734704.1A CN202110734704A CN113590150A CN 113590150 A CN113590150 A CN 113590150A CN 202110734704 A CN202110734704 A CN 202110734704A CN 113590150 A CN113590150 A CN 113590150A
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memory bank
program
memory
bank
instruction operation
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Inventor
丁燕
庞振江
王文赫
侯战斌
崔国宇
王大伟
何杰
夏军虎
林玲
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Beijing Smartchip Microelectronics Technology Co Ltd
Hangzhou Vango Technologies Inc
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Beijing Smartchip Microelectronics Technology Co Ltd
Hangzhou Vango Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Stored Programmes (AREA)

Abstract

The invention provides a memory bank control method, a program upgrading method and a device, and belongs to the technical field of chips. The method comprises the following steps: selecting a read instruction operation pointing to a program to be executed in a first memory bank having the program; selecting a write instruction operation pointing to the program to be executed in a second memory bank in which the program exists; and after the write-in instruction operation is completed, switching the read-out instruction operation to the second memory bank for execution. The invention can be used for memory bank control and program upgrade.

Description

Memory bank control method, program upgrading method and device
Technical Field
The present invention relates to the field of chip technology, and in particular, to a memory bank control method, a memory bank control system, a memory bank control device, a program upgrade method, a device having a program upgrade function, an electronic device, and a computer-readable storage medium.
Background
The Bootloader is a section of code executed before the chip enters the operating system after being reset (hard reset), and is also called a boot program or a boot program, the Bootloader completes the transition from hardware boot to operating system boot, and the Bootloader provides a basic operating environment for operating the operating system. Common Bootloader starting modes are mainly divided into a network starting mode, a disk starting mode and a Flash memory (Flash memory, also referred to as Flash or Flash memory for short) starting mode. The Flash starting mode is the most common mode, for example, NOR Flash is used, random access can be supported, codes of application programs can be directly executed on the Flash, operation is convenient and simple, cost is saved, and the application programs are difficult to upgrade simultaneously when the programs are executed. Therefore, how to reasonably control the read-write logic of the memory and simply realize the program upgrading is a troublesome problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a memory control method, a program upgrading method and a device, which avoid the problem that programming or upgrading of a program is difficult to execute due to the fact that erasing operation is difficult to realize in the instruction reading process of a CPU (Central processing Unit), and further improve the online updating capability of the program in a memory, the chip design difficulty and the cost.
In order to achieve the above object, an embodiment of the present invention provides a memory bank control method, including:
selecting a read instruction operation pointing to a program to be executed in a first memory bank having the program;
selecting a write instruction operation pointing to the program to be executed in a second memory bank in which the program exists;
and after the write-in instruction operation is completed, switching the read-out instruction operation to the second memory bank for execution.
Specifically, the bank control method is performed by a logic device.
Specifically, the logic device includes a data selector.
Specifically, in the memory bank control method, the logic device is in a first operating mode or a second operating mode;
the logic device in the second operating mode selects read command operations and/or write command operations directed to a program in the first memory bank to be executed in the second memory bank, wherein,
the read command operation and/or the write command operation are selected by the logic device in the first operation mode to be executed in the first memory bank.
Specifically, in the bank control method,
the logic device in the second operating mode selects read command operations and/or write command operations directed to programs in the second memory bank to be executed in the first memory bank, wherein,
the read command operation and/or the write command operation are selected by the logic device in the first operating mode to be executed in the second memory bank.
Specifically, in the bank control method,
the logic device in said first mode of operation is switched by a control signal to the logic device in said second mode of operation,
the control signals are determined by the processor and the bus in the idle state.
Specifically, the operation of selecting the write command directed to the program is performed in a second memory bank in which the program is present, wherein,
the program in the second memory bank is the copied program in the first memory bank.
Specifically, the operation of selecting the write command directed to the program is performed in a second memory bank in which the program is present, wherein,
the memory address of the program in the second memory bank is identical to the memory address in the first memory bank.
Specifically, during the execution of the write command operation,
the read instruction operation is executed simultaneously, or
Has finished executing the read instruction operation, or
Waiting for the read instruction operation to be performed.
Specifically, before the write command operation is executed, the bank control method further includes:
selecting an erase instruction operation directed to the program is performed in a second memory bank having the program, wherein the second memory bank has a flash memory medium.
Specifically, before the switching the read instruction operation to the second bank for execution, the bank control method further includes:
determining that a bus is in an idle state, wherein the bus is connected with the first memory bank and also connected with the second memory bank.
Specifically, the bank control method further includes:
and copying the program in the second memory bank to the first memory bank.
Specifically, the bank control method further includes:
a soft reset is performed, or alternatively,
determining that a bus is in an idle state, wherein the bus is connected with the first memory bank and also connected with the second memory bank.
An embodiment of the present invention provides a bank control system, including:
the first selection module is used for selecting a reading instruction operation pointing to a program to be executed in a first memory bank with the program;
the second selection module is used for selecting the write instruction operation pointing to the program to be executed in a second memory bank with the program;
and the switching module is used for switching the reading instruction operation to the second memory bank for execution after the writing instruction operation is completed.
An embodiment of the present invention provides a bank control device, including:
the selection logic circuit is connected with the processor, is respectively connected with the first memory bank and the second memory bank, and is used for selecting the reading instruction operation of the processor pointing to the program to be executed in the first memory bank with the program;
the selection logic circuit is also used for selecting the processor to execute a write instruction operation pointing to the program in a second memory bank with the program;
and the switching logic circuit is connected with the processor and the selection logic circuit and is used for switching the reading instruction operation to the second memory bank for execution after the writing instruction operation is completed.
Specifically, the selection logic circuit has a data selector.
Specifically, the selection logic circuit includes a first data selector;
the first data selector is connected with the processor through a first bus interface and a second bus interface and used for inputting data of the first data selector;
the first data selector is also connected with the first memory bank through a third bus interface and used for outputting data of the first data selector.
Specifically, the selection logic circuit further includes a second data selector;
the second data selector is connected with the processor through the first bus interface and the second bus interface and used for inputting data of the second data selector;
the second data selector is also connected with the second memory bank through a fourth bus interface and used for outputting data of the second data selector.
Specifically, the switching logic circuit has a third data selector;
the third data selector is connected to a register, wherein the register is configured by the processor for data input of the third data selector;
the third data selector is further connected to the first data selector and the second data selector respectively, and is configured to switch between data output of the first data selector and data output of the second data selector.
Specifically, the first memory bank comprises a first memory controller and a first flash memory connected with the first memory controller,
the second memory bank comprises a second memory controller and a second flash memory connected with the second memory controller;
the selection logic circuit is respectively connected with the first storage controller and the second storage controller.
Specifically, the storage capacity of the first flash memory is the same as the storage capacity of the second flash memory.
Specifically, the first flash memory serves as a main memory, and the second flash memory serves as a slave memory;
the storage capacity of the second flash memory is larger than that of the first flash memory.
The embodiment of the invention provides a program upgrading method, which comprises the following steps:
receiving an upgrade request of a program, wherein the program is configured in a first memory bank and a second memory bank;
by using the aforementioned bank control method, the method for executing the upgrade operation corresponding to the upgrade request on the program includes:
selecting a read instruction operation directed to the program to execute in the first memory bank and selecting a write instruction operation corresponding to the upgrade request to execute in the second memory bank, an
And after the write-in instruction operation is completed, switching the read instruction operation pointing to the program to the second memory bank for execution.
An embodiment of the present invention provides an apparatus having a program upgrade function, where the apparatus includes:
a first memory bank configured to store a boot program and an application program;
a second memory bank configured to store the boot program and the application program copied from the first memory bank;
the memory bank control device is configured to select a read instruction operation directed to the application program to be executed in the first memory bank, and select a write instruction operation corresponding to an upgrade request to be executed in the second memory bank, wherein the upgrade request is an upgrade request of the application program received by a processor;
the memory bank control device is further configured to switch a read instruction operation directed to the application program to the second memory bank for execution after the write instruction operation is completed.
In another aspect, an embodiment of the present invention provides an electronic device, including:
at least one processor;
a memory coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the at least one processor implements the aforementioned bank control method or the aforementioned method of program upgrading method by executing the instructions stored by the memory.
In still another aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the computer to execute the foregoing bank control method or the foregoing method for program upgrading.
The invention provides the selection logic and the switching logic of the read-write control of the memory banks, the corresponding instruction operation initiated by the program is not required to be changed, the instruction operation is directly and respectively executed in different memory banks, the invention has the characteristics of multiple working modes, external equipment is not required to be used for program upgrading, the chip design cost and the miniaturization difficulty are improved, users are not obviously interrupted by using intervention in the upgrading process, and the invention is a non-inductive program upgrading.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram of the main method steps of an embodiment of the present invention;
FIG. 2 is a schematic diagram of the main modules of an exemplary memory architecture according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the main modules of an exemplary memory architecture according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the main blocks of an exemplary logic device according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the main modules of an exemplary program storage architecture according to the present invention;
FIG. 6 is a memory diagram illustrating exemplary executed instruction operations according to an embodiment of the present invention;
FIG. 7 is a memory diagram illustrating exemplary executed instruction operations, in accordance with an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
When an application needs to be upgraded, a boot code (an execution file in a boot process, which may be a binary file, such as bin or elf) of a user is loaded from an external device such as a Secure Digital Memory Card (SD)/Embedded Multimedia Card (eMMC), and the boot code may be tried to be copied from the external SD/eMMC to a Memory (RAM) in a chip for execution, and the application is stored in Flash. However, it is difficult to complete the application program upgrade without accessing the external device, which results in inconvenient upgrade operation, and also requires the chip design to support the external device, which results in higher chip design and manufacturing cost. In view of the above, the embodiment of the present invention provides a solution for bank control and program upgrade.
Example 1
An embodiment of the present invention provides a memory bank control method, as shown in fig. 1, where the memory bank control method includes:
s1) selecting a read instruction operation directed to a program to be executed in a first memory bank in which the program is present;
s2) selecting a write command operation directed to the program to be executed in a second memory bank in which the program exists;
s3) switching the read command operation to the second bank for execution after the write command operation is completed, wherein steps S1) and S2) are not limited to a specific sequence, and may be synchronous or asynchronous.
In some implementations, the Memory banks (Memory banks) are physical, addressable Memory cells. A processor (e.g., CPU) may read and write data in the first and second memory banks under a standard bus architecture. The standard bus architecture is arbitrarily selectable. Taking the universal Bus Architecture as an example, under an Advanced Microcontroller Bus Architecture (AMBA), the Bus may be an AHB (Advanced High performance Bus) Bus, and the AHB Bus may generally include a Master device (Master) interface, an Arbiter (Arbiter), a Decoder (Decoder), and a Slave device (Slave) interface.
The first memory bank and the second memory bank in the embodiment of the present invention may be connected to the AHB bus by using two slave interfaces, and may be specifically connected to the AHB bus by using a logic device through the two slave interfaces, which will be further described later. For illustrative purposes, the first memory bank may include a first memory controller (also referred to as a Flash controller) and a first Flash memory (Flash), the second memory bank may include a second memory controller and a second Flash memory, the memories being memory that may be selected as non-Flash media, such as random access memory or read only memory; accordingly, some command operations should be present in response to the memory, e.g., an erase command operation needs to be performed before the flash memory is reprogrammed.
On the basis of the bus architecture, programs can be configured and operations can be performed on the various memory banks. In one embodiment, the programs in the memory banks are read or reprogrammed by an input output request (I/O request) mechanism. For example, the first memory bank and the second memory bank may each be configured with a program, the program in the memory bank may initiate one or more access operations through the I/O request when executed by the processor, and the access operations (the processor participating in the execution) may include a READ instruction operation (READ), an ERASE instruction operation (ERASE), and a WRITE instruction operation (WRITE).
In addition, the operation and maintenance program can initiate one or more task operations in an I/O request mode. The operation and maintenance program can be used for reprogramming or upgrading programs in the memory bank; in some cases, the operation and maintenance program may be configured as part of a program in a memory bank. The task operation may be a plurality of access operations, and the task operation includes an upgrade operation (also called a reprogramming operation), a blank address segment programming operation, a copy operation, and the like, and the task operation and the access operation may each include a Logical Block Address (LBA) and read/write data, and may each be a read instruction operation, an erase instruction operation, and/or a write instruction operation directed to a program.
In some cases, the LBA may be mapped to a physical address of a memory bank storing program data via an address translation table (address translation table), and (Nbank, Nblock, Npage) may be obtained, where Nbank may be a memory bank number (integer) of the program in the memory bank, Nblock may be a block number in the memory bank, and Npage may be a page number in the block, and these task operations may be translated to a physical location of the program so that the read instruction operation, the erase instruction operation, and/or the write instruction operation are completed.
In other cases, the LBA may also be mapped with a physical address of the storage medium via a Flash Translation Layer (FTL), where the FTL is generally software having a logical address-physical address mapping function, and may specifically obtain (Nbank, Nblock, Npage), and at this time, these task operations may be translated to a physical location of the program, so as to facilitate the execution of the read instruction operation, the erase instruction operation, and/or the write instruction operation.
In one embodiment, the programs in the first memory bank are available in a programming operation and the programs in the second memory bank are available in a copy operation, wherein the programs may include boot programs and application programs, which may be used for device hardware usage and/or to implement software functions, etc. Before the copying is executed, preprocessing operations of storage spaces (namely storage capacity) such as partitioning and formatting can be performed on the Flash in the second storage body, so that the storage partitions and formats of the Flash in the second storage body are processed into a form consistent with the Flash in the first storage body. The copy operation may be implemented by a configured copy function or a copy instruction that matches hardware. It will be appreciated that the program in the second memory bank may also be programmed after the preprocessing operation, but that verification is required to be performed again to verify whether it is consistent with the program in the first memory bank.
After being copied to Flash in the second storage body, the relative position of the data of the boot program and the application program in the second storage body to the address of Flash in the first storage body is the same as the relative position of the address of Flash in the first storage body, that is, the physical addresses of the same program in the first storage body and the second storage body may only have a difference in storage body number, which may be understood in the embodiment of the present invention as the storage addresses of the programs in the respective storage bodies being the same. For example, the size of the storage space of Flash in the second storage volume and Flash in the first storage volume may also be the same, and the size of the storage space may be the size of the storage space that can be actually used; the first storage body and the second storage body can select one Flash as a main Flash, the other Flash as a slave Flash and the slave Flash as a backup of the main Flash, wherein the slave Flash can provide a complete clone backup, and addresses and data contents of the two flashes can be identical.
For the logic device mentioned in the foregoing embodiment, the logic device may form selection logic in a bus, and may implement read-write control of a memory bank.
In the first working mode of the embodiment of the present invention, the logic device may select each instruction operation pointing to the Flash storage address in the first storage volume as pointing to the Flash storage address in the first storage volume, and may also select each instruction operation pointing to the Flash storage address in the second storage volume as pointing to the Flash storage address in the second storage volume; the working mode can be applied to a program for normal work.
In the second working mode of the embodiment of the present invention, the logic device may select each instruction operation pointing to the Flash storage address in the first storage volume as the same storage address pointing to Flash in the second storage volume, and may also select each instruction operation pointing to the Flash storage address in the second storage volume as the Flash storage address in the first storage volume; the working mode can be suitable for the program needing to be operated and maintained, and the specific operation of the operation and maintenance can be upgrading, changing the program configuration and the like.
In a program executionIn an embodiment, in the process that a program in a memory bank is executed, the program may initiate a read instruction operation pointing to a Flash memory address (address field where the program is located) in a first memory bank through an I/O request of an access operation, the logic device may be in a first working mode at this time, the logic device selects the read instruction operation pointing to the Flash memory address in the first memory bank as pointing to the Flash memory address in the first memory bank, and if there is a read instruction operation, an erase instruction operation, and/or a write instruction operation pointing to the Flash memory address in any memory bank, the logic device also performs the same selection logic processing. To briefly illustrate this selection logic, in an exemplary embodiment, as shown in FIG. 2, the selection logic may be written as
Figure BDA0003141172460000111
Wherein N0 is the bank number of the first bank 102(Flash memory bank 0), and NaIs the block number, N, of the first bank 102bIs the page number, s, of the first memory bank 1021For the first mode of operation of the logic device 101, the logical arrow is selected
Figure BDA0003141172460000112
On the left and right sides (N)0，Na，Nb) The addresses are Flash memory addresses in the first memory bank 102, W/R/E is one of a write instruction operation, a read instruction operation, and an erase instruction operation, and the same applies to the second memory bank 103(Flash memory bank 1), and details are not repeated.
In an embodiment of program upgrading, the program in the storage may be upgraded according to the configuration of the master Flash and the slave Flash, and the processor may mainly execute the program in the master Flash. The operation and maintenance program may initiate an erase instruction operation and a write instruction operation pointing to (from) a Flash memory address (address field where the program is located in the memory bank) in the second memory bank 103 through the I/O request of the upgrade operation, and a memory bank number of a specific memory address may be a memory bank number of the second memory bank 103. At this time, the process can be completed in multiple stages.
In the first stage, the logic deviceThe member 101 may be in a first operating mode s1. The logic device 101 selects the operation and maintenance program (executed by the processor) to point to the erase instruction operation and the write instruction operation of the program, and points to the Flash memory address in the second memory bank 103, similarly, as shown, it can be noted as
Figure BDA0003141172460000113
Wherein N is1For the bank number of the second memory bank 103, an arrow in the selection logic
Figure BDA0003141172460000121
On the left and right sides (N)1，Na，Nb) Are all Flash memory addresses in the second memory bank 103.
In the second phase, after the erase command operation and the write command operation are performed, a control signal (e.g., 0 to 1) may be applied to the logic device 101, and the control signal may be used to change the logic device from the first operation mode s1Switching to a second operating mode s2The control signal may be configured based on the operating state of the bus, for example, the control signal is applied when the bus is in an idle state, wherein the control signal may be implemented by a pre-configured script or program (the storage location may be arbitrary) responding to the program upgrade operation, or may be implemented by the operation and maintenance program. In this phase, after waiting until the bus is in an idle state, the operation mode of the logic device 101 is changed from the first operation mode s by the control signal1Switching to a second operating mode s2。
In the third phase, as shown in FIG. 3, the logic device 101 may be in the second operation mode s2. The upgraded program is ready to be used, and the upgraded program executed by the processor initiates a read instruction operation pointing to the Flash memory address (address field of the upgraded program) in the first memory bank 102 through the I/Orequest of the access operation. The logic device 101 switchably selects a read instruction operation directed to the upgraded program as a storage address directed to Flash in the second storage 103. Can be recorded as
Figure BDA0003141172460000122
As can be seen, the arrow in the selection logic
Figure BDA0003141172460000123
On the left and right sides (N)0，Na，Nb) And (N)1，Na，Nb) Respectively a Flash memory address in the first memory bank 102 and a Flash memory address in the second memory bank 103. Therefore, the corresponding change of the storage address is not needed in the upgraded program, the logic device 101 can switch the storage address, the use of the user corresponding to the program in the memory bank cannot generate visible interruption, and the difficulty in upgrading the program in the memory bank and the difficulty in maintaining the program are avoided.
In some extensibility implementation phases, the operation and maintenance program may perform copy operations and normal data check operations, etc. after the third phase. And the operation and maintenance program initiates an erasing instruction operation and a writing instruction operation pointing to a Flash storage address (the address field where the original program is located and not upgraded) in the second storage body through the I/Orequest of the copy operation. The logic device switches the erasing instruction operation and the writing instruction operation pointing to the original program into the storage place commander pointing to the Flash in the first storage body, which can be recorded as
Figure BDA0003141172460000131
Therefore, the corresponding change of the storage address is not needed in the operation and maintenance program, the storage address can be switched by the logic device, and the program upgrading in the two memory banks is realized.
In a further extensive implementation phase, after the execution of the copy of the program in the first memory bank is completed, the application of a control signal to the logic device may be stopped, the stopping of the control signal being available for the logic device to operate from the second operation mode s2Switch back to the first operating mode s1Similarly, the control signal may be stopped until the bus is idle.
In a further stage of extensibility, the operation and maintenance program optionally requests a reset to be performed after the copy operation is performed.The reset may be a soft reset or a hard reset. The soft reset can be that the processor loads from the initial address of the upgraded program again through the configured code; the hard reset may be a power-up of the processor and a system boot after performing a power-down. After the reset has been performed, the logic device may revert to the first operating mode s1。
It should be added that the logic device in the foregoing implementation already has an isolated channel of the memory bank, and can independently transmit data. Advantageously, in the first stage, whether during execution of an erase command operation of the program in the second memory bank or during execution of a write command operation of the program in the second memory bank, the program in the first memory bank may be simultaneously executed by the processor for a read command operation, an erase command operation or a write command operation, or may wait for execution of a command operation. For example, step S1) may be performed during normal execution of the program in the memory bank, or may be performed during the first stage of program upgrade. For example, step S2) may be executed in the first stage of program upgrade, or may be executed by the specified program during program execution in the memory bank, or may be executed by the specified program in the third stage. Exemplarily, step S3) may be performed by the third phase of the program upgrade.
The memory bank of the embodiment of the invention can be used as two independent memory banks and can also be used as a master memory unit and a slave memory unit which are mirror images of each other, when the memory bank is used as the master memory unit and the slave memory unit, one memory bank is used as the mirror image of the other memory bank, the read operation and the erase operation can be simultaneously completed, the user experience is good, and the phenomenon of pause caused by upgrading of an application program does not exist.
Example 2
The embodiment of the present invention is the same inventive concept as embodiment 1, and the embodiment of the present invention provides a bank control system, which may include:
the first selection module is used for selecting a reading instruction operation pointing to a program to be executed in a first memory bank with the program;
the second selection module is used for selecting the write instruction operation pointing to the program to be executed in a second memory bank with the program;
and the switching module is used for switching the reading instruction operation to the second memory bank for execution after the writing instruction operation is completed.
In some implementations, the various modules described above can be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SoC), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. It should be noted that, when the term "module" is applied to a specific product, it can be understood as "unit", "logic circuit" (entity) "," (software implementation) functional module "," element "," component ", and the like; in some cases, the second selection module may be the same selection module as the first selection module.
Specifically, the bank control system is implemented by a logic device, wherein the logic device comprises a data selector.
Specifically, in the memory bank control system, the logic device is in a first working mode or a second working mode;
the logic device in the second operating mode selects read command operations and/or write command operations directed to a program in the first memory bank to be executed in the second memory bank, wherein,
the read command operation and/or the write command operation are selected by the logic device in the first operation mode to be executed in the first memory bank.
Specifically, in the memory bank control system, the logic device in the second operation mode selects a read instruction operation and/or a write instruction operation directed to a program in the second memory bank to be executed in the first memory bank, wherein,
the read command operation and/or the write command operation are selected by the logic device in the first operating mode to be executed in the second memory bank.
In particular, in the bank control system,
the logic device in said first mode of operation is switched by a control signal to the logic device in said second mode of operation,
the control signals are determined by the processor and the bus in the idle state.
Specifically, the program in the second memory bank is the copied program in the first memory bank.
Specifically, the memory address of the program in the second memory bank is identical to the memory address in the first memory bank.
Specifically, in the process of executing the write instruction operation, the read instruction operation is executed at the same time, or the read instruction operation is completed, or the read instruction operation is waited to be executed.
Specifically, before the write command operation is executed, the bank control system further includes:
and the third selection module is used for selecting the erasing instruction operation pointing to the program to be executed in a second memory bank with the program, wherein the second memory bank is provided with a flash memory medium.
Specifically, the bank control system further includes:
a determining module configured to determine that a bus is in an idle state, wherein the bus is connected to the first memory bank and is also connected to the second memory bank.
Specifically, the bank control system further includes:
and the copying module is used for copying the program in the second storage body to the first storage body.
Specifically, the bank control system further includes:
a reset module to perform a soft reset, or,
a determining module configured to determine that a bus is in an idle state, wherein the bus is connected to the first memory bank and is also connected to the second memory bank.
Example 3
The embodiment of the present invention belongs to the same inventive concept as embodiments 1 and 2, and provides a bank control device, which may be understood as a device product of the control system of embodiment 2 in some cases. The bank control apparatus may include:
the selection logic circuit is connected with the processor, is respectively connected with the first memory bank and the second memory bank, and is used for selecting the reading instruction operation of the processor pointing to the program to be executed in the first memory bank with the program;
the selection logic circuit is also used for selecting the processor to execute a write instruction operation pointing to the program in a second memory bank with the program;
and the switching logic circuit is connected with the processor and the selection logic circuit and is used for switching the reading instruction operation to the second memory bank for execution after the writing instruction operation is completed.
In some implementations, the bank control device may include the logic device in embodiment 1, and the logic device may be a selection logic circuit, and may preferably be a selection logic circuit and a switching logic circuit. The first bank and the second bank of embodiment 1 can be used for the first bank and the second bank.
The selection logic may have a data selector. Specifically, the selection logic circuit has a first data selector and a second data selector. The first data selector can be connected with the processor through the first bus interface and the second bus interface and used for inputting data of the first data selector; the first data selector is also connected with the first memory bank through a third bus interface and used for outputting data of the first data selector. The second data selector is connected with the processor through the first bus interface and the second bus interface and used for inputting data of the second data selector; the second data selector is also connected with the second memory bank through a fourth bus interface and used for outputting data of the second data selector.
The switching logic circuit may also have a data selector. Specifically, the switching logic circuit is specifically provided with a third data selector. The third data selector is connected with the register, wherein the register is configured by the processor and used for data input of the third data selector; the third data selector is also connected with the first data selector and the second data selector respectively and used for switching the data output of the first data selector and the data output of the second data selector. The control signal in embodiment 1 may be an output of the switching logic circuit, i.e., an output of the third data selector.
In an exemplary embodiment of the present disclosure, as shown in fig. 4, the first data selector 203, the second data selector 204, and the third data selector 205 are all one-out-of-two data selectors (muxes).
The low level identification (0) terminal at the input terminal of the first data selector 203 is connected to a first Slave interface Slave1 in the bus via a first bus interface 201(FlashA input interface); the high-level mark (1) end in the input end of the first data selector 203 is connected with a second Slave device interface Slave2 in the bus through a second bus interface 202(FlashB input interface); the output end of the first data selector 203 is connected to the first memory controller (Flash ctrl a) in the first memory bank via a third bus interface 206(Flash a output interface).
The high-level identification (1) terminal in the input terminal of the second data selector 204 is connected to the first Slave interface Slave1 via the first bus interface 201; the low-level identification (0) terminal in the input terminal of the second data selector 204 is connected to the second Slave interface Slave2 through the second bus interface 202; the output of the second data selector 204 is connected to a second memory controller (Flash ctrl B) in the second memory bank via a fourth bus interface 207.
The low level flag (0) terminal in the input terminal of the third data selector 205 is set to a low level (0) signal; the high-level identification (1) terminal in the input terminal of the third data selector 205 is connected to a register (not shown in fig. 4) that is configured by the processor, and in some cases may be a register in a designated processor; the register may provide a switching signal (flash _ swing) to a high identification terminal in the input terminal of the third data selector 205, and the switching signal may be set to a low signal or a high (1) signal; the output terminal of the third data selector 205 is connected to the selection terminal of the first data selector 203 and simultaneously connected to the selection terminal of the second data selector 204; the select terminal of the third data selector 205 may receive a Bus idle signal (Bus idle, which may be provided by a Bus-specific signal), and the Bus idle signal may be set to a low signal or a high signal to indicate that the current Bus is idle.
In the first mode of operation, the processor may assert the switch signal to a low signal regardless of whether the bus idle status signal currently indicates that the bus is idle. At this time, the input data of the first bus interface 201 is directed to the first memory bank through the first data selector 203 and the third bus interface 206, that is, each instruction operation directed to the Flash memory address in the first memory bank on the bus can be selected to be directed to the Flash memory address in the first memory bank. Meanwhile, the input data of the second bus interface 202 is directed to the second memory bank through the second data selector 204 and the fourth bus interface 207, that is, each instruction operation directed to the Flash memory address in the second memory bank can also be selected to be directed to the Flash memory address in the second memory bank. The operation mode can be applied to a program which normally operates in each bank.
In the second operation mode, when the selection end of the third data selector 205 receives the bus idle state signal, the output end of the third data selector 205 may correspond to the high level flag end of the third data selector 205, and if the processor determines that the upgrade procedure in the second memory bank is completed, the processor may provide a corresponding switch signal to indicate that the bus is idle, and the upgrade procedure is completed, and may perform the bank switch, so that the output end of the first data selector 203 may be switched and the output end of the second data selector 204 may be switched at the same time. At this time, the input data of the first bus interface 201 is directed to the second memory bank through the second data selector 204 and the fourth bus interface 207, that is, each instruction operation directed to the storage address of Flash in the first memory bank on the bus can be selected as the same storage address directed to Flash in the second memory bank. Meanwhile, the input data of the second bus interface 202 is directed to the first memory bank through the first data selector 203 and the third bus interface 206, that is, each instruction operation directed to the Flash memory address in the second memory bank can also be selected to be directed to the Flash memory address in the first memory bank. The working mode can be suitable for the program needing to be operated and maintained, and the specific operation of the operation and maintenance can be upgrading, changing the program configuration and the like. It should be added that, the aforementioned bus interfaces may be integrated into the memory bank control device, or may not be integrated, and are configured separately to adapt to a specific chip design.
Example 4
The embodiment of the present invention and embodiments 1 to 3 all belong to the same inventive concept, and the embodiment of the present invention provides a program upgrading method, which can be executed by using the memory bank control device of embodiment 3, and the program upgrading method may include:
receiving an upgrade request of a program, wherein the program is configured in a first memory bank and a second memory bank;
by using the aforementioned bank control method, the method for executing the upgrade operation corresponding to the upgrade request on the program includes:
selecting a read instruction operation directed to the program to execute in the first memory bank and selecting a write instruction operation corresponding to the upgrade request to execute in the second memory bank, an
And after the write-in instruction operation is completed, switching the read instruction operation pointing to the program to the second memory bank for execution.
The embodiment of the invention also provides equipment with a program upgrading function, and the equipment can comprise:
a first memory bank configured to store a boot program and an application program;
a second memory bank configured to store the boot program and the application program copied from the first memory bank;
a memory bank control device, which may be the memory bank control device in embodiment 3, configured to select a read instruction operation directed to the application program to be executed in the first memory bank, and select a write instruction operation corresponding to an upgrade request to be executed in the second memory bank, where the upgrade request is an upgrade request for a processor to receive the application program;
the memory bank control device is further configured to switch a read instruction operation directed to the application program to the second memory bank for execution after the write instruction operation is completed.
In some implementations, as shown in fig. 5, the first storage is a first Flash storage Flash bank a, and the second storage is a second Flash storage Flash bank B. The first Flash memory bank a includes a first memory controller Flashctrl a and a 512KB first Flash memory (Flash _ a IP core, which may be denoted as Flash a for simplicity). The second Flash bank B includes a second memory controller flashctrl B and a 512KB second Flash memory (Flash _ B IP core, which may be denoted as FlashB for simplicity). The two memory controllers respectively control the corresponding flash memories to read and write so as to execute read instruction operation, erase instruction operation, write instruction operation and the like.
The two memory controllers are also connected via a bank control device (flash bank switch, FBS, or also referred to as flash bank switch) to two slave interfaces (#0 and #1) of a BUs MATRIX (AHB _ BU-S _ MATRIX, which may include the master interface and the slave interface mentioned in embodiment 1, etc.) of the AHB BUs.
As in fig. 6 and 7, to focus on the access operation procedure on the memory, the memory bank control device FBS and the two memory controllers can be abstracted as a straight line representation. Boot programs (Boot programs) on the first Flash memory Flash A and the second Flash memory Flash B are chip Boot programs, data contents on an area E, an area F, an area G, an area E ', an area F' and an area G 'on the first Flash memory Flash A are all application programs, data contents on an area E', an area F 'and an area G' on the second Flash memory Flash B are backups respectively corresponding to the data contents on the area E, the area F and the area G, the data contents on the area E, the area F and the area G can be one application program or three different application programs, and the like, and the number relation between the data contents on each area on the second Flash memory Flash B and the number relation between the application programs is also similar.
In fig. 6, the bank control device FBS can be in a first operating mode. When an application program in the first Flash memory Flash a is executed by the processor, a first access operation 301 is initiated, where the first access operation 301 may be performed with respect to an address segment of the application program in the first Flash memory Flash a, for example, read instruction operations 302 and 303, the bank control device FBS may direct a read instruction operation pointing to an address of the application program to a region E in the first Flash memory Flash a of the first memory bank, for example, memory addresses address1 and address2, and a completion time of the first access operation 301 may be from time t1 to time t2 (a first continuous time interval).
An application program in the area E of the first flash memory FlashA needs to be upgraded, and the second flash memory FlashB can be erased and written. The second access operation 304 may be initiated based on the upgrade request after the operation and maintenance program is executed by the processor, the second access operation 304 may be performed on the address field of the application program in the second Flash memory FlashB, for example, the write instruction operations 305 and 306 after the erase instruction operation is performed, the bank control device FBS may direct the write instruction operation pointing to the address of the application program to the area E' in the second Flash memory Flash B of the second memory bank, at this time, the addresses of the memory in the memory bank may be consistent except for the bank number, at this time, the addresses of the memory may also be the address1 and the address2, the completion time of the second access operation 304 may be from the time t1 to the time t3 (second continuous time interval), and the first continuous time interval and the second continuous time interval may overlap, so that the program upgrade will not intervene in the normal use of the original program.
After the second access operation 304 is completed, the processor may configure a register (which may be performed by execution of the operation and maintenance program) connected to the bank control device FBS, so as to provide a flash _ shock signal, and perform a bank read/write switch when the bus is idle. At this time, the bank control device FBS can be switched to the second operating mode.
In fig. 7, the upgraded application is in area E', and when executed by the processor, a third access operation 307 may be initiated, the third access operation 307 being directed to the native application in region E of the first flash memory FlashA, such as read instruction operations 308 and 309, however, because the memory bank control device FBS in the second operating mode switches the pointing addresses of the read command operations 308 and 309 to the addresses of the upgraded application programs in the area E' in the second Flash memory Flash B of the second memory bank, the command operations actually executed at this time are the read command operations 310 and 311, the memory addresses may still be address1 and address2, the time for completing the third access operation 307 may be from the time t4 to the time t5, there is no use interruption due to program upgrade, the program may be upgraded without any sense, and the user may use the upgraded program seamlessly. After this, the copy operation and the switching again (or soft reset) of the bank control apparatus FBS, etc. can be continued to realize the bank master-slave backup use.
Example 5
The embodiment of the invention and the embodiments 1 to 4 all belong to the same inventive concept, and the embodiment of the invention provides electronic equipment and a computer-readable storage medium.
Electronic devices are intended to represent various forms of devices that have instruction processing capabilities and computing capabilities. The memory stores instructions executable by at least one processor, and the at least one processor implements the aforementioned bank control method in embodiment 1 and the program upgrade method in embodiment 4 by executing the instructions stored in the memory.
The computer-readable storage medium may be configured with a computer program that implements the memory bank control method in embodiment 1 and the program upgrade method in embodiment 4 described above when executed by a processor.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
Those skilled in the art will understand that all or part of the steps in the method according to the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. The electronic device may include an instruction processing device in the form of various integrated circuits (e.g., a microcontroller MCU, micro-controller unit; system on a Chip, SoC) of elements such as an integrated circuit and a transistor, and the storage medium may include: various media that can store program code, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, may be non-transitory.
In addition, any combination of various different implementation manners of the embodiments of the present invention is also possible, and the embodiments of the present invention should be considered as disclosed in the embodiments of the present invention as long as the combination does not depart from the spirit of the embodiments of the present invention.

Claims (26)

1. A bank control method, comprising:
selecting a read instruction operation pointing to a program to be executed in a first memory bank having the program;
selecting a write instruction operation pointing to the program to be executed in a second memory bank in which the program exists;
and after the write-in instruction operation is completed, switching the read-out instruction operation to the second memory bank for execution.
2. The bank control method according to claim 1, wherein the bank control method is performed by a logic device.
3. The memory bank control method according to claim 2, wherein the logic device includes a data selector.
4. The bank control method according to claim 2, wherein the logic device is in a first operation mode or a second operation mode;
the logic device in the second operating mode selects read command operations and/or write command operations directed to a program in the first memory bank to be executed in the second memory bank, wherein,
the read command operation and/or the write command operation are selected by the logic device in the first operation mode to be executed in the first memory bank.
5. The bank control method according to claim 4, wherein in the bank control method,
the logic device in the second operating mode selects read command operations and/or write command operations directed to programs in the second memory bank to be executed in the first memory bank, wherein,
the read command operation and/or the write command operation are selected by the logic device in the first operating mode to be executed in the second memory bank.
6. The bank control method according to claim 4 or 5, wherein in the bank control method,
the logic device in said first mode of operation is switched by a control signal to the logic device in said second mode of operation,
the control signals are determined by the processor and the bus in the idle state.
7. The memory bank control method according to claim 1, wherein the selecting of the write instruction operation directed to the program is performed in a second memory bank in which the program is present, wherein,
the program in the second memory bank is the copied program in the first memory bank.
8. The memory bank control method according to claim 7, wherein the selecting of the write instruction operation directed to the program is performed in a second memory bank in which the program is present, wherein,
the memory address of the program in the second memory bank is identical to the memory address in the first memory bank.
9. The bank control method according to claim 1, wherein, during execution of the write command operation,
the read instruction operation is executed simultaneously, or
Has finished executing the read instruction operation, or
Waiting for the read instruction operation to be performed.
10. The bank control method according to claim 1, wherein before the write command operation is executed, the bank control method further comprises:
selecting an erase instruction operation directed to the program is performed in a second memory bank having the program, wherein the second memory bank has a flash memory medium.
11. The memory bank control method according to claim 1, wherein before the switching the read instruction operation to the second memory bank is performed, the memory bank control method further comprises:
determining that a bus is in an idle state, wherein the bus is connected with the first memory bank and also connected with the second memory bank.
12. The bank control method according to claim 1, further comprising:
and copying the program in the second memory bank to the first memory bank.
13. The bank control method according to claim 12, further comprising:
a soft reset is performed, or alternatively,
determining that a bus is in an idle state, wherein the bus is connected with the first memory bank and also connected with the second memory bank.
14. A bank control system, comprising:
the first selection module is used for selecting a reading instruction operation pointing to a program to be executed in a first memory bank with the program;
the second selection module is used for selecting the write instruction operation pointing to the program to be executed in a second memory bank with the program;
and the switching module is used for switching the reading instruction operation to the second memory bank for execution after the writing instruction operation is completed.
15. A bank control apparatus, characterized by comprising:
the selection logic circuit is connected with the processor, is respectively connected with the first memory bank and the second memory bank, and is used for selecting the reading instruction operation of the processor pointing to the program to be executed in the first memory bank with the program;
the selection logic circuit is also used for selecting the processor to execute a write instruction operation pointing to the program in a second memory bank with the program;
and the switching logic circuit is connected with the processor and the selection logic circuit and is used for switching the reading instruction operation to the second memory bank for execution after the writing instruction operation is completed.
16. The memory bank control apparatus according to claim 15,
the selection logic circuit has a data selector.
17. The memory bank control apparatus according to claim 16,
the selection logic circuit comprises a first data selector;
the first data selector is connected with the processor through a first bus interface and a second bus interface and used for inputting data of the first data selector;
the first data selector is also connected with the first memory bank through a third bus interface and used for outputting data of the first data selector.
18. The memory bank control apparatus according to claim 17,
the selection logic circuit further comprises a second data selector;
the second data selector is connected with the processor through the first bus interface and the second bus interface and used for inputting data of the second data selector;
the second data selector is also connected with the second memory bank through a fourth bus interface and used for outputting data of the second data selector.
19. The memory bank control apparatus according to claim 18,
the switching logic circuit has a third data selector;
the third data selector is connected to a register, wherein the register is configured by the processor for data input of the third data selector;
the third data selector is further connected to the first data selector and the second data selector respectively, and is configured to switch between data output of the first data selector and data output of the second data selector.
20. The bank control apparatus according to any one of claims 15 to 19,
the first memory bank includes a first memory controller and a first flash memory connected to the first memory controller,
the second memory bank comprises a second memory controller and a second flash memory connected with the second memory controller;
the selection logic circuit is respectively connected with the first storage controller and the second storage controller.
21. The memory bank control apparatus according to claim 20,
the storage capacity of the first flash memory is identical to that of the second flash memory.
22. The memory bank control apparatus according to claim 20,
the first flash memory is used as a main memory, and the second flash memory is used as a slave memory;
the storage capacity of the second flash memory is larger than that of the first flash memory.
23. A program upgrading method, characterized in that the program upgrading method comprises:
receiving an upgrade request of a program, wherein the program is configured in a first memory bank and a second memory bank;
performing, with the bank control method according to any one of claims 1 to 13, an upgrade operation corresponding to the upgrade request on the program, including:
selecting a read instruction operation directed to the program to execute in the first memory bank and selecting a write instruction operation corresponding to the upgrade request to execute in the second memory bank, an
And after the write-in instruction operation is completed, switching the read instruction operation pointing to the program to the second memory bank for execution.
24. An apparatus having a program upgrade function, comprising:
a first memory bank configured to store a boot program and an application program;
a second memory bank configured to store the boot program and the application program copied from the first memory bank;
a memory bank control device according to any one of claims 15 to 22, configured to select a read instruction operation directed to the application program to be executed in the first memory bank, and select a write instruction operation corresponding to an upgrade request to be executed in the second memory bank, wherein the upgrade request is an upgrade request of the application program received by a processor;
the memory bank control device is further configured to switch a read instruction operation directed to the application program to the second memory bank for execution after the write instruction operation is completed.
25. An electronic device, comprising:
at least one processor;
a memory coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, and the at least one processor implements the bank control method of any one of claims 1 to 13 or the program upgrade method of claim 23 by executing the instructions stored by the memory.
26. A computer-readable storage medium storing computer instructions which, when executed on a computer, cause the computer to perform the bank control method of any one of claims 1 to 13 or the program upgrade method of claim 23.
CN202110734704.1A 2021-06-30 2021-06-30 Memory bank control method, program upgrading method and device Pending CN113590150A (en)

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CN105760200A (en) * 2016-02-26 2016-07-13 晨星半导体股份有限公司 Terminal device and system updating method thereof
CN109390020A (en) * 2017-08-02 2019-02-26 瑞萨电子株式会社 Semiconductor memory system and its control method

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CN1318172A (en) * 1999-04-14 2001-10-17 密克罗奇普技术公司 Method and system for updating user memory in emulator systems
CN101872306A (en) * 2009-04-21 2010-10-27 京信通信系统（中国）有限公司 Embedded system for realizing software updating and software backup and implementation method thereof
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