CN113574806A

CN113574806A - Polarization encoding

Info

Publication number: CN113574806A
Application number: CN201980094041.2A
Authority: CN
Inventors: 陈宇; 陈捷; 朱凯; K·S·J·拉杜
Original assignee: Nokia Shanghai Bell Co Ltd; Nokia Solutions and Networks Oy
Current assignee: Nokia Shanghai Bell Co Ltd; Nokia Solutions and Networks Oy
Priority date: 2019-01-14
Filing date: 2019-01-14
Publication date: 2021-10-29
Also published as: WO2020146992A1

Abstract

Embodiments of the present disclosure provide a method, apparatus, and computer-readable medium for performing polarization encoding. In an example embodiment, the method includes generating an initial sequence including a plurality of information bits and a plurality of check bits in an initial order. At least one of the plurality of parity bits is a duplicate of one of the plurality of information bits. The method further includes generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in the following manner: such that at least one of the plurality of parity bits and one of the information bits will be processed differently during polarization encoding of the interleaved sequence. The method also includes encoding the interleaved sequence using a polar code. The method also includes transmitting the encoded sequence to a receiving device.

Description

Polarization encoding

Technical Field

Embodiments of the present disclosure relate generally to wireless communications and, in particular, to a method, apparatus, and computer-readable medium for performing polarization encoding.

Background

Polar codes are used as New Radio (NR) enhanced mobile broadband (eMBB) control channel coding solutions. Research shows that the polarization code has the advantages of low complexity, low delay and no error code layer effect. Therefore, it can also be used for ultra-reliable low-latency communication (URLLC) and large-scale machine type communication (mtc).

In the information theory, a polar code is a linear block error correction code. The code construction is based on multiple recursive concatenations of short kernel code that convert physical channels into virtual outer channels. As the number of recursions becomes large, the virtual channels tend to have either high reliability or low reliability (in other words, they are polarized), and the data bits are assigned to the most reliable channels.

Disclosure of Invention

In general, example embodiments of the present disclosure provide a method, apparatus, and computer-readable medium for performing polarization encoding.

In a first aspect, a method for communication is provided. The method includes generating an initial sequence including a plurality of information bits and a plurality of check bits in an initial order. At least one of the plurality of parity bits is a repetition of one of the information bits. The method also includes generating an interleaved sequence by changing the initial order such that the at least one of the plurality of parity bits and the one of the information bits will be processed differently during polarization encoding of the interleaved sequence of the plurality of information bits and the plurality of parity bits. The method also includes encoding the interleaved sequence using a polar code. The method also includes transmitting the encoded sequence to a receiving device.

In a second aspect, a method for communication is provided. The method comprises the following steps: generating an initial sequence including a plurality of information bits and a plurality of check bits in an initial order; inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to the receiving device; generating an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing an initial order such that the at least one dummy bit is disposed before the plurality of information bits and the plurality of parity bits; encoding the interleaved sequence using a polar code; and transmitting the encoded sequence to a receiving device.

In a third aspect, a method for communication is provided. The method comprises the following steps: generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits having a predefined value; generating an interleaved sequence of a plurality of information bits and a plurality of check bits by changing an initial order; encoding the interleaved sequence using a polar code; and transmitting the encoded sequence to a receiving device.

In a fourth aspect, an electronic device is provided. The electronic device includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code configured to, with the at least one processor, cause the electronic device to: generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits being a repetition of one of the information bits; generating an interleaved sequence by changing an initial order such that the at least one of the plurality of parity bits and the one of the information bits will be processed differently during polarization encoding of the interleaved sequence of the plurality of information bits and the plurality of parity bits; encoding the interleaved sequence using a polar code; and transmitting the encoded sequence to a receiving device.

In a fifth aspect, an electronic device is provided. The electronic device includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code configured to, with the at least one processor, cause the electronic device to: generating an initial sequence including a plurality of information bits and a plurality of check bits in an initial order; inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to the receiving device; generating an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing an initial order such that the at least one dummy bit is disposed before the plurality of information bits and the plurality of parity bits; encoding the interleaved sequence using a polar code; and transmitting the encoded sequence to a receiving device.

In a sixth aspect, an electronic device is provided. The electronic device includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code configured to, with the at least one processor, cause the electronic device to: generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits having a predefined value; generating an interleaved sequence of a plurality of information bits and a plurality of check bits by changing an initial order; encoding the interleaved sequence using a polar code; and transmitting the encoded sequence to a receiving device.

In a seventh aspect, a computer-readable medium having instructions stored thereon is provided. The instructions, when executed on at least one processor of a device, cause the device to perform the method according to the first aspect.

In an eighth aspect, a computer-readable medium having instructions stored thereon is provided. The instructions, when executed on at least one processor of a device, cause the device to perform a method according to the second aspect.

In a ninth aspect, a computer-readable medium having instructions stored thereon is provided. The instructions, when executed on at least one processor of a device, cause the device to perform the method according to the third aspect.

It should be understood that the summary is not intended to identify key or essential features of embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become readily apparent from the following description.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following more detailed description of some embodiments of the present disclosure, as illustrated in the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a communication environment in which embodiments of the present disclosure may be implemented;

fig. 2 illustrates a flow diagram of an example method according to some embodiments of the present disclosure;

fig. 3 is a schematic diagram illustrating an example of an interleaving sequence in accordance with some embodiments of the present disclosure;

fig. 4 shows a flow diagram of an example method according to some other embodiments of the present disclosure;

fig. 5 is a schematic diagram illustrating an example of an interleaving sequence according to some other embodiments of the present disclosure;

fig. 6A is a schematic diagram illustrating an example mapping of interleaving sequences to subchannels in accordance with some other embodiments of the present disclosure;

fig. 6B is a diagram illustrating an example mapping of interleaving sequences to subchannels in accordance with other embodiments of the present disclosure;

FIG. 7 shows a flowchart of an example method according to other embodiments of the present disclosure;

FIG. 8 shows a flow diagram of an example method according to other embodiments of the present disclosure;

fig. 9 is a diagram illustrating an example mapping of interleaving sequences to subchannels in accordance with other embodiments of the present disclosure;

fig. 10 shows a flowchart of an example method according to some other embodiments of the present disclosure;

FIG. 11 is a schematic diagram of an example polar decoding architecture;

FIG. 12 is a graph illustrating simulation results of performance evaluations according to some embodiments of the present disclosure; and

FIG. 13 is a simplified block diagram of a device suitable for implementing embodiments of the present disclosure.

Throughout the drawings, the same or similar reference numbers refer to the same or similar elements.

Detailed Description

The principles of the present disclosure will now be described with reference to a few exemplary embodiments. It is understood that these embodiments are described for illustrative purposes only and are presented to aid those skilled in the art in understanding and enabling the disclosure, without placing any limitation on the scope of the disclosure. The disclosure described herein may be implemented in a variety of other ways besides those described below.

In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

As used herein, the term "network device" or "base station" (BS) refers to a device that is capable of providing or hosting a cell or coverage area in which a terminal device may communicate. Examples of network devices include, but are not limited to, a node B (NodeB or NB), an evolved NodeB (eNodeB or eNB), a next generation NodeB (gnb), a Remote Radio Unit (RRU), a Radio Head (RH), a Remote Radio Head (RRH), a low power node (such as a femto node, pico node, etc.). For discussion purposes, some embodiments will be described below with reference to an eNB or a gNB as an example of a network device.

As used herein, the term "terminal device" refers to any device having wireless or wired communication capabilities. Examples of terminal devices include, but are not limited to, User Equipment (UE), personal computers, desktop computers, mobile phones, cellular phones, smart phones, Personal Digital Assistants (PDAs), portable computers, image capture devices such as digital cameras, gaming devices, music storage and playback devices, or internet appliances that support wireless or wired internet access and browsing, among others. For discussion purposes, some embodiments will be described below with reference to a UE as an example of a terminal device, and the terms "terminal device" and "user equipment" (UE) may be used interchangeably in the context of this disclosure.

The term "circuitry" as used herein may refer to one or more or all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and/or digital circuitry only); and (b) a combination of hardware circuitry and software, such as (as applicable): (i) a combination of analog and/or digital hardware circuit(s) and software/firmware, and (ii) hardware processor(s) with software (including digital signal processor (s)), any portion of software and memory(s) that work in conjunction to cause a device such as a mobile telephone or server to perform various functions; and (c) hardware circuit(s) and/or processor(s), such as microprocessor(s) or a portion of microprocessor(s), that require software (e.g., firmware) to operate (but may not be present when operation is not required).

This definition of "circuitry" applies to all uses of the term in this application, including in any claims. As another example, as used in this application, the term "circuitry" also encompasses an implementation of purely hardware circuitry or processor (or multiple processors) or a portion of a hardware circuitry or processor and its (or their) accompanying software and/or firmware. The term "circuitry" also encompasses (e.g., and if applicable to a particular claim element) a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in a server, a cellular network device, or other computing or network device.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "comprising" and its variants are to be understood as open-ended terms, meaning "including but not limited to". The term "based on" should be understood as "based at least in part on". The terms "one embodiment" and "an embodiment" should be understood as "at least one embodiment". The term "another embodiment" should be understood as "at least one other embodiment". The terms "first", "second", etc. may refer to different or identical objects. Other definitions (explicit and implicit) may be included below.

In some examples, a value, process, or device is referred to as "best," "lowest," "highest," "minimum," "maximum," or the like. It should be understood that such description is intended to suggest that a selection may be made among many functional alternatives used, and that such a selection need not be better, smaller, higher, or otherwise preferable than other selections.

Fig. 1 is a schematic diagram of a communication environment 100 in which embodiments of the present disclosure may be implemented. The communication environment 100 may include a network device 110, the network device 110 providing wireless connectivity to a plurality of

terminal devices

120, 130 within its coverage area.

Terminal devices

120 and 130 may communicate with network device 110 via

wireless transmission channels

115 or 125 and/or with each other via transmission channel 135.

It is to be understood that the number of network devices and the number of terminal devices shown in fig. 1 are for illustrative purposes only and do not represent any limitation. Communication environment 100 may include any suitable number of network devices and terminal devices suitable for implementing embodiments of the present disclosure. Further, it should be understood that various wireless communications as well as wired communications (if desired) may exist between these network devices and the terminal device.

Communications in communication environment 100 may conform to any suitable standard including, but not limited to, global system for mobile communications (GSM), extended coverage global system for mobile internet of things (EC-GSM-IoT), Long Term Evolution (LTE), LTE evolution, LTE advanced (LTE-a), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (CDMA), GSM EDGE Radio Access Network (GERAN), and so forth.

Further, communications in the communication environment 100 may be performed in accordance with any generation of communication protocols now known or to be developed in the future. Examples of communication protocols include, but are not limited to, first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, and fifth generation (5G) communication protocols.

As an illustrative example, the various example implementations or techniques described herein may be applied to various terminal devices, such as Machine Type Communication (MTC) terminal devices, enhanced machine type communication (eMTC) terminal devices, internet of things (IoT) terminal devices, and/or narrowband IoT terminal devices.

In an example implementation, the terminal device or UE may be a UE/terminal device with a URLLC application. A cell (or cells) may include a plurality of terminal devices connected to the cell, including different types or classes of terminal devices, e.g., classes including MTC, NB-IoT, URLLC, or other UE classes.

Various example implementations may be applied to multiple wireless technologies or wireless networks, such as LTE, LTE-a, 5G, cmWave, and/or mmWave band networks, IoT, MTC, eMTC, URLLC, etc., or any other wireless network or wireless technology. These example networks or technologies are provided as illustrative examples only, and various example implementations may be applied to any wireless technology/wireless network.

As mentioned above, a polar code may be used as a control channel coding scheme for URLLC. The false alarm rate of error detection is critical for downlink control channels that require blind decoding. Compared to LTE, URLLC requires a lower false alarm rate for error detection, such as 1 e-5. Two conventional solutions for reducing the false alarm rate are proposed.

In one of the two conventional solutions, it is different to employ more Cyclic Redundancy Checks (CRCs), which means that a larger CRC polynomial should be used. Because current CRC attachment is optimized for early termination by using an interleaver after CRC generation, a larger CRC polynomial should be carefully designed to have backward compatibility.

In another conventional solution, unused bits in a Downlink Control Information (DCI) message are employed for checking. However, this solution has two problems: even without repetition, the false alarm rate cannot meet the requirement, and the current 8 DCI formats do not all contain unused bits.

To address at least in part the above and other potential problems, embodiments of the present disclosure provide solutions for polarization encoding. According to an embodiment of the present disclosure, at least one new parity bit is introduced and is a copy of one of the plurality of information bits. At least one new parity bit is inserted into the plurality of information bits such that the at least one new parity bit and the one of the information bits will be processed differently during polarization encoding. With the embodiments of the present disclosure, since the at least one new parity bit and the information bit of the information bits are to be processed differently during polarization encoding, the probability of an error occurring in the at least one new parity bit and one of the plurality of information bits may be reduced. Therefore, the inspection effectiveness can be improved. Some embodiments according to the present disclosure will be described in detail below in conjunction with fig. 2-12.

Fig. 2 illustrates a flow diagram of an example method 200 in accordance with some embodiments of the present disclosure. In the context of the present disclosure, for ease of discussion and without loss of generality, the network device 110 in the communication environment 100 may be described as a transmitting device and the terminal device 120 in the communication environment 100 may be described as a receiving device. It should be understood that in some other communication scenarios, terminal device 120 may be a transmitting device and network device 110 may be a receiving device.

In general, the transmitting device 110 may transmit information to the receiving device 120 for communication. For example, the transmitted information may be data information, control information, and the like. Prior to transmission, transmitting device 110 may encode (such as channel encode) the information using a polar code to improve the quality of the transmission. Accordingly, the reception apparatus 120 may receive the encoded information and acquire the information by decoding the encoded information using the polarization code.

At block 210, the transmitting device 110 generates an initial sequence, for example, based on control information to be transmitted to the receiving device 120. The initial sequence includes a plurality of information bits and a plurality of check bits in an initial order. At least one of the plurality of parity bits is a duplicate of one of the information bits. For example, each of the at least one parity bit may be a copy of the information bit adjacent to the parity bit. In the context of the present disclosure, a parity bit that is a copy of an information bit is also referred to as a new parity bit, and other parity bits of the plurality of parity bits are also referred to as existing parity bits.

In some embodiments, the at least one new check bit is a difference in a Downlink Control Information (DCI) message. In some embodiments, the existing check bits may be any type of error detection code, such as CRC bits. For ease of discussion and without loss of generality, the existing check bits will be illustrated with the CRC bits as an example. It should be appreciated that if other error detection schemes are employed by the transmitting device 110 and the receiving device 120, the existing parity bits may be other types of error detection codes.

In some embodiments, the number of at least one new parity bit may be determined based on an expected false positive rate and the number of existing parity bits. For example, when the expected false alarm rate is 2^-27And the number of the existing check bits is 2^-24The number of at least one new parity bit may be determined to be 3.

At block 220, the transmitting device 110 generates an interleaved sequence of a plurality of information bits and a plurality of parity bits by changing the initial order. The change to the initial order is performed such that: the at least one new parity bit and one of the plurality of information bits are to be processed differently during polarization encoding of the interleaved sequence. In the context of the present disclosure, an interleaved sequence to be encoded using a polar code may also be referred to as an information block or block.

In some embodiments, during polar encoding of the interleaved sequence, transmitting device 110 may perform an exclusive-or output of at least one new parity bit and perform an original output of one of the information bits. Alternatively, during polar encoding of the interleaved sequence, transmitting device 110 may perform an exclusive-or output of one of the information bits and perform the original output of at least one new check bit. It should be understood that performing exclusive or output and performing raw output are merely examples of different ways of processing and do not set any limit on the scope of the present disclosure. Since one of the at least one new parity bit and the information bit will be processed differently during polarization encoding, the probability of an error occurring in the information bit of the at least one new parity bit and the information bit may be reduced. Therefore, the inspection effectiveness can be improved.

In general, after changing the initial order of the initial sequence, the plurality of check bits may not be uniformly distributed in the interleaved sequence, for example, as shown in fig. 3.

Fig. 3 is a schematic diagram illustrating an example of an interleaving sequence 300 according to some embodiments of the present disclosure. As shown, the interleaving sequence 300 includes information bits 311 and check bits 312. The first, second, and third

information bit sequences

314, 315, and 316 may be referred to as a first distributed crc (DCRC) portion, a second (DCRC) portion, and a third (DCRC) portion, respectively, as defined in 3GPP TS 38.211. As can be seen in fig. 3, the check bits 312 are not evenly distributed in the interleaved sequence 300, which may reduce the effectiveness of the check.

To improve the validity of the check, in some embodiments of the present disclosure, the transmitting device 110 changes the initial order of the initial sequence to evenly distribute the plurality of check bits to generate the interleaved sequence. In other words, the plurality of check bits are uniformly distributed in the interleaved sequence. This means that for any two portions in the interleaved sequence, the difference between the ratio of parity bits to information bits in one of the two portions and the ratio of parity bits to information bits in the other of the two portions is below a threshold difference. One such embodiment will be described below with reference to fig. 4.

Fig. 4 illustrates a flow diagram of an example method 400 of generating an interleaving sequence, in accordance with some other embodiments of the present disclosure. The method 400 may be implemented at the transmitting device 110 as shown in fig. 1. For purposes of discussion, the method 400 will be described with reference to fig. 1 and 3 from the perspective of the transmitting device 110. For example, method 400 may be an example implementation of block 220 as shown in FIG. 2. It should be understood that method 400 may include additional blocks not shown and/or may omit some blocks shown, and that the scope of the present disclosure is not limited in this respect.

At block 410, the transmitting device 110 sets the index x of the DCRC portion to 1. At block 415, the transmitting device 110 evenly distributes N check bits in the first DCRC section 314, where N represents the number of new check bits as described above.

At block 420, the transmitting device 110 calculates a first average number of information bits between two check bits in the DCRC portion x and a second average number of information bits between two check bits in the DCRC portion x + 1.

At block 425, the sending device 110 determines whether the first average number of information bits in the DCRC portion x is less than the second average number of information bits in the DCRC portion x + 1. If it is determined that the first average number is not less than the second average number, the transmitting device 110 increments the index x by 1 at block 430.

In block 435, the transmitting device 110 determines whether the value of index x is less than or equal to the total number of DCRC portions. For example, in the example shown in FIG. 3, the total number of DCRC portions is equal to three. If the value of index x is equal to 1, the transmitting device 110 may determine that the value of index x is less than the total number of DCRC portions.

If it is determined at block 435 that the value of index x is less than or equal to the total number of DCRC portions, then the transmitting device 110 determines at block 440 whether there are any check bits that need to be moved to the next DCRC portion.

If it is determined at block 440 that no check bits need to be moved to the next DCRC section, then transmitting device 110 arranges the check bits and information bits that will be processed differently during polar encoding on the f-node and g-node, respectively. To arrange the parity bits and the information bits on the f-node and the g-node, respectively, if both the parity bits and the information bits are arranged on the f-node or the g-node, the transmitting device 110 may shift one of the parity bits and the information bits to the left or right by at most one bit.

On the other hand, if it is determined at block 425 that the first average number is not less than the second average number, the transmitting device 110 moves one check bit in the DCRC section x to the DCRC section x +1 and uniformly distributes the check bit in the DCRC section x at block 450. The method 400 then returns to block 420.

Further, if it is determined at block 435 that the value of index x is greater than the total number of DCRC portions, the transmitting device 110 increments the index x by 1 at block 455. The method 400 then returns to block 420.

Further, if it is determined at block 440 that no check bits need to be moved to the next DCRC portion, the transmitting device 110 sets the index x of the DCRC portion to 1 at block 460. The method 400 then returns to block 420.

With the method 400, a plurality of parity bits are uniformly distributed in an interleaved sequence, e.g., as shown in fig. 5. Fig. 5 is a schematic diagram illustrating an example of an interleaving sequence 500 according to some other embodiments of the present disclosure. In the example shown in fig. 5, the existing parity bits 511 and the new parity bits 512 are uniformly distributed in the interleaving sequence 500, thereby improving the validity of the parity, compared to the example shown in fig. 3. It should be noted that the check bit sequence 313 is not moved because the sub-channel to which the check bits 313 are to be mapped has higher reliability.

Referring again to fig. 2, at block 230, transmitting device 110 encodes the interleaved sequence using a polar code. During polar encoding, various encoding algorithms may be used, including existing polar encoding algorithms as well as other polar encoding algorithms that may be developed in the future.

At block 240, the transmitting device 110 transmits the encoded sequence to the receiving device 120.

In general, polarization encoding has the following characteristics: at a particular breakpoint, the index of the first subchannel to which the information bits or parity bits are mapped will change to half of it. For example, for a specific size information block, if the index of the first subchannel is 256, the index of the first subchannel becomes 128 even if only one additional bit is added to the information block. Typically, the receiving device 120 will start decoding from the first subchannel. If the index of the first subchannel is greatly reduced, the decoding delay may be significantly increased, as will be described in connection with fig. 6A and 6B.

Fig. 6A is a schematic diagram illustrating an example mapping of interleaving sequences to subchannels of channel 600, and fig. 6B is a schematic diagram illustrating an example mapping of interleaving sequences to subchannels of channel 605, according to some other embodiments of the present disclosure.

As shown in fig. 6A, channel 600 includes sub-channel 611 and sub-channel 612. Existing parity bits or information bits in the information block are mapped onto the sub-channel 611 for polarization encoding. Thus, in the context of the present disclosure, the sub-channel 611 to which existing check bits or information bits are mapped is also referred to as the occupied sub-channel 611 of the first type. No existing parity bits or information bits are mapped onto subchannel 612, but the frozen bits are mapped onto subchannel 612. Because the value of the frozen bits is known to the receiving device 120, the receiving device 120 will exclude the encoded frozen bits from decoding. Thus, in the context of the present disclosure, the subchannel 612 to which the frozen bits are mapped is also referred to as a first type of clear subchannel 612.

As shown in fig. 6A, the initially occupied sub-channel 611 of the first type is adjacent to the empty sub-channel 612 of the first type. Upon receiving the encoded information block, the receiving device 120 will start decoding from the initially occupied sub-channel 611 of the first type. Information bits or check bits are mapped onto the initially occupied sub-channels 611 of the first type.

The position of the initially occupied sub-channel can be changed if an additional bit is added to the information block. As shown in fig. 6B, the position of the initially occupied sub-channel is changed so that it is located between the first type of empty sub-channels 612. The initially occupied sub-channels located between the first type of empty sub-channels 612 may be referred to as second type of occupied sub-channels 613. Upon receiving the encoded information block, the receiving device 120 will start decoding from the occupied sub-channel 613 of the second type. In other words, the receiving device 120 will take more time to decode the encoded information block. That is, the decoding delay is significantly increased.

To reduce decoding delay, in some embodiments, transmitting device 110 may insert at least one dummy bit before the check bits and the information bits, which will be described below with reference to fig. 7.

Fig. 7 illustrates a flow diagram of an example method 700 in accordance with some embodiments of the present disclosure. For example, method 700 may be implemented at network device 110 as shown in fig. 1. It should be understood that method 700 may include additional blocks not shown and/or may omit some blocks shown, and the disclosure is not limited in this regard. In the context of the present disclosure, for ease of discussion and without loss of generality, the network device 110 in the communication environment 100 may be described as a transmitting device and the terminal device 120 in the communication environment 100 may be described as a receiving device. It should be understood that in some other communication scenarios, terminal device 120 may be a transmitting device and network device 110 may be a receiving device.

At block 710, the transmitting device 110 generates an initial sequence that includes a plurality of information bits and a plurality of check bits in an initial order.

At block 720, the transmitting device 110 inserts at least one dummy bit into the initial sequence, the value of each dummy bit being known to the receiving device.

At block 730, the transmitting device 110 generates an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing the initial order such that the at least one dummy bit is disposed before the plurality of information bits and the plurality of parity bits.

At block 740, the transmitting device 110 encodes the interleaved sequence using a polarization code.

At block 750, the transmitting device 110 transmits the encoded sequence to the receiving device 120.

In some embodiments, the at least one dummy bit is determined based on an identification of the receiving device 120.

Because the receiving device 120 knows the value of each dummy bit, the receiving device 120 will bypass at least one dummy bit and start encoding of information bits or check bits after the at least one dummy bit. In other words, the receiving device 120 may exclude decoding of at least one dummy bit. Therefore, the decoding speed is accelerated, and the decoding delay is reduced.

Fig. 8 shows a flowchart of an example method 800 of inserting at least one dummy bit according to other embodiments of the present disclosure. The method 800 may be implemented at the transmitting device 110 as shown in fig. 1. For purposes of discussion, the method 800 will be described with reference to fig. 1 from the perspective of the transmitting device 110. For example, method 800 may be one example implementation of method 700 shown in FIG. 7. It should be understood that method 800 may include additional blocks not shown and/or may omit some blocks shown, and that the scope of the present disclosure is not limited in this respect.

As shown, the transmitting device 110 generates a first additional sequence by combining the frozen bit sequence with the interleaved sequence at block 810. For example, in the example shown in fig. 6B, the first additional sequence may be a sequence including bits mapped onto the subchannels 611, 612, and 613.

At block 820, the transmitting device 110 determines the number of frozen bits in the subset of frozen bits between the start bit and the first bit in the first additional sequence. For example, in the example shown in fig. 6B, the start bit may be a bit mapped onto subchannel 613, the first bit may be a bit mapped onto subchannel 611 following subchannel 613, and the subset of frozen bits may comprise frozen bits mapped onto subchannel 612 between subchannel 613 and subchannel 611.

At block 830, the transmitting device 110 determines whether the number of frozen bits in the subset of frozen bits exceeds a threshold number. In some embodiments, the threshold number may be determined to be 2^ abs (log2(P) -1), where P represents the index of the subchannel to which the starting bit in the first additional sequence is mapped. For example, in the example shown in fig. 6B, P denotes an index of the sub-channel 613. It should be understood that 2^ abs (log2(P) -1) is only one example of a threshold number and does not set any limit on the scope of the present disclosure. The threshold number may be determined to be any suitable value depending on the particular application scenario.

If it is determined at block 830 that the number of frozen bits in the subset of frozen bits exceeds the threshold number, the transmitting device 110 marks the starting bit x as "D" (also referred to as bit "D") at block 840. On the other hand, if it is determined at block 830 that the number of frozen bits in the subset of frozen bits does not exceed the threshold number, then the transmitting device 110 may perform any suitable action at block 890.

At block 850, transmitting device 110 inserts dummy bits labeled "Y" (also referred to as bits "Y"). At block 860, the transmitting device 110 interleaves the dummy bits, check bits, and information bits.

At block 870, transmitting device 110 determines whether bit "Y" precedes bit "D". If it is determined at block 870 that bit "Y" does not precede bit "D", then transmitting device 110 exchanges the positions of bit "D" and bit "Y" at block 880. On the other hand, if it is determined at block 870 that bit "Y" precedes bit "D," then transmitting device 110 may perform any suitable action at block 890.

It should be appreciated that method 800 may be repeated if more dummy bits are to be inserted.

Fig. 9 is a diagram illustrating an example mapping of interleaving sequences to subchannels of a channel 900, according to other embodiments of the present disclosure. Comparing the example shown in fig. 9 with the example shown in fig. 6B, dummy bits are mapped onto subchannels 614 (also referred to as second type of white subchannels 614). The start parity bits or information bits as shown in fig. 6B are mapped onto sub-channel 613 (also referred to as second type of occupied sub-channel 613). In this way, upon receiving the encoded information block, the receiving device 120 will bypass the subchannel 614 and start encoding from the subchannel 611 after the subchannel 614. That is, the decoding speed is accelerated, and the decoding delay is reduced.

Fig. 10 shows a flowchart of an example method 1000 of generating an interleaving sequence, in accordance with some other embodiments of the present disclosure. The method 1000 may be implemented at the transmitting device 110 as shown in fig. 1. For purposes of discussion, the method 1000 will be described with reference to fig. 1 from the perspective of the transmitting device 110. It should be understood that method 1000 may include additional blocks not shown and/or may omit some blocks shown, and that the scope of the present disclosure is not limited in this regard.

At block 1010, the transmitting device 110 generates an initial sequence that includes a plurality of information bits and a plurality of check bits in an initial order. At least one parity bit of the plurality of parity bits has a predefined value.

In some embodiments, the predefined value may be 0 or 1.

At block 1020, the transmitting device 110 generates an interleaved sequence of a plurality of information bits and a plurality of check bits by changing an initial order.

At block 1030, the transmitting device 110 encodes the interleaved sequence using a polarization code.

At block 1040, the transmitting device 110 transmits the encoded sequence to the receiving device 120.

In some embodiments, at least one of the plurality of check bits is a bit in a downlink control information message.

In some embodiments, the plurality of check bits are evenly distributed in the interleaved sequence.

Hereinafter, a decoding operation performed at the reception apparatus 120 will be described with reference to fig. 11. Fig. 11 is a schematic diagram of an example polar decoding architecture 1100. As shown, the example polarization decoding structure 1100 includes f-nodes 1111 through 1114 and g-nodes 1121 through 1124.

In some embodiments, the calculations performed at the f-nodes 1111 to 1114 may be represented by the following equation (1), and the calculations performed at the g-nodes 1121 to 1124 may be represented by the following equation (2):

f(a,b)＝sign(a)sign(b)min(|a|,|b|) (1)

g(a,b)＝(-1)^u+b (2)

where a and b denote input parameters of the f nodes 1111 to 1114 and input parameters of the g nodes 1121 to 1124, respectively, and u denotes decoded information bits or decoded check bits.

For leaf nodes in the code tree for polarization decoding, the f nodes 1111 to 1114 are odd index nodes, and the g nodes 1121 to 1124 are even index nodes. The leaf nodes are indexed such that the first node is decoded first in the successive erasure decoder.

As described above, during polar encoding, the transmitting device 110 may arrange the information bits and the check bits, which are copies of the information bits, on the f-node and g-node, respectively, so that they are processed differently. Accordingly, during polar decoding, the receiving device 120 may arrange the encoded information bits on one of the f-nodes 911 and 912 and the encoded check bits on one of the g-nodes 921 and 922. Since the calculations 911 to 914 performed at the f-node and the calculations performed at the g-nodes 921 to 924 are not strongly correlated with each other, the inspection efficiency can be improved.

Fig. 12 is a graph 1200 illustrating simulation results for performance evaluation, in accordance with some embodiments of the present disclosure. In the simulation, an example solution according to an embodiment of the present disclosure is compared with a conventional encoding/decoding scheme. In fig. 12, a curve 1210 represents a conventional encoding/decoding scheme and a curve 1220 represents an example scheme according to an embodiment of the present disclosure. In fig. 12, the horizontal axis represents SNR and the vertical axis represents BLER.

In the simulation, the block size K is taken into account 6 and 6 CRC bits, where two new check bits are introduced. Thus, there are 8 information bits. The two new parity bits are set to the 8 th bit and the 6 th bit, respectively, which are obtained by copying the information bit 5 and the information bit 4, respectively. The list size used is 16. These check bits are used for tree pruning without performing repetition. As can be seen from fig. 12, a gain of about 0.3dB needs to be achieved. It is also observed that for larger list sizes, the gain is higher, which is particularly useful for URLLC, since URLLC may use larger list sizes to achieve better performance.

In some embodiments, an apparatus (e.g., network device 110 or terminal device 120, 130) for performing method 200 may include respective modules for performing corresponding steps in method 200. These modules may be implemented in any suitable manner. For example, it may be implemented by circuitry or software modules.

In some embodiments, the apparatus comprises: means for generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order, at least one of the plurality of check bits being a copy of one of the information bits; means for generating an interleaved sequence of a plurality of information bits and a plurality of parity bits by changing an initial order in a manner that: causing at least one of the plurality of parity bits and one of the information bits to be processed differently during polarization encoding of the interleaved sequence; means for encoding the interleaved sequence using a polar code; and means for transmitting the encoded sequence to a receiving device.

In some embodiments, the means for generating the interleaved sequence comprises means for changing the initial order to evenly distribute the plurality of parity bits to generate the interleaved sequence.

In some embodiments, an apparatus (e.g., network device 110 or terminal device 120, 130) for performing method 700 may include respective modules for performing corresponding steps in method 700. These modules may be implemented in any suitable manner. For example, it may be implemented by circuitry or software modules.

In some embodiments, the apparatus comprises: means for generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order; means for inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to the receiving device; means for generating an interleaved sequence of the plurality of information bits, the plurality of check bits, and the at least one dummy bit by changing an initial order in a manner that: causing at least one dummy bit to be disposed before the plurality of information bits and the plurality of check bits; means for encoding the interleaved sequence using a polar code; and means for transmitting the encoded sequence to a receiving device.

In some embodiments, the at least one dummy bit is determined based on an identity of the receiving device.

In some embodiments, an apparatus (e.g., network device 110 or terminal device 120, 130) for performing method 1000 may include respective modules for performing corresponding steps in method 1000. These modules may be implemented in any suitable manner. For example, it may be implemented by circuitry or software modules.

In some embodiments, the apparatus comprises: means for generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order, at least one check bit of the plurality of check bits having a predefined value; means for generating an interleaved sequence of a plurality of information bits and a plurality of check bits by changing an initial order; means for encoding the interleaved sequence using a polar code; and means for transmitting the encoded sequence to a receiving device.

Fig. 13 is a simplified block diagram of an apparatus 1300 suitable for implementing embodiments of the present disclosure. The device 1300 may be considered as a further example embodiment of the network device 110 and the

terminal devices

120, 130 as shown in fig. 1. Thus, the device 1300 may be implemented at or as at least a part of the network device 110 or the

terminal device

120, 130.

As shown, device 1300 includes a processor 1310, a memory 1320 coupled to processor 1310, a suitable Transmitter (TX) and Receiver (RX)1340 coupled to processor 1310, and a communication interface coupled to TX/RX 1340. Memory 1320 stores at least a portion of program 1330. TX/RX 1340 is used for bi-directional communication. TX/RX 1340 has at least one antenna to facilitate communication, but in practice the access nodes referred to in this application may have multiple antennas. The communication interface may represent any interface required for communication with other network elements, such as an X2 interface for bidirectional communication between enbs, an S1 interface for communication between a Mobility Management Entity (MME)/serving gateway (S-GW) and an eNB, a Un interface for communication between an eNB and a Relay Node (RN), or a Uu interface for communication between an eNB and a terminal device.

Programs 1330 are assumed to include program instructions that, when executed by associated processor 1310, enable device 1300 to operate according to embodiments of the present disclosure, as discussed herein with reference to fig. 2 through 10. The embodiments herein may be implemented by computer software executable by the processor 1310 of the device 1300, or by hardware, or by a combination of software and hardware. The processor 1310 may be configured to implement various embodiments of the present disclosure. Further, the combination of the processor 1310 and the memory 1320 may form a processing device 1350 suitable for implementing various embodiments of the present disclosure.

The memory 1320 may be of any type suitable to the local technology network and may be implemented using any suitable data storage technology, such as non-transitory computer readable storage media, semiconductor-based storage devices, magnetic storage devices and systems, optical storage devices and systems, fixed memory and removable memory, as non-limiting examples. Although only one memory 1320 is shown in device 1300, there may be several physically different memory modules in device 1300. The processor 1310 may be of any type suitable to the local technology network, and may include one or more of general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs) and processors based on a multi-core processor architecture, as non-limiting examples. The device 1300 may have multiple processors, such as application specific integrated circuit chips that are time dependent from a clock synchronized to the main processor.

The components included in the apparatus and/or devices of the present disclosure may be implemented in various ways, including software, hardware, firmware, or any combination thereof. In one embodiment, one or more of the units may be implemented using software and/or firmware, such as machine executable instructions stored on a storage medium. Some or all of the elements in an apparatus and/or device may be implemented at least in part by one or more hardware logic components in addition to or in place of machine-executable instructions. By way of example, and not limitation, illustrative types of hardware logic components that may be used include Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.

In general, the various embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While various aspects of the embodiments of the disclosure are illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product comprises computer-executable instructions, such as those included in program modules, that execute in a device on a target real or virtual processor to perform the processes or methods described above with reference to any of figures 2, 4 and 7. Generally, program modules include routines, programs, libraries, objects, classes, components, data types, etc. that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or split between program modules as desired in various embodiments. Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed facility, program modules may be located in both local and remote memory storage media.

Program code for performing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the execution of the program codes by the processor or controller causes the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

The above program code may be embodied on a machine-readable medium, which may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More specific examples of a machine-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Also, while the above discussion contains several specific implementation details, these should not be construed as limitations on the scope of the disclosure, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the disclosure has been described in language specific to structural features and/or methodological acts, it is to be understood that the disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An electronic device, comprising:

at least one processor; and

at least one memory including computer program code;

the at least one memory and the computer program code configured to, with the at least one processor, cause the electronic device to:

generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order, at least one check bit of the plurality of check bits being a copy of one information bit of the plurality of information bits;

generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in the following manner: causing said at least one of said plurality of parity bits and said one of said information bits to be processed differently during polarization encoding of said interleaved sequence;

encoding the interleaved sequence using a polarization code; and

the encoded sequence is transmitted to a receiving device.

2. The electronic device of claim 1, wherein the at least one of the plurality of check bits is a bit in a downlink control information message.

3. The electronic device of claim 1, wherein the plurality of parity bits are evenly distributed in the interleaved sequence.

4. An electronic device, comprising:

at least one processor; and

at least one memory including computer program code;

generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order;

inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to the receiving device;

generating an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing the initial order in the following manner: causing the at least one dummy bit to be disposed before the plurality of information bits and the plurality of check bits;

encoding the interleaved sequence using a polarization code; and

transmitting the encoded sequence to the receiving device.

5. The electronic device of claim 4, wherein the at least one dummy bit is determined based on an identity of the receiving device.

6. An electronic device, comprising:

at least one processor; and

at least one memory including computer program code;

generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order, at least one check bit of the plurality of check bits having a predefined value;

generating an interleaved sequence of the plurality of information bits and the plurality of check bits by changing the initial order;

encoding the interleaved sequence using a polarization code; and

the encoded sequence is transmitted to a receiving device.

7. The electronic device of claim 6, wherein the at least one of the plurality of check bits is a bit in a downlink control information message.

8. The electronic device of claim 6, wherein the plurality of parity bits are evenly distributed in the interleaved sequence.

9. A method of communication, comprising:

encoding the interleaved sequence using a polarization code; and

the encoded sequence is transmitted to a receiving device.

10. The method of claim 9, wherein the at least one of the plurality of check bits is a bit in a downlink control information message.

11. The method of claim 9, wherein the plurality of parity bits are evenly distributed in the interleaved sequence.

12. A method of communication, comprising:

encoding the interleaved sequence using a polarization code; and

transmitting the encoded sequence to the receiving device.

13. The method of claim 12, wherein the at least one dummy bit is determined based on an identity of the receiving device.

14. A method of communication, comprising:

encoding the interleaved sequence using a polarization code; and

the encoded sequence is transmitted to a receiving device.

15. The method of claim 14, wherein the at least one of the plurality of check bits is a bit in a downlink control information message.

16. The method of claim 14, wherein the plurality of check bits are evenly distributed in the interleaved sequence.

17. A computer-readable medium having instructions stored thereon that, when executed on at least one processor of a device, cause the device to at least:

encoding the interleaved sequence using a polarization code; and

the encoded sequence is transmitted to a receiving device.

18. A computer-readable medium having instructions stored thereon that, when executed on at least one processor of a device, cause the device to at least:

encoding the interleaved sequence using a polarization code; and

the encoded sequence is transmitted to a receiving device.

19. A computer-readable medium having instructions stored thereon that, when executed on at least one processor of a device, cause the device to at least:

encoding the interleaved sequence using a polarization code; and

the encoded sequence is transmitted to a receiving device.

20. A communication device, comprising:

means for generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits being a copy of one of the plurality of information bits;

means for generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in a manner that: causing said at least one of said plurality of parity bits and said one of said information bits to be processed differently during polarization encoding of said interleaved sequence;

means for encoding the interleaved sequence using a polarization code; and

means for transmitting the encoded sequence to a receiving device.

21. The apparatus of claim 20, wherein the at least one of the plurality of check bits is a bit in a downlink control information message.

22. The apparatus of claim 20, wherein the plurality of parity bits are evenly distributed in the interleaved sequence.

23. A communication device, comprising:

means for generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order;

means for inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to a receiving device;

means for generating an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing the initial order in a manner that: causing the at least one dummy bit to be disposed before the plurality of information bits and the plurality of check bits;

means for encoding the interleaved sequence using a polarization code; and

means for transmitting the encoded sequence to the receiving device.

24. The apparatus of claim 23, wherein the at least one dummy bit is determined based on an identity of the receiving device.

25. A communication device, comprising:

means for generating an initial sequence comprising a plurality of information bits and a plurality of check bits in an initial order, at least one check bit of the plurality of check bits having a predefined value;

means for generating an interleaved sequence of the plurality of information bits and the plurality of check bits by changing the initial order;

means for encoding the interleaved sequence using a polarization code; and

means for transmitting the encoded sequence to a receiving device.

26. The apparatus of claim 25, wherein the at least one of the plurality of check bits is a bit in a downlink control information message.

27. The apparatus of claim 25, wherein the plurality of parity bits are evenly distributed in the interleaved sequence.