CN113573403A

CN113573403A - Slave clock synchronization system and method for 5G RRU

Info

Publication number: CN113573403A
Application number: CN202110845443.0A
Authority: CN
Inventors: 孙勇; 彭金民; 徐光�; 陈平
Original assignee: Nanjing Howking Technology Co ltd
Current assignee: Nanjing Howking Technology Co ltd
Priority date: 2021-07-26
Filing date: 2021-07-26
Publication date: 2021-10-29
Anticipated expiration: 2041-07-26
Also published as: CN113573403B

Abstract

The invention relates to the technical field of 5G mobile communication, in particular to a slave clock synchronization system for a 5G RRU (remote radio unit), which comprises an FPGA (field programmable gate array), an ARM (advanced RISC machine) and an HCU (hybrid control unit), wherein the FPGA is used for identifying and forwarding a PTPv2 message sent by a BBU (baseband unit) and adding a timestamp to a PTPv2 message; the ARM is used for processing the PTPv2 message sent by the FPGA, extracting a receiving timestamp from the PTPv2 message, calculating link delay and time offset and controlling the HCU; and the HCU is used for realizing a PTP hardware clock when receiving the ARM driving signal, and simultaneously outputting 1pps and high-precision TOD information for the synchronization of the FPGA, so as to realize the synchronization with the BBU. Based on the existing platform, the method solves the problem of slave clock synchronization of the RRU, and can effectively save the cost; through the clock synchronization chip, the research and development period and the cost are greatly reduced.

Description

Slave clock synchronization system and method for 5G RRU

Technical Field

The invention relates to the technical field of 5G mobile communication, in particular to a slave clock synchronization system and method for a 5G RRU.

Background

With the promotion and increasing popularization of 5G mobile phones, the requirements of 5G applications are continuously expanded, and the large use of application technologies such as big data, virtual reality VR, unmanned driving, Internet of things and the like prompts the 5G applications to formally walk into the public vision and gradually enter thousands of households. The 5G technology has the advantages of high speed, low latency, high throughput and the like, and is suitable for the technology, and the precision requirement on clock synchronization (including clock frequency synchronization and clock phase synchronization) in 5G application is higher. The clock synchronization precision of the traditional 2G/3G/4G mobile network generally only reaches a delicate order of magnitude, and is more than enough to meet the requirements of general application, but with the application and popularization of the 5G technology, the precision is very important. For 5G applications, at least up to sub-microsecond level is required to meet the normal development of 5G services and the daily life needs of people.

The application of the 5G technology cannot leave the base station construction and reasonable layout of the 5G network. Although each large operator may make full use of the existing 3G/4G station infrastructure, such as a shared base station room, an antenna tower, etc., when laying out a 5G network, from the viewpoint of cost reduction, it is necessary to add some necessary 5G related facilities. Generally, a complete set of 5G base station facilities includes a base station processing unit BBU connected to a core service network, a plurality of radio remote units RRUs, an antenna feeder transceiver unit AAU, and supporting facilities such as a relay RRU HUB, a power supply system, an optical fiber feeder facility, a lightning protection facility, and the like. Of course, there is an indispensable key facility in these facilities, namely a precise time service system, to unify the work of each component so that they can work in a coordinated and cooperative manner. The time service system is closely related to service processing, and the facilities related to the service processing mainly include a base station processing unit BBU, a radio remote unit RRU, relay equipment RRU and a HUB.

Generally speaking, the simplest and most direct scheme for realizing an accurate time service system is to adopt high-precision time service equipment such as a GPS and a beidou BDS, the precision of which can reach a sub-microsecond level and can completely meet the service requirement of a 5G network, but the use of the time service equipment is expensive on one hand, and the cost is too high if the time service equipment is used in each BBU, RRU and RRU HUB facility; on the other hand, these time service devices mainly rely on satellites to work, and are difficult to install and select addresses, and cannot work normally in areas where satellite signals cannot be received.

In order to reduce the cost, the synchronous Ethernet SyncE and/or IEEE 1588 protocol specification is adopted to become an alternative solution for realizing clock synchronization. The synchronous ethernet transmits and recovers a clock signal in a hardware coding and decoding manner, the precision of the synchronous ethernet can reach microsecond level, and in order to achieve higher precision, the synchronous ethernet is usually required to be matched with and applied to IEEE 1588 protocol specification. The IEEE 1588 Protocol specification is set by the IEEE 1588 working group, and a Precision Time synchronization Protocol (PTP) defined by the specification is widely used in measurement and automation systems due to its openness, and is particularly suitable for applications in ethernet and distributed network environments. The protocol specification is updated to v2 version at present to meet the requirement of clock synchronization with higher precision in a distributed network environment, wherein the precision can reach sub-microsecond level or even sub-nanosecond level.

In a 5G base station system, usually, a main clock mode is adopted at one end of a baseband processing unit BBU, and a slave clock mode is adopted at one end of a radio remote unit RRU, and the radio remote unit RRU is directly or indirectly (through an RRU HUB) connected to the BBU through an optical fiber. In order to control the cost and meet a certain synchronization precision requirement, the invention aims to solve the problem of determining a proper IEEE 1588v2 implementation scheme under the condition of an existing software and hardware platform and solve the slave clock synchronization problem of RRU equipment.

The current 5G RRU system platform adopts the system architecture shown in fig. 2, that is, a 4 × 4MIMO wireless radio frequency function is realized by an organization mode of FPGA + ARM + RF and front end, and the basic functions of each component or module are as follows:

FPGA: the base band signal processing and service distribution functions of the RRU are realized;

ARM: the functions of RF configuration, system monitoring, operation and maintenance management and the like are realized;

RF and front end: and the 4-by-4 MIMO channel is connected with the FPGA and an external antenna unit AAU, so that the signal conversion processing and distribution transmission of the baseband service signal from the FPGA and the RF terminal user service signal from the AAU are realized.

In the existing 5G RRU system platform, the FPGA is not an integrated chip with an ARM core embedded therein, so that an ARM processor needs to be externally connected to implement functions such as specific configuration and management.

In order to implement IEEE 1588 clock synchronization and improve synchronization accuracy as much as possible, the FPGA needs to have a capability of timestamp management, i.e., "stamping", and also needs to have a capability of recognizing and processing PTPv2 messages. When the PTPv2 message from the BBU reaches the RRU through the optical/electrical port, the FPGA is the first component for processing the message, namely the message data is encoded, the FPGA needs to decode first, and then the PTPv2 message can be identified from the encoded message data and processed by stamping, so the stamping is not given to the FPGA, otherwise the required clock synchronization precision cannot be achieved. As for the processing of the PTPv2 message, it is a relatively complex task, and it is obviously impractical to give the FPGA a complete task — even for an FPGA chip with an embedded ARM core, this part of the task is given to the ARM core in the chip to complete. Therefore, for the 5G RRU serving as the slave clock, the FPGA only needs to realize the function of identifying the PTPv2 message, and the relevant PTPv2 message processing work is finished by an external ARM processor. One additional task that the FPGA needs to do is to "stamp" the PTPv2 message from the ARM processor before it is encoded and sent to the BBU via the optical/electrical ports.

In order to realize the processing of the PTP message, the ARM processor usually adopts an open-source protocol stack and an open-source upper layer application, but there is a difficulty that the open-source protocol stack is based on a Linux kernel (at least the kernel above v3.0 supports), while the PTP implementation mechanism of the Linux kernel is based on a high-precision PTP clock source, and only the kernel of an updated or higher version supports the complete PTP function and the expansion characteristic thereof. The ARM processor of the current system platform is ARM9, the Linux kernel version is based on v2.6, if PTP function is to be realized, the kernel is upgraded to a high version or the PTP function is transplanted from the high version to the current kernel version without considering the replacement of the ARM processor, although both of them have difficulty. But is a threshold that must be crossed.

Disclosure of Invention

The invention provides a slave clock synchronization system and a slave clock synchronization method for a 5G RRU, which realize the slave clock synchronization of RRU equipment based on the existing platform and have the advantage of low cost.

In order to realize the purpose of the invention, the adopted technical scheme is as follows: a slave clock synchronization system for a 5G RRU, characterized by: comprises an FPGA, an ARM and an HCU,

the FPGA is used for identifying and forwarding the PTPv2 message sent by the BBU, and adding a timestamp to the PTPv2 message;

the ARM is used for processing the PTPv2 message sent by the FPGA, extracting a receiving timestamp from the PTPv2 message, calculating link delay and time offset and controlling the HCU;

and the HCU realizes a PTP hardware clock when receiving the ARM driving signal, and simultaneously outputs 1pps and high-precision TOD information for the FPGA to synchronize, thereby realizing the synchronization with the BBU.

As an optimization scheme of the invention, the FPGA comprises a PMACU unit and a TSU unit, the PMACU unit realizes the forwarding of the PTPv2 message, and a time stamp is added to the PTPv2 message in the TSU unit.

As an optimization scheme of the invention, PTPv2 message transmission is realized between the FPGA and the ARM through an RMMI interface, and the FPGA comprises an MII-to-RMMI module.

In order to achieve the purpose of the present invention, the adopted technical solution is a method for synchronizing a slave clock synchronization apparatus of a 5G RRU, comprising the following steps:

1) the BBU informs the RRU to start time synchronization by sending a SYNC message to the RRU;

2) after decoding, an FPGA in the RRU identifies a SYNC message, and the TSU adds a timestamp to the SYNC message and sends the SYNC message to the PMACU unit to be sent to the ARM;

3) the ARM receives the SYNC message and submits the SYNC message to an upper-layer open source PTP protocol stack application program, and the open source PTP protocol stack application program processes the SYNC message and takes corresponding timestamp information as receiving stamp information t2 of the SYNC message;

4) if the open source PTP protocol stack application program detects that the SYNC message is a one-step synchronous message, extracting the sending timestamp information t1 of the BBU from the SYNC message;

5) the open source PTP protocol stack application program generates a DELAY REQ message, and the ARM sends the DELAY REQ message to the PMACU unit;

6) the PMACU unit adds a timestamp to the received DELAY REQ message by the TSU unit, then sends the message to the BBU, and meanwhile, the ARM acquires timestamp information t3 of the DELAY REQ message from the FPGA;

7) after receiving the DELAY REQ message, the BBU generates DELAY RESP messages and sends the DELAY RESP messages to the RRU;

8) and the RRU receives DELAY RESP messages, extracts the receiving timestamp information t4 of the BBU from the messages, and after the timestamp information participates in calculation, the ARM controls the HCU to carry out time synchronization operation, and the HCU outputs 1pps and high-precision TOD information for the FPGA to synchronize so as to realize synchronization with the BBU.

As an optimization scheme of the present invention, in step 4), if the open source PTP protocol stack application detects that the SYNC message is a two-step synchronization message, the following steps are executed:

41) the BBU sends a FOLLOW UP message, the FPGA receives the FOLLOW UP message, the TSU adds a timestamp and sends the message to the ARM;

42) the ARM receives the FOLLOW UP message, submits the FOLLOW UP message to the open source PTP protocol stack application program, the open source PTP protocol stack application program ignores the stamping information of the FOLLOW UP message, the sending time stamp information t1 of the BBU is extracted from the SYNC message, and then the step 5 is skipped.

As an optimization scheme of the invention, the FPGA adds timestamp information to all the received messages, and the FPGA simultaneously judges whether the messages are the PTPv2 messages or not and sends the messages marked with the time information of the PTPv2 messages to a PMACU unit; the FPGA discards the time information of the non-PTPv 2 message and then sends the message to the PMACU unit.

The invention has the positive effects that: 1) based on the existing platform, the method solves the problem of slave clock synchronization of the RRU, and can effectively save the cost;

2) the invention greatly reduces the research and development period and cost through the clock synchronization chip;

3) the invention is easy to expand and has universality.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a system architecture diagram of a slave clock synchronization system for a 5G RRU of the present invention;

fig. 2 is a system architecture diagram of a conventional 5G RRU;

FIG. 3 is a flow chart of a process for a SYNC message being a one-step synchronization message;

FIG. 4 is a flow chart of a process for a SYNC message being a two-step synchronization message;

FIG. 5 is a logic diagram of a PMACU cell of the FPGA;

FIG. 6 is a TSU cell logic diagram for an FPGA;

FIG. 7 is a data area structure diagram of a data field;

fig. 8 is a length field value of udp data 1588 data.

Detailed Description

The implementation of the invention is described in further detail below with reference to the attached drawing figures:

as shown in fig. 1, a slave clock synchronization system for 5G RRU comprises an FPGA, an ARM and an HCU,

and the HCU is used for realizing a PTP hardware clock when receiving the ARM driving signal, and simultaneously outputting 1pps and high-precision TOD information for the synchronization of the FPGA, so as to realize the synchronization with the BBU. The hcu (hardware Clock unit) is a Clock synchronization chip of a third party, and after the chip is added, the 5G RRU system has the following newly added functions except for the basic functions that need to be realized originally:

FPGA: two functional units, namely a PMACU (Peer MAC Unit) unit and a Time Stamping Unit (TSU) unit are added. The message forwarding of the PTPv2 is realized in the PMACU unit through an MAC interface (MII/RMII); the 'stamping' function of the PTPv2 message is realized in the TSU;

ARM: the method comprises the following steps that PTPv2 message processing is realized in a LInux kernel, an open source PTP protocol stack and upper layer application thereof, a HCU driver and the like are added;

HCU: related functions of a PTP Hardware Clock (PTP Hardware Clock) are realized, and 1PPS and high-precision TOD information are output for being used by an FPGA and other parts needing precise synchronization.

As shown in fig. 3, a method for synchronizing a slave clock synchronization apparatus of a 5G RRU includes the following steps:

8) and after the RRU receives DELAY RESP messages and extracts the receiving time stamp information t4 of the BBU from the messages, and after the time stamp information (t1, t2, t3 and t4) participates in calculation, the ARM controls the HCU to carry out time synchronization operation, and the HCU outputs 1pps and high-precision TOD information for FPGA synchronization, so that synchronization with the BBU is realized.

As shown in fig. 4, in step 4), if the open source PTP protocol stack application detects that the SYNC message is a two-step SYNC message, the following steps are performed:

In step 8), the ARM calculates the link delay and the time offset through a certain algorithm, and controls the HCU to perform the time synchronization operation.

It should be noted that master-slave clock synchronization compliant with IEEE 1588 specification is a step-by-step optimization procedure, which is initiated by the master clock BBU end and performed periodically, in order to achieve a stable and ideal synchronization state.

The functions realized in the FPGA are mainly a TSU unit with a timestamp marking function and a PMACU unit with a PTPv2 message forwarding function, wherein the TSU unit has two functions of timestamp marking and message analysis. The communication between the RRU and the BBU stipulates that 1588 protocol data uses a packet bearer of a UDP protocol, a standard Ethernet MAC protocol is used, and the MAC frame format between the RRU and the BBU is an IP frame. Therefore, the precondition of message analysis is that the FPGA detects the Ethernet mac frame format, and firstly detects whether the data frame is an IP frame or not, and then detects whether the data frame is a message of a UDP protocol or not.

The frame format used in the present invention is shown in table 1, wherein when the type value is equal to 0x0800, it indicates that the data frame is an IP frame, the data field includes an IP header and load data, the first 20 bytes of the data are standard IP headers, and the 8-bit protocol value is defined to be 17 (in application, 1588 protocol data is carried by udp packet, and the corresponding value is 17).

7 bytes

1 byte

6 bytes

2 bytes

46-1500 bytes

4 bytes

Lead code

Start frame

Destination physical address

Source physical address

Type (B)

Data of

Frame sequence detection

TABLE 1

The data field of the data field includes the udp header and the udp payload, see fig. 7. Wherein, the source/destination port indicates the port numbers of the sender and the receiver, the udp data area is the data actually sent or received by the upper layer application, and the 1588 protocol data is included in the udp load section. Since udp data can be freely specified by a user, in the 1588 implementation, it needs to assist to determine whether currently received data is 1588 data according to port information and a length field in the udp header, that is, if udp data is 1588 data, the following conditions must be simultaneously satisfied:

1) the port number is a port specified by standard 1588 protocol: 319 or 320;

2) the length field value reaches at least the size of the ptp header (i.e. 34 bytes), see fig. 8;

3) the version field of the PTP header takes the value 2.

Therefore, the FPGA can correctly analyze the message, and the PTPv2 message can be stamped after being detected. If the message is analyzed first and is not a PTP type message, then the timestamp is stamped, which may result in a delay of the timestamp. In order to analyze and stamp the message at the same time, the communication protocol provides that whether the message is a PTPv2 message or not, the message is stamped, whether the message is a PTP message or not is judged, the message which is the PTP message is marked with time information and then sent to a PMACU unit, and if the message is not the PTP message, the time information is directly discarded, and the message is sent to a PMACU module, so that the influence on time synchronization can be reduced as much as possible.

After the FPGA correctly analyzes the message from the ARM or BBU, the timestamp is marked, and the specific position of the mark is determined by the frame format of the Ethernet. The first 8 bytes of the frame format respectively represent the bit synchronization and the frame start position, so as long as the FPGA identifies the seventh byte and detects the start position of the frame, the time information at the moment is recorded, and the time stamp function is completed.

The function of sending the message marked with the timestamp to the ARM or BBU by the FPGA is realized in the PMACU module, as shown in fig. 5, which includes a FIFO memory unit for receiving and sending data, an MII to RMII module, an MDIO, an IP of the MAC of the FPGA itself, and the like. Due to the limitation of the function of the ARM processor in the existing platform, PTP message transmission can be realized between the FPGA and the ARM only through the RMII interface. The FPGA can not directly call the RMII protocol, so that an MII-to-RMII module is needed, the IP of the MII protocol is called, and an FIFO module is added at the input end and the output end of data, so that the data transmission process is completely aligned, and the correct transmission of the PTPv2 message is finally realized.

The TSU unit in the FPGA has the functions that firstly, Ethernet data packets entering the TSU unit are counted in a counter module, after 7 bytes are determined, an enable signal is generated, after time information is determined, the enable signal of a register is triggered, and the time information is stored in the register. And then the subsequent packet and the packet are sent to the PMACU unit for subsequent calculation of the delay, as shown in fig. 6.

The second purpose of the invention is to achieve cost control, and the adopted technical scheme can reduce the cost as much as possible. Because there is no need to replace a more advanced FPGA chip or ARM chip.

The third purpose of the invention is to realize controllable research and development time, the selected technical scheme is easy to realize, and the method can be completed in the established research and development period, so that the finally developed product can not lose market opportunity due to the overlong research and development period. The driving of the third-party clock synchronization chip is realized based on an open source, and technical support provides guarantee, so that the third-party clock synchronization chip is transplanted to the existing platform, and the required research and development time is controllable.

Compared with the prior art, the workload and the difficulty of PTP function transplantation of the Linux kernel of the ARM are much higher, in order to reduce research and development burden and reduce the difficulty, large and complete functions are not pursued during transplantation, a minimum transplantation strategy is adopted, namely relevant function codes are transplanted from the kernel of a lower version (v3.x) supporting PTP functions, irrelevant codes are uniformly removed, and the transplantation target is only to achieve the aim of supporting the basic PTP clock synchronization function.

As for the processing of the PTPv2 message, this part can be completely based on an open source implementation, and hardly occupies a development cycle.

In summary, the above measures can ensure that the development time of the project is controllable.

The fourth purpose of the invention is easy to expand, and the adopted technical scheme is required to have good expansibility, and the function can be easily realized without great framework change during function upgrading.

The technical scheme for realizing the fourth purpose of the invention is as follows: the adopted clock synchronization scheme is based on the realization of an open source, the PTP protocol stack runs in an ARM processor system, and the function is easy to expand. The organization architecture of the technical scheme is relatively open and has universality, a third-party clock chip and an ARM processor or even an FPGA chip in the architecture are not limited to a single certain model, a product designer can replace the third-party clock chip and the ARM processor or even the FPGA chip according to the corresponding chip model of the product used by the product designer, the same function can be realized as long as the same organization architecture is maintained, and the expected precision requirement is met. The design idea of the technical scheme is not only suitable for synchronous design of the slave clocks, but also suitable for synchronous design of the master clock, and certainly, the latter has more and more complex requirements on functions to be realized by the FPGA.

The above-mentioned embodiments only express the embodiments of the present invention, and the description thereof is more specific and detailed, and therefore, the present invention should not be construed as limiting the scope of the present invention. It should be noted that several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Claims

1. A slave clock synchronization system for a 5G RRU, characterized by: comprises an FPGA, an ARM and an HCU,

2. The slave clock synchronization system of claim 1 for a 5G RRU, wherein: the FPGA comprises a PMACU unit and a TSU unit, the PMACU unit realizes the forwarding of the PTPv2 message, and a time stamp is added to the PTPv2 message in the TSU unit.

3. The slave clock synchronization system for a 5G RRU of claim 2, wherein: PTPv2 message transmission is realized between the FPGA and the ARM through an RMMI interface, and the FPGA comprises an MII-to-RMMI module.

4. The slave clock synchronization system for a 5G RRU of claim 2, wherein: the HCU is a clock synchronization chip.

5. A method for synchronizing with the slave clock synchronization apparatus for 5G RRU according to claim 2, wherein: the method comprises the following steps:

3) the ARM receives the SYNC message and submits the SYNC message to an upper-layer open source PTP protocol stack application program, and the open source PTP protocol stack application program processes the SYNC message and takes corresponding timestamp information as receiving timestamp information t2 of the SYNC message;

5) the open source PTP protocol stack application program generates a DELAY REQ message, and the ARM sends the DELAYREQ message to the PMACU unit;

6. The method of claim 5, wherein the slave clock synchronization device is used for 5G RRU, and the method comprises the following steps: in step 4), if the open source PTP protocol stack application detects that the SYNC message is a two-step SYNC message, the following steps are executed:

7. A method for synchronization of a slave clock synchronization device for a 5G RRU according to claim 5 or 6, characterized by: the FPGA adds timestamp information to all the received messages, and the FPGA simultaneously judges whether the messages are the PTPv2 messages or not, and sends the messages marked with the time information of the PTPv2 messages to the PMACU unit; the FPGA discards the time information of the non-PTPv 2 message and then sends the message to the PMACU unit.