CN113572941A - Multifunctional image acquisition device applied to CPCI computer - Google Patents

Multifunctional image acquisition device applied to CPCI computer Download PDF

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Publication number
CN113572941A
CN113572941A CN202110937245.7A CN202110937245A CN113572941A CN 113572941 A CN113572941 A CN 113572941A CN 202110937245 A CN202110937245 A CN 202110937245A CN 113572941 A CN113572941 A CN 113572941A
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module
data
image
fpga
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任明
吴川
高云龙
冯洋
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/80—Camera processing pipelines; Components thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast

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Abstract

The invention provides a multifunctional image acquisition device applied to a CPCI computer, which comprises: the system comprises a video decoding module for transmitting and converting images, a time code conversion module for transmitting and converting time codes, an FPGA module for enhancing images and processing time codes, a first SDRAM module and a second SDRAM module for caching related data, a DSP module for calculating a target position in real time according to the images, and a PCI module for connecting a CPCI computer; the invention integrates the chips such as FPGA, SDRAM, PCI and DSP, realizes the stable and reliable acquisition of image and time code data in real time, has high-efficiency real-time data processing capability, and simultaneously realizes the continuous caching of related data during data transmission; the invention can not only collect images through the CPCI bus, but also transmit the images through the network port, and can analyze the direct current B time code generated by the GPS or the Beidou system.

Description

Multifunctional image acquisition device applied to CPCI computer
Technical Field
The invention relates to the field of computer image acquisition, in particular to a multifunctional image acquisition device applied to a CPCI computer.
Background
The image acquisition device is used for transmitting image data generated by output equipment such as a CCIR or PAL camera, a television and the like to a computer through a bus, and images can be displayed, processed and stored on the computer by programming a driving program. The CPCI computer has higher reliability and stability than a PCI bus interface because the interface uses an European card connector and standard 3U and 6U board card sizes, so the CPCI computer is widely applied to the severe environments of vehicle-mounted and ship-mounted and the like, an image acquisition card in the market can transmit an original image to the CPCI computer, and then the computer processes the image, thereby greatly influencing the processing speed of the computer and achieving the standard of real-time image processing.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a multifunctional image acquisition device applied to a CPCI computer.
In order to achieve the purpose, the invention adopts the following specific technical scheme:
the invention provides a multifunctional image acquisition device applied to a CPCI computer, which comprises: the system comprises a video decoding module for transmitting and converting images, a time code conversion module for transmitting and converting time codes, an FPGA module for enhancing images and processing time codes, a first SDRAM module and a second SDRAM module for caching data related to the time codes and the images, a DSP module for reducing the calculation amount of a CPCI computer and calculating the target position in real time according to the images, and a PCI module for connecting the CPCI computer;
the video decoding module is connected between the camera and the FPGA module;
the time code conversion module is connected between the time code generator and the FPGA module;
the first SDRAM module, the second SDRAM module and the DSP module are respectively connected with the FPGA module;
the PCI module is connected between the FPGA module and the CPCI computer.
Preferably, the multifunctional image acquisition device applied to the CPCI computer further comprises a portal video output module for transmitting data.
Preferably, the image decoded by the video decoding module is a YUV image; the video decoding module calculates pixel data, pixel clock data, line field synchronous data and odd-even field data of the image according to the image and transmits the pixel data, the pixel clock data, the line field synchronous data and the odd-even field data to the FPGA module.
Preferably, the time code conversion module converts the differential signal of the time code into a path of B code signal of TTL level to obtain high and low level data, and the time code conversion module transmits the high and low level data to the FPGA module.
Preferably, the network port video output module is connected with the FPGA module; and the network port video output module regenerates an image according to the pixel data, the pixel clock data, the line field synchronous data and the odd-even field data, compresses the image and outputs the compressed image through the Ethernet.
The invention can obtain the following technical effects:
the invention integrates the chips such as FPGA, SDRAM, PCI and DSP, realizes the stable and reliable acquisition of image and time code data in real time, has high-efficiency real-time data processing capability, and simultaneously realizes the continuous caching of related data during data transmission; the invention can not only collect images through the CPCI bus, but also transmit the images through the network port, and can analyze the direct current B time code generated by the GPS or the Beidou system.
Drawings
Fig. 1 is a schematic structural diagram of a multifunctional image acquisition device applied to a CPCI computer according to an embodiment of the present invention;
fig. 2 is a main flowchart when the multi-functional image pickup device applied to the CPCI computer processes image data according to an embodiment of the present invention;
fig. 3 is a flowchart of the CPCI computer controlling the multi-functional image capturing device applied to the CPCI computer to capture data according to the embodiment of the present invention.
Wherein the reference numerals include: the device comprises a video decoding module 1, a time code conversion module 2, an FPGA module 3, a first SDRAM module 4, a second SDRAM module 5, a DSP module 6, a network port video output module 7, a PCI module 8, a camera 9, a time code generator 10 and a CPCI computer 11.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same blocks. In the case of the same reference numerals, their names and functions are also the same. Therefore, detailed description thereof will not be repeated.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention.
The specific operation of the present invention will be described in detail with reference to fig. 1 to 3:
as shown in fig. 1, the present invention provides a multifunctional image capturing device applied to a CPCI computer 11, comprising: the device comprises a video decoding module 1, a time code conversion module 2, an FPGA module 3, a first SDRAM module 4, a second SDRAM module 5, a DSP module 6, a network port video output module 7 and a PCI module 8.
The video decoding module 1 is used for transmitting and converting images. The video decoding module 1 is connected between the camera 9 and the FPGA module 3. The image decoded by the video decoding module 1 is a YUV image; the video decoding module 1 calculates pixel data, pixel clock data, line field synchronization data and odd-even field data of the image according to the image and transmits the pixel data, the pixel clock data, the line field synchronization data and the odd-even field data to the FPGA module 3.
In an embodiment of the present invention, a TVP5150 chip is used as a video decoding chip of the video decoding module 1, and a frame frequency of a generated YUV image is 25frames/s, wherein valid data of one frame of image is 1440 pixels 576 pixels, one frame of image is divided into odd field and even field transmission, and a pixel clock calculated by the TVP5150 chip is 27M.
The time code conversion module 2 is used for transmitting and converting time codes. The time code conversion module 2 is connected between the time code generator 10 and the FPGA module 3. The time code conversion module 2 converts the differential signal of the time code into a path of a TTL level B code signal to obtain high and low level data, and the time code conversion module transmits the high and low level data to the FPGA module 3.
In an embodiment of the present invention, the time code conversion module 2 performs level conversion by using a MAX3490 chip, converts the differential signal of the time code into a path of TTL level B code signal, and transmits the TTL level B code signal to the FPGA module 3.
The FPGA module 3 is used for enhancing images and processing time codes.
The method for enhancing the image by the FPGA module 3 comprises the following steps:
a1, FPGA module 3 calculates the maximum pixel value and the minimum pixel value of each line of a field image according to the pixel point of a field image (both odd field image and even field image) in one of the frames of images transmitted by video decoding module 1;
a2, the FPGA module 3 calculates the average max of the maximum pixel values of all the rows and the average min of the minimum pixel values of all the rows according to the maximum pixel value and the minimum pixel value of each row;
a3, FPGA module 3 calculates average ave of pixel values greater than max in pixel values according to pixel values of pixel points of another field (different from the field in step A1) imagemaxAnd an average ave of pixel values less than min valuemin；
A4, FPGA module 3 according to formula (I) to the video decoding module 1 transmitted all images to carry on the linear amplification of the pixel value, finish the image enhancement; the formula (I) is shown below:
Figure BDA0003213282660000041
wherein input represents the original pixel value of the image transmitted by the video decoding module 1, and output represents the pixel value of the output enhanced image; when input<aveminWhen output is 0.
And after receiving the time code data, the FPGA module 3 decodes the time according to the standard format of the time code.
In one embodiment of the present invention, the symbol width of each time code is 10ms, the pulse width of 0 code is 2ms, the pulse width of 1 code is 5ms, and the pulse width of flag P code is 8 ms; the adopted clock is a frequency division clock (10MHz) of an input clock (50MHz) of the FPGA module 3, the pulse width is counted by the frequency division clock, 0 code, 1 code or P code can be known according to the counted value, and the information of year, month, day, hour, minute and second is extracted according to the format of the time code.
The FPGA module 3 is also added with a self-checking function, and the method comprises the following steps:
b1, replacing blanking line data of a line before the effective image data with time data, and setting a start flag bit as a data self-checking start point at the start point of the line;
b2, the FPGA module 3 judges whether the initial position of the data stored in the first SDRAM module 4 and the second SDRAM module 5 is the initial flag bit, if the initial position of the data stored in the first SDRAM module 4 and the second SDRAM module 5 is the initial flag bit, the FPGA module 3 determines that no data loss occurs; otherwise, the FPGA module 3 determines that the data loss occurs. In an embodiment of the present invention, if the FPGA module 3 determines that a data loss occurs, the IP core FIFOs in the first SDRAM module 4, the second SDRAM module 5, and the FPGA module 3 are reset.
The first SDRAM module 4 and the second SDRAM module 5 are used to buffer data related to time codes and images. The first SDRAM module 4 and the second SDRAM module 5 are respectively connected with the FPGA module 3.
Because the FPGA module 3 also has the problem of unmatched clocks when transmitting data to the PCI module 8, in order to ensure the reliability and stability of data transmission, the invention adopts the first SDRAM module 4 and the second SDRAM module 5 to carry out a double-cache mechanism of two SDRAM, thereby ensuring the matching of the sequential logic of data transmission. When any SDRAM module stores full data, the interrupt of the PCI module 8 is triggered, and the data are subjected to DMA transmission; meanwhile, other collected data can be transmitted to another SDRAM module for storage.
The first SDRAM module 4 and the second SDRAM module 5 can collect and transmit image data in turn and alternately, and the problem of image cache interruption during image data transmission is solved. In one embodiment of the present invention, the first SDRAM module 4 and the second SDRAM module 5 may store 1440 × 289(1440 × 288+1440) 8-bit data, respectively.
For 1440 × 288+1440 8bit data, wherein:
1440 × 288 8-bit data are image data in a conventional format;
the 1440 pieces of 8-bit data are one line of time data added before the image data by the FPGA module 3, and the time data are calculated by the time code conversion module 2 and include time information such as year, month, day, hour, minute, second, and the like.
The CPCI computer 11 can acquire not only the image data but also time information corresponding to the image data after acquiring the 1440 × 289(1440 × 288+1440) pieces of 8-bit data.
The DSP module 6 is used to reduce the amount of computation of the CPCI computer 11 and to calculate the target position from the image in real time. The DSP module 6 is connected with the FPGA module 3.
While the conventional function of calculating the target position in real time from the image is realized by the CPCI computer 11, the present invention adds the DSP module 6 capable of calculating the target position in real time from the image, thereby reducing the amount of calculation of the CPCI computer 11.
The FPGA module 3 transmits the image area where the target is located to the DSP module 6, the DSP module 6 calculates the position miss distance and the tracking state result of the target according to the received image area, the position of the target is calculated in real time, the position miss distance, the target tracking frame and the tracking state result of the target are returned to the FPGA module 3, the FPGA module 3 performs character superposition on the image according to the information fed back by the DSP module 6, the tracking frame of the target is drawn, and the image is displayed on the next frame of image of the video to be tracked.
When the contrast ratio of the target image is lower, the FPGA module 3 can transmit the image enhanced by the FPGA module 3 to the DSP module 6, so that the tracking effect of the image target is better.
The PCI module 8 is used to connect to a CPCI computer 11. The PCI module 8 is connected between the FPGA module 3 and the CPCI computer 11.
In an embodiment of the present invention, the PCI chip adopted by the PCI module 8 has a model of PCI9054, supports 32-bit data bits, and has a clock frequency of 33 MHz.
As shown in fig. 3, the process of transmitting the image from the FPGA module 3 to the CPCI computer 11 after passing through the PCI module 8 is as follows:
c1, the CPCI computer 11 starts to collect data;
c2, CPCI computer 11 sends out the order of starting to collect data to PCI module 8, PCI module 8 produces LHOLD signal and transmits to FPGA module 3;
c3, FPGA module 3 receives the application of PCI module 8 to the local end operation right;
c4, FPGA module 3 responds to LHOLD signal, and gives operation right to PCI module 8;
c5, CPCI computer 11 starts receiving data through PCI module 8.
The multifunctional image capturing apparatus applied to the CPCI computer 11 further includes: and a network port video output module 7.
The network port video output module 7 is used for transmitting data to the outside. And the network port video output module 7 is connected with the FPGA module 3. The network port video output module 7 compresses the pixel data, the line field synchronization data, the odd-even field data, and the pixel clock data of the image and outputs the compressed data through the ethernet.
In an actual application environment, the image data not only needs to be transmitted to the CPCI computer 11, but also needs to be remotely transmitted to a display control console or a command center; the existing acquisition device realizes the remote transmission function by adding a module of a CCIR or PAL mode video switching network port independently, which wastes resources and time, and the invention regenerates images according to pixel data, pixel clock data, line field synchronous data and odd-even field data by a network port video output module 7, and outputs the images through Ethernet after compressing.
The image regenerated by the internet access video output module 7 can be an original image or an image enhanced by the FPGA module 3.
In an embodiment of the present invention, the network interface video output module 7 uses a DM368 core development board to compress the acquired CCIR or PAL system video by h.264 and then transmits the compressed video through the ethernet; the FPGA module 3 transmits pixel data, line field synchronous data, odd-even field data and pixel clock data of the image to the DM368 core board, and the DM368 core board transmits the data to a specified position through a network port after H.264 compression.
The camera 9 captures image data and transmits it to the video decoding module 1. In one embodiment of the present invention, the camera 9 employs a CCIR or PAL system camera.
The time code generator 10 transmits the time code data to the time code conversion module 2. The time code generator 10 uses a B time code generator of the B time code interface terminal general specification (GJB 2991A-2008). In one embodiment of the present invention, the timecode generator 10 is an IRIG-B timecode generator.
In summary, the present invention provides a multifunctional image capturing device applied to a CPCI computer. The invention integrates the chips such as FPGA, SDRAM, PCI and DSP, realizes the stable and reliable acquisition of image and time code data in real time, has high-efficiency real-time data processing capability, and simultaneously realizes the continuous caching of related data during data transmission; the invention can not only collect images through the CPCI bus, but also transmit the images through the network port, and can analyze the direct current B time code generated by the GPS or the Beidou system.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and should not be taken as limiting the invention. Variations, modifications, substitutions and alterations of the above-described embodiments may be made by those of ordinary skill in the art without departing from the scope of the present invention.
The above embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the claims of the present invention.

Claims (5)

1. A multifunctional image acquisition device applied to a CPCI computer is characterized by comprising: the device comprises a video decoding module (1) for transmitting and converting images, a time code conversion module (2) for transmitting and converting time codes, an FPGA module (3) for enhancing the images and processing the time codes, a first SDRAM module (4) and a second SDRAM module (5) for caching data related to the time codes and the images, a DSP module (6) for reducing the calculation amount of a CPCI computer (11) and calculating a target position in real time according to the images, and a PCI module (8) for connecting the CPCI computer (11);
the video decoding module (1) is connected between a camera (9) and the FPGA module (3);
the time code conversion module (2) is connected between the time code generator (10) and the FPGA module (3);
the first SDRAM module (4), the second SDRAM module (5) and the DSP module (6) are respectively connected with the FPGA module (3);
the PCI module (8) is connected between the FPGA module (3) and the CPCI computer (11).
2. The multi-function image capturing apparatus for CPCI computer as claimed in claim 1, wherein said multi-function image capturing apparatus for CPCI computer further comprises a portal video output module (7) for transmitting data.
3. A multi-functional image capturing apparatus applied to a CPCI computer as claimed in claim 1, wherein the image decoded by the video decoding module (1) is YUV image; the video decoding module (1) calculates pixel data, pixel clock data, line field synchronous data and odd-even field data of the image according to the image and transmits the pixel data, the pixel clock data, the line field synchronous data and the odd-even field data to the FPGA module (3).
4. The multifunctional image capturing device for a CPCI computer as claimed in claim 1, wherein the time code conversion module (2) converts the differential signal of the time code into a path of B-code signal with TTL level to obtain high and low level data, and the time code conversion module (2) transmits the high and low level data to the FPGA module (3).
5. A multifunctional image capturing device applied to a CPCI computer as claimed in claim 2, wherein said portal video output module (7) is connected to said FPGA module (3); and the network port video output module (7) regenerates an image according to the pixel data, the pixel clock data, the line field synchronous data and the odd-even field data, compresses the image and outputs the compressed image through the Ethernet.
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Application publication date: 20211029