CN113572687B - High-order router self-adaptive parallel starting method based on event-driven mechanism - Google Patents
High-order router self-adaptive parallel starting method based on event-driven mechanism Download PDFInfo
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- H04L45/00—Routing or path finding of packets in data switching networks
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Abstract
The invention discloses a self-adaptive parallel starting method of a high-order router based on an event-driven mechanism, which comprises the steps of dividing the high-order router based on the scale of a network system to obtain a plurality of routing chip sets; setting an event-driven detection flow and monitoring each routing chip set respectively; when at least one routing chipset occurs a trigger event, controlling the routing chipset to execute the event-driven detection process based on the trigger event. The invention realizes that the event-driven process is adopted to control the adaptive parallel start of the multi-path routing chipset after the high-order router is divided, realizes the parallel management of the ultra-large-scale routing chipset and ensures the high-efficiency self-start of the high-order router.
Description
Technical Field
The application relates to the technical field of computer application software design, in particular to a high-order router self-adaptive parallel starting method based on an event-driven mechanism.
Background
As high performance network systems grow larger, they also present higher challenges for efficient management of higher-order routers.
The router is started manually in a conventional starting mode, namely a 'console + distributed service' multi-to-multi two-stage starting management model, the console sends a plurality of groups of starting commands to the distributed service, and the distributed service correspondingly starts a plurality of groups of service threads after receiving the plurality of groups of management commands of the console to realize parallel initialization control on bottom equipment through hardware multi-channels; in addition, a one-to-many three-level starting management model of 'console + intermediate agent + distributed services' is provided, the console only needs to send a group of starting commands to the intermediate agent, the intermediate agent can be connected with a plurality of distributed services, and each distributed server receives a group of management commands of the intermediate agent and then starts a plurality of groups of service threads to realize parallel initialization control on bottom equipment.
The first mode belongs to a many-to-many network layer and service layer tightly coupled design, is suitable for small-scale systems, and is limited by the number of subscriber lines of a control console in the starting efficiency and the parallel starting capability of each level of router when the scale is increased; although the second mode has enhanced scalability and improved parallelism, as the scale increases, the link check and repair also consumes more thread resources, and the parallel start performance of the system decreases accordingly.
In summary, the conventional method is difficult to meet the requirement of high-order routers in a high-performance network system to realize efficient startup.
Disclosure of Invention
In order to solve the above problem, an embodiment of the present application provides a high-order router adaptive parallel start method based on an event-driven mechanism.
In a first aspect, an embodiment of the present application provides a method for adaptive parallel startup of a high-order router based on an event-driven mechanism, where the method includes:
dividing a high-order router based on the scale of a network system to obtain a plurality of routing chip sets;
setting an event-driven detection flow and monitoring each routing chip set respectively;
when at least one routing chipset occurs a trigger event, controlling the routing chipset to execute the event-driven detection process based on the trigger event.
Preferably, when there is at least one routing chipset having a trigger event, controlling the routing chipset to execute the event-driven detection procedure based on the trigger event, includes:
when at least one routing chipset occurs a trigger event, analyzing the trigger event;
when the analysis result represents that the routing chipset is switched from an online power-off state to a power-on state, checking whether the routing chipset is locked;
when the routing chipset is locked, controlling the routing chipset to enter an initial state;
and locking the routing chipset when the routing chipset is not locked.
Preferably, after the locking the routing chipset, the method further includes:
checking whether the routing chipset has entered an initial state;
and when the routing chipset does not enter the initial state, controlling the routing chipset to enter the on-state and carrying out initialization training on the routing chipset.
Preferably, after the controlling the routing chipset to enter the on-state and performing the initialization training on the routing chipset, the method further includes:
judging an initialization training result;
when the initialization training result represents that initialization fails, unlocking the routing chipset and controlling the routing chipset to enter a sleep state;
and when the initialization training result represents that the initialization is successful, controlling the routing chip set to enter a query state and checking the link state.
Preferably, after the checking the link status, the method further includes:
when the link state is normal, unlocking the routing chipset and controlling the routing chipset to enter a sleep state;
when the link state is abnormal, controlling the routing chip set to enter a link repair state and carrying out cycle detection on the link;
and after at least one cycle detection and repair process is completed, unlocking the routing chipset and controlling the routing chipset to enter a sleep state.
In a second aspect, an embodiment of the present application provides a high-order router adaptive parallel start apparatus based on an event-driven mechanism, where the apparatus includes:
the dividing module is used for dividing the high-order router based on the scale of the network system to obtain a plurality of routing chip sets;
the setting module is used for setting an event-driven detection process and respectively monitoring each routing chipset;
and the execution module is used for controlling the routing chipset to execute the event-driven detection process based on the trigger event when at least one routing chipset has the trigger event.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor executes the computer program to implement the steps of the method as provided in the first aspect or any one of the possible implementation manners of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method as provided in the first aspect or any one of the possible implementations of the first aspect.
The invention has the beneficial effects that: after the high-order router is divided, the event-driven process is adopted to control the adaptive parallel start of the multi-path routing chipset, so that the parallel management of the super-large-scale routing chipset is realized, and the high-efficiency self-start of the high-order router is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of a high-order router adaptive parallel start method based on an event-driven mechanism according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a high-order router adaptive parallel start apparatus based on an event-driven mechanism according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the following description, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The following description provides embodiments of the present application, which may be combined or interchanged with one another, and therefore the present application is also to be construed as encompassing all possible combinations of the same and/or different embodiments described. Thus, if one embodiment includes the feature A, B, C and another embodiment includes the feature B, D, then this application should also be considered to include embodiments that include all other possible combinations of one or more of A, B, C, D, although this embodiment may not be explicitly recited in text below.
The following description provides examples, and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements described without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.
Referring to fig. 1, fig. 1 is a schematic flowchart of a method for adaptively starting a higher-order router in parallel based on an event-driven mechanism according to an embodiment of the present application. In an embodiment of the present application, the method includes:
s101, dividing a high-order router based on the scale of a network system to obtain a plurality of routing chip sets.
The execution subject of the present application may be a controller.
The high-order router can be understood as a router with a higher order and a more complex structure in the embodiment of the application.
In the embodiment of the present application, in order to enable startup management of a high-order router in a high-performance network system, a console is not used as a terminal for performing total control on all data, but a distributed manner is adopted, the high-order router is divided according to the scale of the network system and divided into a plurality of routing chip sets, and each routing chip set performs a corresponding startup management process in a distributed manner.
And S102, setting an event-driven detection flow, and monitoring each routing chip set respectively.
In this embodiment of the present application, in order to enable each routing chipset to perform independent startup management, a set of event-driven detection flows is set, that is, after some initial information data triggering the event-driven detection flow is detected, a process of gradually performing detection operations based on the set event-driven detection flow is performed. After the event-driven detection process is set, each routing chipset is monitored respectively, so that independent and autonomous detection and execution processes of each routing chipset are realized.
S103, when at least one routing chipset has a trigger event, controlling the routing chipset to execute the event-driven detection process based on the trigger event.
The trigger event may be understood as an initial event capable of triggering the event-driven detection procedure to start in the embodiment of the present application.
In the embodiment of the present application, since multiple routing chipsets may generate trigger events at the same time, when at least one routing chipset generates a trigger event, the routing chipset is controlled to perform a corresponding detection procedure in an event-driven detection procedure based on the generated trigger event. In particular, the triggering event may be an offline, online, power-up, power-down, link degradation, or the like event.
In one possible embodiment, step S103 includes:
when at least one routing chipset occurs a trigger event, analyzing the trigger event;
when the analysis result represents that the routing chipset is switched from an online power-off state to a power-on state, checking whether the routing chipset is locked;
when the routing chipset is locked, controlling the routing chipset to enter an initial state;
and locking the routing chipset when the routing chipset is not locked.
In the embodiment of the present application, since the starting detection processes performed by different trigger events in the event-driven detection process may be different, when a trigger event occurs, the trigger event is first analyzed to determine the specific type of the trigger event. When the analysis result represents that the routing chipset changes from the online power-off state to the power-on state, namely the user is indicated to plug and replace the plug-in after powering off the high-order router, and power up of hardware is carried out again, so that the system represents that a new plug-in is powered up, and at this time, an event-driven detection process is triggered to carry out an initialization step. Specifically, it is first detected whether a corresponding routing chipset is locked, and for the router hardware that is just started, in order to protect information security, the router hardware needs to be locked before the user does not perform the next operation command. When the routing chipset is detected to be switched from the on-line power-off state to the power-on state, whether the routing chipset is locked or not is checked, and for the equipment which is in the locked state, the equipment is controlled to enter an initial state to wait for subsequent operation of a user; for the device without locking, the device will be automatically controlled to lock.
In one embodiment, after locking the routing chipset, the method further includes:
checking whether the routing chipset has entered an initial state;
and when the routing chipset does not enter the initial state, controlling the routing chipset to enter the on-state and carrying out initialization training on the routing chipset.
In the embodiment of the present application, after a device that is not locked is locked, it is also checked whether the device, that is, the routing chipset, is initialized, that is, the device has entered an initial state. For the equipment which is not in the initial state, the equipment is controlled to enter the starting state, namely the working state, so as to carry out initial training on the equipment. The initial training mode can be trained through a weight initialized neural network model.
In one embodiment, after the controlling the routing chipset to enter the on-state and performing the initialization training on the routing chipset, the method further includes:
judging an initialization training result;
when the initialization training result represents that initialization fails, unlocking the routing chipset and controlling the routing chipset to enter a sleep state;
and when the initialization training result represents that the initialization is successful, controlling the routing chip set to enter a query state and checking the link state.
In the embodiment of the application, after the initialization training is finished, the initialization training result is judged, if the judgment result is failure, the initialization cannot be carried out, and the equipment possibly cannot carry out subsequent normal work, so that the equipment is directly unlocked and enters a sleep state, the equipment cannot work at present, and the subsequent processing of a user is waited. If the judgment result is successful, the equipment is initialized, the equipment state is switched to the query state, and whether the link state is abnormal is checked.
In one embodiment, after the checking the link status, the method further includes:
when the link state is normal, unlocking the routing chipset and controlling the routing chipset to enter a sleep state;
when the link state is abnormal, controlling the routing chipset to enter a link repair state and performing cycle detection on the link;
and after at least one cycle detection and repair process is finished, unlocking the routing chip set and controlling the routing chip set to enter a sleep state.
In the embodiment of the application, for the device with a normal link state, the device is unlocked and controlled to enter the sleep state. For the equipment with abnormal link state, the link degradation controls the equipment to enter a link repairing state to carry out circular detection, and the detected problem is repaired in the circular detection process. Generally, the cyclic detection process is performed three times, and after at least one cyclic detection repairing process is completed, the device is controlled to be unlocked and enter a sleep state. It should be noted that, although the device in the initialization training process is finally unlocked and enters the sleep state no matter whether there is a problem or not, the present application aims to implement the self-starting of the complex high-order router, so as to improve the deployment efficiency of the network system, that is, the routing chipset is distributed to perform an autonomous processing flow according to the event-driven detection flow, so that after the abnormality determination and repair process is completed, the device directly enters the sleep state to wait for subsequent operations in order to improve the deployment efficiency. Although the above process finally enters the sleep state, when the subsequent corresponding device is started again, only the device in the normal state can finally enter the initial state, and the device in the abnormal state still finally enters the sleep state in the event driven detection process.
The following describes in detail a high-order router adaptive parallel start apparatus based on an event-driven mechanism according to an embodiment of the present application with reference to fig. 2. It should be noted that, the higher-order router adaptive parallel start apparatus based on the event-driven mechanism shown in fig. 2 is used for executing the method of the embodiment shown in fig. 1 of the present application, and for convenience of description, only the portion related to the embodiment of the present application is shown, and details of the specific technology are not disclosed, please refer to the embodiment shown in fig. 1 of the present application.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a high-order router adaptive parallel start apparatus based on an event-driven mechanism according to an embodiment of the present disclosure. As shown in fig. 2, the apparatus includes:
the dividing module 201 is configured to divide a high-order router based on a network system scale to obtain a plurality of routing chipsets;
a setting module 202, configured to set an event-driven detection procedure, and monitor each routing chipset respectively;
the execution module 203 is configured to, when there is at least one routing chipset having a trigger event, control the routing chipset to execute the event-driven detection procedure based on the trigger event.
In one possible implementation, the execution module 203 includes:
the first analysis unit is used for analyzing the trigger event when at least one routing chipset occurs to the trigger event;
the first characterization unit is used for checking whether the routing chipset is locked or not when the analysis result characterizes that the routing chipset is switched from an online power-off state to a power-on state;
the locking processing unit is used for controlling the routing chipset to enter an initial state when the routing chipset is locked;
and the unlocking processing unit is used for locking the routing chipset when the routing chipset is unlocked.
In one embodiment, the executing module 203 further comprises:
a first checking unit for checking whether the routing chipset has entered an initial state;
the first initialization unit is used for controlling the routing chipset to enter an on state and carrying out initialization training on the routing chipset when the routing chipset does not enter an initial state.
In one embodiment, the executing module 203 further comprises:
the first judging unit is used for judging an initialization training result;
the first processing unit is used for unlocking the routing chipset and controlling the routing chipset to enter a sleep state when the initialization training result represents initialization failure;
and the second processing unit is used for controlling the routing chip set to enter a query state and checking the link state when the initialization training result represents that the initialization is successful.
In one embodiment, the executing module 203 further comprises:
the third processing unit is used for unlocking the routing chipset and controlling the routing chipset to enter a sleep state when the link state is normal;
the fourth processing unit is used for controlling the routing chipset to enter a link repair state and performing cycle detection on the link when the link state is abnormal;
and the fifth processing unit is used for unlocking the routing chipset and controlling the routing chipset to enter a sleep state after at least one cycle detection and repair process is completed.
It is clear to a person skilled in the art that the solution according to the embodiments of the present application can be implemented by means of software and/or hardware. The "unit" and "module" in this specification refer to software and/or hardware that can perform a specific function independently or in cooperation with other components, where the hardware may be, for example, a Field-Programmable Gate Array (FPGA), an Integrated Circuit (IC), or the like.
Each processing unit and/or module in the embodiments of the present application may be implemented by an analog circuit that implements the functions described in the embodiments of the present application, or may be implemented by software that executes the functions described in the embodiments of the present application.
Referring to fig. 3, a schematic structural diagram of an electronic device according to an embodiment of the present application is shown, where the electronic device may be used to implement the method in the embodiment shown in fig. 1. As shown in fig. 3, the electronic device 300 may include: at least one central processor 301, at least one network interface 304, a user interface 303, a memory 305, at least one communication bus 302.
Wherein a communication bus 302 is used to enable the connection communication between these components.
The user interface 303 may include a Display screen (Display) and a Camera (Camera), and the optional user interface 303 may further include a standard wired interface and a wireless interface.
The network interface 304 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.
The central processor 301 may include one or more processing cores. The central processor 301 connects various parts within the entire electronic device 300 using various interfaces and lines, and performs various functions of the terminal 300 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 305 and calling data stored in the memory 305. Alternatively, the central Processing unit 301 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The CPU 301 may integrate one or a combination of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is to be understood that the modem may not be integrated into the cpu 301, and may be implemented by a single chip.
The Memory 305 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 305 includes a non-transitory computer-readable medium. The memory 305 may be used to store instructions, programs, code sets, or instruction sets. The memory 305 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 305 may alternatively be at least one storage device located remotely from the central processor 301. As shown in fig. 3, memory 305, which is a type of computer storage medium, may include an operating system, a network communication module, a user interface module, and program instructions.
In the electronic device 300 shown in fig. 3, the user interface 303 is mainly used for providing an input interface for a user to obtain data input by the user; the central processing unit 301 may be configured to invoke the higher-order router adaptive parallel boot application based on the event-driven mechanism stored in the memory 305, and specifically perform the following operations:
dividing a high-order router based on the scale of a network system to obtain a plurality of routing chip sets;
setting an event-driven detection flow and monitoring each routing chip set respectively;
when at least one routing chipset occurs a trigger event, controlling the routing chipset to execute the event-driven detection process based on the trigger event.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVD, CD-ROMs, microdrive, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some service interfaces, indirect coupling or communication connection of devices or units, and may be electrical or in other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program, which is stored in a computer-readable memory, and the memory may include: flash disks, read-Only memories (ROMs), random Access Memories (RAMs), magnetic or optical disks, and the like.
The above description is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure should not be limited thereby. That is, all equivalent changes and modifications made in accordance with the teachings of the present disclosure are intended to be included within the scope of the present disclosure. Embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (7)
1. A high-order router self-adaptive parallel starting method based on an event-driven mechanism is characterized by comprising the following steps:
dividing a high-order router based on the scale of a network system to obtain a plurality of routing chip sets;
setting an event-driven detection flow and monitoring each routing chip set respectively;
when at least one routing chipset occurs a trigger event, controlling the routing chipset to execute the event-driven detection process based on the trigger event;
when there is at least one routing chipset having a trigger event, controlling the routing chipset to execute the event-driven detection process based on the trigger event, including:
when at least one routing chipset occurs a trigger event, analyzing the trigger event;
when the analysis result represents that the routing chip set is switched from an on-line power-off state to a power-on state, checking whether the routing chip set is locked or not;
when the routing chipset is locked, controlling the routing chipset to enter an initial state;
and locking the routing chipset when the routing chipset is not locked.
2. The method of claim 1, wherein after locking the routing chipset, further comprising:
checking whether the routing chipset has entered an initial state;
and when the routing chipset does not enter the initial state, controlling the routing chipset to enter the on-state and carrying out initialization training on the routing chipset.
3. The method of claim 2, wherein after the controlling the routing chipset to enter an on state and performing initialization training on the routing chipset, further comprising:
judging an initialization training result;
when the initialization training result represents that initialization fails, unlocking the routing chipset and controlling the routing chipset to enter a sleep state;
and when the initialization training result represents that the initialization is successful, controlling the routing chip set to enter a query state and checking the link state.
4. The method of claim 3, wherein after checking the link status, further comprising:
when the link state is normal, unlocking the routing chipset and controlling the routing chipset to enter a sleep state;
when the link state is abnormal, controlling the routing chipset to enter a link repair state and performing cycle detection on the link;
and after at least one cycle detection and repair process is completed, unlocking the routing chipset and controlling the routing chipset to enter a sleep state.
5. An adaptive parallel boot apparatus for a higher-order router based on an event-driven mechanism, the apparatus comprising:
the dividing module is used for dividing the high-order router based on the scale of the network system to obtain a plurality of routing chip sets;
the setting module is used for setting an event-driven detection process and respectively monitoring each routing chipset;
the execution module is used for controlling the routing chipset to execute the event-driven detection process based on the trigger event when at least one routing chipset has the trigger event;
the execution module comprises:
the first analysis unit is used for analyzing the trigger event when at least one routing chip set generates the trigger event;
the first characterization unit is used for checking whether the routing chipset is locked or not when the analysis result characterizes that the routing chipset is switched from an online power-off state to a power-on state;
the locking processing unit is used for controlling the routing chipset to enter an initial state when the routing chipset is locked;
and the unlocking processing unit is used for locking the routing chipset when the routing chipset is unlocked.
6. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 1-4 are implemented when the computer program is executed by the processor.
7. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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