CN113571544A - High-integration phase change memory array structure - Google Patents
High-integration phase change memory array structure Download PDFInfo
- Publication number
- CN113571544A CN113571544A CN202110779718.5A CN202110779718A CN113571544A CN 113571544 A CN113571544 A CN 113571544A CN 202110779718 A CN202110779718 A CN 202110779718A CN 113571544 A CN113571544 A CN 113571544A
- Authority
- CN
- China
- Prior art keywords
- phase change
- layer
- core
- gate electrode
- array structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008859 change Effects 0.000 title claims abstract description 64
- 239000012782 phase change material Substances 0.000 claims abstract description 86
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 239000004065 semiconductor Substances 0.000 claims description 49
- 210000000988 bone and bone Anatomy 0.000 claims description 11
- 230000010354 integration Effects 0.000 abstract description 15
- 238000003860 storage Methods 0.000 abstract description 7
- 229920005591 polysilicon Polymers 0.000 description 35
- 238000009826 distribution Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 239000007772 electrode material Substances 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000009413 insulation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention belongs to the technical field of storage equipment, and particularly relates to a high-integration-level phase change memory array structure which comprises units; the unit comprises a core bar, wherein a phase change material layer, a channel layer, a polycrystalline silicon layer and a gate electrode are sequentially arranged outwards on two opposite surfaces or four circumferential surfaces of the core bar; the plurality of units are stacked into an n multiplied by n array structure through three-dimensional stacking, and n units stacked mutually in the height direction form a memory chain; the unit at the bottom end of the memory chain is connected with the gating circuit; the gating circuit comprises a core bar, wherein channel layers, a polycrystalline silicon layer and a gate electrode are sequentially arranged on two opposite surfaces or the outer side of the circumferential wall surface of the core bar; the core bar, the channel layer and the polycrystalline silicon layer of the gating circuit are formed by downwards extending units at the bottom end of the memory chain along the height direction of the memory chain; the gate electrode of the gating circuit has the same structure as the gate electrode of the corresponding unit. The invention can realize high integration level, and meanwhile, the invention does not have obvious sensible heat crosstalk, thereby ensuring the reliability of the storage device.
Description
Technical Field
The invention belongs to the technical field of storage equipment, and particularly relates to a high-integration-level phase change memory array structure.
Background
With the rapid development of the internet and internet of things industries, the amount of information to be stored and processed by a computer is increasing, and people demand high-performance and large-capacity storage devices. The following mainstream storage devices are basically divided into two categories: the volatile memory and the nonvolatile memory are distinguished according to whether the information can be stored after power failure. Phase Change Memory (PCM) is an emerging non-volatile Memory that stores data that does not disappear after power is lost. In addition, the phase change memory has the advantages of high integration level, low static power consumption, byte addressing and the like, and therefore, the phase change memory is receiving attention in practical application and is considered to be one of storage media most likely to replace the DRAM.
For many years, researchers have proposed a variety of different PCM structures, such as mushroom-shaped structures, vertical electrode structures, and the like, with the most widely accepted mushroom-shaped cells. The most basic PCM cell is made up of upper and lower electrodes and a thin layer of GST and heating filament between the electrodes, the GST material and heating filament making up the body portion of the cell. The mushroom structure is mainly characterized in that it has a simple structure, and the heater is in direct contact with the phase change material, which contributes to minimizing heat loss. However, the disadvantage is that each cell has only one area of phase change material and is relatively large, so that if a large number of data are to be stored, a large-scale array is required, and the size of the array is also very large, which limits the development of the integration level. And when the array works, the thermal crosstalk problem is serious, so that the reliability of the memory is reduced. According to the 3D XPoint architecture, the typical stacked structure of the PCM array can be divided into a common word line and a common bit line, and if the stacked structure is a vertical electrode, the stacked structure also has a crossed electrode array structure.
To phase-change a PCM cell requires a large input current to accomplish active region heating by self-heating. In the process of writing, the GST region temperature will reach the melting point, and in the memory array with the increasing integration density, the temperature of one region will increase due to thermal diffusion, and if the situation is serious, the adjacent cells may have phase change, which causes information error, and the performance and reliability of the memory device and the adjacent devices are reduced.
In summary, the invention provides a high-integration phase change memory array structure, and electrical characteristics of a PCM unit and an array in a phase change process are researched through an independently developed electric-thermal coupling simulator based on a time domain finite element method and a region decomposition method.
Disclosure of Invention
The present invention is directed to solve the above problems and to provide a phase change memory array structure with high integration.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
a high integration phase change memory array structure comprising cells; the unit comprises a core bar, wherein phase change material layers, a channel layer, a polycrystalline silicon layer and a gate electrode are sequentially arranged on two opposite surfaces or four circumferential surfaces of the core bar; the plurality of units are stacked into an n multiplied by n array structure through three-dimensional stacking, and n units stacked mutually in the height direction form a memory chain; the unit at the bottom end of the memory chain is connected with the gating circuit; the gating circuit comprises a core bar, and a channel layer, a polycrystalline silicon layer and a gate electrode are sequentially arranged outside the core bar; the core bar, the channel layer and the polycrystalline silicon layer of the gating circuit are formed by downwards extending units at the bottom end of the memory chain along the height direction of the memory chain; the gate electrode of the gating circuit has the same structure as the gate electrode of the corresponding unit. The device also comprises a diode gate, a bit line, an electrode and a word line; the bottom end of the gating circuit is connected with a diode gating device, and the diode gating device is connected with a word line; the channel layer of the top cell of the memory chain is connected with an electrode, and the electrode is connected with a bit line.
Further, the thickness of the core bar of the gating circuit is the sum of the thickness of the core bar of the corresponding unit and the thickness of the phase change material layer.
Furthermore, the heights of the phase change material layer, the channel layer and the polycrystalline silicon layer are equal to the height of the core bone, and the gate electrode is located in the middle of the height of the polycrystalline silicon layer.
Furthermore, the gate electrodes on the four circumferential sides of the core frame are surrounded into a circumferential shape.
Furthermore, the core bone, the phase change material layer, the channel layer, the polysilicon layer and the gate electrode are all cuboid.
Furthermore, the core bone, the channel layer, the polysilicon layer and the gate electrode are all cuboid; the phase change material layer is dumbbell-shaped with the middle part smaller than the two ends.
Further, several cells are stacked in three dimensions into a 3 × 3 × 3 array structure.
Furthermore, the diode gate comprises a first doped semiconductor, a second doped semiconductor and a third doped semiconductor which are mutually overlapped in the height direction, the structures and the sizes of the first doped semiconductor, the second doped semiconductor and the third doped semiconductor are the same, the first doped semiconductor is connected with the bottom end of the memory chain, and the third doped semiconductor is connected with the word line.
Further, the bit lines and the word lines are each rectangular parallelepiped.
Compared with the prior art, the invention has the beneficial technical effects that:
the invention can realize high integration level, and meanwhile, the invention does not have obvious sensible heat crosstalk, thereby ensuring the reliability of the storage device.
Drawings
FIG. 1 is a schematic diagram of a cell in an x-z plane according to an embodiment;
FIG. 2 is a schematic view of a phase change material layer of a stripe-shaped unit in the y-z plane according to the first embodiment;
FIG. 3 is a schematic diagram of the dumbbell-shaped unit of the first embodiment in the y-z plane, showing the relative positions of the phase change material layer and the core;
FIG. 4 is the modeling of FIG. 1 in COMSOL;
FIG. 5 is a schematic diagram of the modeled structure of FIG. 2 in COMSOL;
FIG. 6 is a schematic diagram of the modeled structure of FIG. 3 in COMSOL;
FIG. 7 is a schematic plan view of a phase change memory array in a first embodiment, showing the structure in the x-z direction;
FIG. 8 is a schematic plan view of a phase change memory array in the first embodiment;
FIG. 9 is a plan view of a phase change memory array in the first embodiment;
FIG. 10 is a schematic diagram illustrating operation of one memory chain in a phase change memory array according to one embodiment;
FIG. 11 is a comparison of the integration level of the phase change memory array and the reference cell in the first embodiment;
FIG. 12 is a temperature distribution graph along the z-axis of a memory chain with phase change cells on a cross section of a phase change material layer where phase change occurs in a phase change memory array according to one embodiment;
FIG. 13 is a graph showing the temperature distribution along the y-axis in the cross-section of the phase change material layer undergoing phase change at the center height in the phase change memory array comprising stripe-shaped cells according to the first embodiment;
FIG. 14 is a graph showing the temperature distribution along the y-axis direction at the center height of the cross-section of the phase-change material layer undergoing phase change in a phase-change memory array composed of dumbbell-shaped cells according to the first embodiment;
FIG. 15 is a schematic structural view of a second unit according to an embodiment in the x-z plane;
FIG. 16 is a schematic view of the phase change material layer of the stripe-shaped cells of the second embodiment in the y-z plane;
FIG. 17 is a schematic diagram of the dumbbell-shaped unit of the second embodiment in the y-z plane, showing the relative positions of the phase change material layer and the core;
FIG. 18 is the modeling of FIG. 15 in COMSOL;
FIG. 19 is a schematic diagram of the modeled structure of FIG. 16 in COMSOL;
FIG. 20 is a schematic diagram of the modeled structure of FIG. 17 in COMSOL;
FIG. 21 is a plan view showing the structure of the phase change memory array according to the second embodiment in the x-z direction;
FIG. 22 is a plan view showing the structure of the phase change memory array according to the second embodiment in the x-y direction;
FIG. 23 is a plan view showing the structure of the phase change memory array according to the second embodiment in the y-z direction;
FIG. 24 is a schematic diagram illustrating operation of one memory chain in the phase change memory array according to the second embodiment;
FIG. 25 is a comparison of the integration level of the phase change memory array and the reference cell in the second embodiment;
FIG. 26 is a temperature distribution graph along the z-axis of a memory chain of phase change cells in a cross section of a phase change material layer in the phase change memory array according to the second embodiment;
FIG. 27 is a graph showing the temperature distribution along the y-axis direction at the center height in the cross section of the phase change material layer in the phase change memory array comprising stripe-shaped cells according to the second embodiment;
FIG. 28 is a graph showing the temperature distribution along the y-axis direction at the center height of the cross-section of the phase-change material layer undergoing phase change in the phase-change memory array composed of dumbbell-shaped cells according to the second embodiment.
In the figure, a gate electrode 1, a polysilicon layer 2, a channel layer 3, a phase change material layer 4, a core bone 5, a bit line 6-1, an electrode 6-2, a word line 7, a thermal insulating layer 8, a diode gate 9, a first doped semiconductor 9-1, a second doped semiconductor 9-2 and a third doped semiconductor 9-3.
Detailed Description
The invention will be further described with reference to specific examples, but the scope of the invention is not limited thereto.
Example one
As shown in fig. 1 and fig. 7-9, the present embodiment provides a highly integrated phase change memory array structure, which includes a cell; the unit comprises a core rod 5, wherein a phase change material layer 4, a channel layer 3, a polycrystalline silicon layer 2 and a gate electrode 1 are sequentially arranged outside two opposite surfaces of the core rod 5. In the unit, the phase change material layer 4, the channel layer 3, the polysilicon layer 2, and the gate electrode 1 are distributed on two sides of the core bar 5 in a mirror image manner to form a dual-unit structure, wherein the phase change material layer 4 is a phase change region of the present embodiment. A plurality of units are stacked in three dimensions to form an n × n × n array structure, and n units stacked on each other in the height direction form a memory chain. The embodiment also comprises a gating circuit, and the unit at the bottom end of the memory chain is connected with the gating circuit. The gating circuit comprises a core rod 5, and a channel layer 3, a polycrystalline silicon layer 2 and a gate electrode 1 are sequentially arranged outside two opposite surfaces of the core rod 5. The core bar, the channel layer and the polycrystalline silicon layer of the gating circuit are formed by downwards extending units at the bottom end of the memory chain along the height direction of the memory chain; the gate electrode of the gating circuit has the same structure as the gate electrode of the corresponding unit.
The present embodiment further includes a diode gate 9, a bit line 6-1, an electrode 6-2, and a word line 7. The bottom end of the gating circuit is connected with a diode gate 9, and the diode gate 9 is connected with a word line 7; the channel layer 3 at the top cell of the memory chain is connected to electrode 6-2 and electrode 6-2 is connected to bit line 6-1. The core bar 5, the channel layer 3, the polysilicon layer 2 and the gate electrode 1 are all rectangular.
The longitudinal direction along which the cuboid of the core 5 is located is the x-direction, the width direction is the y-direction, and the height direction is the z-direction. The phase-change material layer 4, the channel layer 3, the polysilicon layer 2 and the gate electrode 1 are all covered on the plane where the width and the height of the core 5 are located, namely, the y-z plane of the core 5 is located. The outer side of the phase-change material layer 4 is sequentially covered with the channel layer 3 and the polysilicon layer 2, and the polysilicon layer 2 is attached to the gate electrode 1. The thickness directions of the phase-change material layer 4, the channel layer 3, the polycrystalline silicon layer 2 and the gate electrode 1 are all along the x direction, the thickness of the phase-change material layer 4 is 2nm, the thickness of the channel layer 3 is 7.5nm, and the thickness of the polycrystalline silicon layer 2 is 4 nm. As shown in fig. 2 and 3, the cells are divided into strip-shaped cells and dumbbell-shaped cells. The length directions of the phase change material layer 4, the channel layer 3, the polycrystalline silicon layer 2 and the gate electrode 1 of the strip-shaped unit are all along the y direction and are equal to the width of the core bone 5; the heights of the phase-change material layer 4, the channel layer 3 and the polycrystalline silicon layer 2 are all equal to the height of the core bone 5 along the z direction, namely the outer edges of the phase-change material layer 4, the channel layer 3 and the polycrystalline silicon layer 2 are all flush with the outer edge of the y-z side face of the core bone 5; the height of the gate electrode 1 is along the z-direction and less than the height of the core 5. In the unit, the height of the gate electrode 1 is 25nm, and the gate electrode 1 is positioned in the middle of the height of the polysilicon layer 2. The dumbbell-shaped unit is different from the strip-shaped unit in that the phase-change material layer of the dumbbell-shaped unit is dumbbell-shaped, the size of the middle part of the phase-change material layer is smaller than that of the two ends of the phase-change material layer, and the narrowed middle part of the phase-change material layer is a part which is correspondingly covered with the electrode; the narrowed middle portion of the phase change material layer becomes smaller in size along the y-axis, and the remaining portion has the same size along the y-axis as the width of the core bar along the y-axis.
The thickness of the core 5 of the gating circuit is along the x-axis direction and is the sum of the thickness of the core 5 of the corresponding unit along the x-axis direction and the thickness of the phase change material layer 4. The width of the core 5 of the gate is in the y-direction, the same as the width of the core 5 of its corresponding cell. The distance between adjacent memory chains in the array in the x-axis direction is the sum of the thicknesses of the gate electrodes 1 of two adjacent memory units, and the distance in the y-axis direction is the sum of the widths of the gate electrodes 1 extending out of the width of the core bar 5 between the adjacent units. The gate electrode 1 of the gate circuit abuts against the polysilicon layer 2 of the gate circuit. The gating circuit is provided with a plurality of gate electrodes in the height direction, the distance between the gate electrode closest to the bottom of the memory chain and the bottom of the memory chain is 15nm, and the distance between the gate electrode closest to the top of the diode gate and the top of the diode gate is 15 nm.
The bit line 6-1 has a rectangular parallelepiped shape. The bit line 6-1 has a length along the x-axis, a width along the y-axis, and a height along the z-axis. The length of the bit line 6-1 is equal to the sum of the thickness of the core 5 of the unit below the bit line along the x direction, the thickness of the phase change material on two sides of the core 5 and the thickness of the channel layer on two sides of the core 5. The width of the bit line 6-1 is equal to the length of the gate electrode 1 in the y-axis direction.
The word lines 7 are rectangular parallelepiped, and have a longitudinal direction along the x-axis direction, a width direction along the y-axis direction, and a height direction along the z-axis direction. The length of the word line 7 is the sum of the thickness of the core 5, the thickness of the phase-change material on two sides of the core 5, the thickness of the channel layer on two sides of the core 5, the thickness of the polysilicon layer 2 on two sides of the core 5, and the thickness of the gate electrode on two sides of the core 5 along the x direction of the unit. The width of the word line 7 is equal to the length dimension of the core 5 along the y-axis.
The core 5, GST, channel, electrode 6-2, gate oxide material used in the array are the same as the cells, the diode gating device uses polysilicon, and the selector circuit is also a MOS structure composed of gate electrode 1, gate oxide, polysilicon channel. The array is filled with dielectric material SiO2 around it, with SiN encapsulation on the top and bottom.
The diode gate 9 includes a first doped semiconductor 9-1, a second doped semiconductor 9-2 and a third doped semiconductor 9-3 which are stacked on each other in a height direction, and the first doped semiconductor 9-1, the second doped semiconductor 9-2 and the third doped semiconductor 9-3 are all rectangular parallelepiped and have the same size. Taking the first doped semiconductor 9-1 as an example, the length direction of the first doped semiconductor 9-1 is along the x-axis direction, the width direction is along the y-direction, and the height direction is along the z-direction, the length of the first doped semiconductor 9-1 is the sum of the thickness of the mandrel 5, the thickness of the channel layer on both sides of the mandrel 5, and the thickness of the polysilicon layer 2 on both sides of the mandrel 5, of which the upper end selection circuit is along the x-axis direction. The width of the first doped semiconductor 9-1 is equal to the width dimension of the core 5 along the y-axis. The first doped semiconductor 9-1 is connected to the bottom of the memory chain and the third doped semiconductor 9-3 is connected to the word line 7. The bit line 6-1 is a metal electrode material, and the word line 7 is a metal electrode material.
As shown in fig. 4-6, the unit of this embodiment is modeled by using COMSOL before simulation, a thermal insulation layer 8 with a thickness of 2nm is arranged between the core 5 and the phase change material layer 4 and between the phase change material layer 4 and the channel layer 3 during modeling, the thermal insulation layer 8 is also arranged around the phase change material layer 4, and the sizes of the core 5, the channel layer 3 and the polysilicon layer 2 are correspondingly increased according to the thermal insulation layer 8. During modeling, dielectric materials are filled around the cell, the top of the cell is provided with a first top cap electrode 6, and the bottom of the cell is provided with a second top cap electrode 7. The first cap electrode 6 includes a bit line 6-1 and an electrode 6-2, and the second cap electrode 7 is a word line 7. In the case of using COMSOL modeling, a 2nm thermal barrier layer 8 was placed between layers and between cells to simulate thermal resistance boundaries.
As shown in fig. 7-9, the phase change memory array structure of the present embodiment includes a memory chain, a gating circuit, a diode gate 9, a word line 7, and a bit line 6-1. The memory chain is formed by vertically stacking the units shown in fig. 1, the gating circuit is composed of a core bar 5, a channel layer 3, a polycrystalline silicon layer 2 and a gate electrode 1, the core bar 5, the channel layer 3 and the polycrystalline silicon layer 2 are all extended from the upper memory chain, and the phase-change material is partially replaced by the core bar 5 material. The diode gate 9 is composed of a first doped semiconductor 9-1, a second doped semiconductor 9-2, and a third doped semiconductor 9-3 using a common fabrication method. The bit line 6-1 on the top is a metal electrode material, and 6-2 is a connection electrode 6-2 of the bit line 6-1 and the channel layer 3. The bottom word line 7 is a metal electrode material. As with the cells, a 2nm insulating layer 8 was placed between the layers and between the cells to simulate the thermal resistance boundary when using COMSOL modeling. The array proposed in this example had a layer spacing of 20nm in the x-axis and 10nm in the y-axis.
In actual operation, as shown in fig. 10, current flows from the top bit line 6-1, may flow through the channel layer 3, the gating circuit and the diode gate 9 to the bottom grounded word line 7. When the gate electrodes 1 on both sides of the cell are controlled to cut off the channel layer 3, the current will flow to the inner phase-change material layer 4, so that the phase-change material layer is heated and changed in phase. The diode gate 9 is used to control the memory chain in the array through which current will flow, the selection circuit is used to determine which cell on both sides of the core 5 the current will flow, and the gate electrode 1 is used to control the channel layer 3 of a certain layer to be turned off, thereby controlling the specific phase change position in the array.
During simulation, a current pulse is applied to the top of the electrode 6-2, and the polysilicon channel 3 under the middle layer gate electrode 1 is set to be in a closed state by setting material parameters, so that current can flow to an internal phase change material area to enable the temperature of the internal phase change material area to rise and generate phase change. The materials used and their parameters are listed in table 1, set in advance in the simulator.
TABLE 1
The simulations were performed in steps with a current pulse duration of 2ns, with a step size of 0.01ns, and the maximum temperature was read at t-1.8 ns (step 180). When the temperature of the GST region is raised to the melting point 873K, the phase-change material is melted into an amorphous state; and otherwise, when the temperature does not reach the melting point, the phase-change material continuously keeps the crystalline state. Kinoshita proposed a vertical electrode array in Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes, 2012.
As shown in fig. 11, compared with the reference array, the integration level of the array structure proposed in this embodiment can reach 2.3 times when the width wch of the phase change region is 24 nm; when the width of the phase change region is 18nm, the width can reach 2.9 times; the width of the phase change region is 12nm, which is 3.7 times of the width of the phase change region.
The temperature distribution around the phase change cells in the array proposed in this embodiment was observed because increased integration due to the changed size may exacerbate thermal crosstalk in the array cells. As shown in fig. 12-13, which show the temperature distribution along the z-axis and y-axis directions of the cross-section of the cell undergoing a phase change, it can be seen that the cells surrounding the cell do not reach a temperature at which the phase change occurs, and there is no significant thermal crosstalk.
When the unit structure is dumbbell-shaped, the height of the phase change material layer 4, the channel layer 3 and the polysilicon layer 2 is equal to the height of the core rod 5,
the phase change material layer is dumbbell-shaped with the middle part smaller than the two ends. The portion of the phase change material layer where the middle size becomes smaller is the portion covered by the gate electrode 1. The narrowed middle portion of the phase change material layer becomes smaller in size along the y-axis, and the remaining portion has the same size along the y-axis as the width of the core bar along the y-axis. As shown in fig. 14, changing the stripe shape in each cell to the dumbbell shape does not affect the integration thereof, but can reduce thermal crosstalk in the y-axis direction.
Example two
As shown in fig. 15 and fig. 21-23, the present embodiment provides a highly integrated phase change memory array structure, which includes a cell; the unit comprises a core rod 5, wherein a phase change material layer 4, a channel layer 3, a polycrystalline silicon layer 2 and a gate electrode 1 are sequentially arranged outside the four circumferential surfaces of the core rod 5. In the unit, the phase change material layer 4, the channel layer 3, the polysilicon layer 2, and the gate electrode 1 are disposed around the core bar 5 to form a four-unit structure, wherein the phase change material layer 4 is a phase change region of this embodiment. A plurality of units are stacked in three dimensions to form an n × n × n array structure, and n units stacked on each other in the height direction form a memory chain. The embodiment also comprises a gating circuit, and the units at the bottom end of the memory chain are all connected with the gating circuit. The gating circuit comprises a core rod 5, and a channel layer 3, a polycrystalline silicon layer 2 and a gate electrode 1 are sequentially arranged outside the four circumferential surfaces.
The core bar, the channel layer and the polycrystalline silicon layer of the gating circuit are formed by downwards extending units at the bottom end of the memory chain along the height direction of the memory chain; the gate electrode of the gating circuit has the same structure as the gate electrode of the corresponding unit.
The present embodiment further includes a diode gate 9, a bit line 6-1, an electrode 6-2, and a word line 7. The bottom end of the gating circuit is connected with a diode gate 9, and the diode gate 9 is connected with a word line 7; the channel layer 3 at the top cell of the memory chain is connected to electrode 6-2 and electrode 6-2 is connected to bit line 6-1. The core bar 5, the channel layer 3, the polysilicon layer 2 and the gate electrode 1 are all rectangular.
The longitudinal direction along which the cuboid of the core 5 is located is the x-direction, the width direction is the y-direction, and the height direction is the z-direction. The outer side of the phase change material layer 4 is sequentially covered with the channel layer 3 and the polysilicon layer 2, and the surface of the polysilicon layer is tightly attached to the gate electrode 1. The phase-change material layer 4, the channel layer 3 and the polysilicon layer 2 are attached to two opposite x-z side surfaces and two opposite y-z side surfaces of the core 5. The thickness of the phase-change material layer 4 is 2nm, the thickness of the channel layer 3 is 7.5nm, and the thickness of the polysilicon layer 2 is 4 nm. The heights of the phase-change material layer 4, the channel layer 3 and the polycrystalline silicon layer 2 are equal to the height of the core bone 5; the height of the gate electrode 1 is less than the height of the core bar 5. In the unit, the height of the gate electrode 1 is 25nm, and the gate electrode 1 is positioned in the middle of the height of the polysilicon layer 2. The four phase change material layers are respectively distributed on four circumferential sides of the core. The four channel layers 3 are respectively distributed on four circumferential sides of the core. Four polysilicon layers 2 are respectively distributed on four circumferential sides of the core. The gate electrodes on the four circumferential sides of the core frame are surrounded into a circumferential shape.
In the present embodiment, a plurality of units are stacked in three dimensions to form a 3 × 3 × 3 array structure. One memory chain of this embodiment is composed of 3 units, which are stacked one above the other and connected by a core 5. The core 5, the channel layer 3 and the polysilicon layer 2 of the gating circuit are respectively formed by extending the core 5, the channel layer 3 and the polysilicon layer 2 of the corresponding units, and the phase change material is partially replaced by the core 5 material. The thickness of the core 5 of the gating circuit is the sum of the thickness of the core 5 of the corresponding unit and the thickness of the phase-change material layer 4. The distance between adjacent memory chains in the array in the x-axis direction and the y-axis direction is the sum of the thicknesses of two adjacent unit gate electrodes. The gate electrode 1 of the gate circuit abuts against the polysilicon layer 2 of the gate circuit. The gating circuit is provided with a plurality of gate electrodes in the height direction, the distance between the gate electrode closest to the bottom of the memory chain and the bottom of the memory chain is 15nm, and the distance between the gate electrode closest to the top of the diode gate and the top of the diode gate is 15 nm.
The bit line 6-1 has a rectangular parallelepiped shape. The bit line 6-1 has a width direction along the x-axis direction, a length direction along the y-direction, and a height direction along the z-axis direction. The width of the bit line 6-1 is the sum of the thickness of the core 5 of the unit below the bit line, the thickness of the phase change material on two sides of the core 5 and the thickness of the channel layer on two sides of the core 5 in the x-axis direction. The length of the bit line 6-1 is equal to the length of the outermost gate electrode 1 in the y-axis direction.
The word lines 7 are rectangular parallelepiped, and have a longitudinal direction along the x-axis direction, a width direction along the y-axis direction, and a height direction along the z-axis direction. The length of the word line 7 is the sum of the thickness of the unit core 5, the thickness of the phase-change material on two sides of the core 5, the thickness of the channel layer on two sides of the core 5, the thickness of the polycrystalline silicon layer 2 on two sides of the core 5, and the thickness of the gate electrode on two sides of the core 5 in the x direction. The width of the word line 7 is the sum of the thickness of the unit core 5, the thickness of the phase-change material on two sides of the core 5, the thickness of the channel layer on two sides of the core 5 and the thickness of the polysilicon layer 2 on two sides of the core 5 in the y direction.
The core 5, GST, channel, electrode 6-2, gate oxide material used in the array are the same as the cells, the diode gating device uses polysilicon, and the selector circuit is also a MOS structure composed of gate electrode 1, gate oxide, polysilicon channel. The array is filled with dielectric material SiO2 around it, with SiN encapsulation on the top and bottom.
The diode gate 9 includes a first doped semiconductor 9-1, a second doped semiconductor 9-2 and a third doped semiconductor 9-3 which are stacked on each other in a height direction, and the first doped semiconductor 9-1, the second doped semiconductor 9-2 and the third doped semiconductor 9-3 are all rectangular parallelepiped and have the same size. Taking the first doped semiconductor 9-1 as an example, the length direction of the first doped semiconductor 9-1 is along the x-axis direction, the width direction is along the y-direction, the height direction is along the z-direction, the length of the first doped semiconductor 9-1 is along the x-axis direction, and the sum of the thickness of the core 5 of the upper end gating circuit, the thickness of the channel layer on both sides of the core 5, and the thickness of the polysilicon layer 2 on both sides of the core 5 is obtained. The width of the first doped semiconductor 9-1 is the sum of the thickness of the core 5 of the upper end gating circuit, the thickness of the channel layer on two sides of the core 5 and the thickness of the polysilicon layer 2 on two sides of the core 5 in the y-axis direction. The first doped semiconductor 9-1 is connected to the bottom of the memory chain and the third doped semiconductor 9-3 is connected to the word line 7. The bit line 6-1 is a metal electrode material, and the word line 7 is a metal electrode material. As shown in fig. 18 and 19, the metal electrode material is modeled by using COMSOL before simulation in the unit of this embodiment, a thermal insulation layer 8 with a thickness of 2nm is arranged between the core 5 and the phase change material layer 4 and between the phase change material layer 4 and the channel layer 3 during modeling, the thermal insulation layer 8 is arranged around the phase change material layer 4, and the sizes of the core 5, the channel layer 3 and the polysilicon layer 2 are correspondingly increased according to the thermal insulation layer 8. During modeling, dielectric materials are filled around the unit, and a first top cap electrode is arranged on the top of the unit. The bottom is a second cap electrode. The first cap electrode includes a bit line 6-1 and an electrode 6-2, and the second cap electrode is a word line 7. In the case of using COMSOL modeling, a 2nm thermal barrier layer 8 was placed between layers and between cells to simulate thermal resistance boundaries.
As shown in fig. 21 to 23, the phase change memory array structure of the present embodiment includes a memory chain, a gating circuit, a diode gate 9, a word line 7, and a bit line 6-1. The memory chain is formed by vertically stacking the units shown in fig. 1, the gating circuit is composed of a core bar 5, a channel layer 3, a polycrystalline silicon layer 2 and a gate electrode 1, the core bar 5, the channel layer 3 and the polycrystalline silicon layer 2 are all extended from the upper memory chain, and the phase-change material is partially replaced by the core bar 5 material. The diode gate 9 is composed of a first doped semiconductor 9-1, a second doped semiconductor 9-2, and a third doped semiconductor 9-3 using a common fabrication method. The bit line 6-1 on the top is a metal electrode material, and 6-2 is a connection electrode 6-2 of the bit line 6-1 and the channel layer 3. The bottom word line 7 is a metal electrode material. As with the cells, a 2nm insulating layer 8 was placed between the layers and between the cells to simulate the thermal resistance boundary when using COMSOL modeling. The array proposed in this example has a layer pitch Wgetd of 20nm in the x-axis direction and a layer pitch Ws of 20nm in the y-axis direction.
In actual operation, as shown in fig. 24, current flows from the top bit line 6-1, may flow through the channel layer 3, the gating circuit and the diode gate 9 to the bottom grounded word line 7. When the gate electrodes 1 on both sides of the cell are controlled to cut off the channel layer 3, the current will flow to the inner phase-change material layer 4, so that the phase-change material layer is heated and changed in phase. The diode gate 9 is used to control the memory chain in the array through which current will flow, the selection circuit is used to determine which cell on both sides of the core 5 the current will flow, and the gate electrode 1 is used to control the channel layer 3 of a certain layer to be turned off, thereby controlling the specific phase change position in the array.
During simulation, a current pulse is applied to the top of the electrode 6-2, and the polysilicon channel 3 under the middle layer gate electrode 1 is set to be in a closed state by setting material parameters, so that current can flow to an internal phase change material area to enable the temperature of the internal phase change material area to rise and generate phase change. The materials used and their parameters are listed in table 2, set in advance in the simulator.
TABLE 2
The simulations were performed in steps with a current pulse duration of 2ns, with a step size of 0.01ns, and the maximum temperature was read at t-1.8 ns (step 180). When the temperature of the GST region is raised to the melting point 873K, the phase-change material is melted into an amorphous state; and otherwise, when the temperature does not reach the melting point, the phase-change material continuously keeps the crystalline state. Kinoshita proposed a vertical electrode array in Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes, 2012.
As shown in fig. 25, compared with the reference array, the integration level of the array structure proposed in this embodiment can reach 2.1 times when the width wch of the phase change region is 24 nm; when the width of the phase change region is 18nm, the width can reach 3.1 times; the width of the phase change region is 12nm, which is 3.6 times of the width of the phase change region.
Since the thermal crosstalk may be increased in the array unit due to the increased integration degree caused by the changed size, the temperature distribution around the phase change unit in the array proposed in this embodiment is observed, as shown in fig. 26 and 27, which shows the temperature distribution along the z-axis and y-axis directions on the cross section of the phase change unit, it can be seen that the temperature of the unit around the unit does not reach the temperature at which the phase change occurs, and there is no significant thermal crosstalk.
As shown in fig. 16 and 17, the unit of the present embodiment is divided into a strip-shaped unit and a dumbbell-shaped unit, and the phase change material layer of the strip-shaped unit has a rectangular parallelepiped shape. The phase-change material of the dumbbell-shaped unit is in a dumbbell shape, and the size of the middle part of the phase-change material is smaller than the sizes of the two ends of the phase-change material. The portion of the phase change material layer where the middle size becomes smaller is the portion covered by the gate electrode 1. In the x-z coordinate, the narrowed middle portion of the phase change material layer becomes smaller in size along the x-axis, and the remaining portion is the same in size as the core 5. In the y-z coordinate, the narrowed middle portion of the phase change material layer becomes smaller in size along the y-axis, and the remaining portion is the same in size as the core 5. As shown in fig. 28, changing the stripe shape to the dumbbell shape in each cell does not affect the integration thereof, but can reduce thermal crosstalk in the y-axis direction.
While the embodiments of the present invention have been described in detail, it will be apparent to those skilled in the art that variations may be made in the embodiments without departing from the spirit of the invention, and such variations are to be considered within the scope of the invention.
Claims (9)
1. A high-integration phase change memory array structure is characterized in that,
comprises a unit; the unit comprises a core bar, wherein phase change material layers, a channel layer, a polycrystalline silicon layer and a gate electrode are sequentially arranged on two opposite surfaces or four circumferential surfaces of the core bar; the plurality of units are stacked into an n multiplied by n array structure through three-dimensional stacking, and n units stacked mutually in the height direction form a memory chain;
the unit at the bottom end of the memory chain is connected with the gating circuit; the gating circuit comprises a core bar, and a channel layer, a polycrystalline silicon layer and a gate electrode are sequentially arranged outside the core bar; the core bar, the channel layer and the polycrystalline silicon layer of the gating circuit are formed by downwards extending units at the bottom end of the memory chain along the height direction of the memory chain; the gate electrode of the gating circuit has the same structure as the gate electrode of the corresponding unit;
the device also comprises a diode gate, a bit line, an electrode and a word line; the bottom end of the gating circuit is connected with a diode gating device, and the diode gating device is connected with a word line; the channel layer of the top cell of the memory chain is connected with an electrode, and the electrode is connected with a bit line.
2. The highly integrated phase change memory array structure of claim 1, wherein: the thickness of the core bar of the gating circuit is the sum of the thickness of the core bar of the corresponding unit and the thickness of the phase change material layer.
3. The highly integrated phase-change memory array structure of claim 1 or 2, wherein: the height of the phase change material layer, the height of the channel layer and the height of the polycrystalline silicon layer are equal to the height of the core bone, and the gate electrode is located in the middle of the height of the polycrystalline silicon layer.
4. The highly integrated phase change memory array structure of claim 1, wherein: the gate electrodes on the four circumferential sides of the core frame are surrounded into a circumferential shape.
5. The highly integrated phase change memory array structure of claim 1, wherein: the core bone, the phase change material layer, the channel layer, the polycrystalline silicon layer and the gate electrode are all cuboid.
6. The highly integrated phase change memory array structure of claim 1, wherein: the core bone, the channel layer, the polycrystalline silicon layer and the gate electrode are all cuboid; the phase change material layer is dumbbell-shaped with the middle part smaller than the two ends.
7. The highly integrated phase change memory array structure of claim 1, wherein: several units are stacked in three dimensions into a 3 × 3 × 3 array structure.
8. The highly integrated phase change memory array structure of claim 1, wherein: the diode gate comprises a first doped semiconductor, a second doped semiconductor and a third doped semiconductor which are mutually overlapped in the height direction, the structures and the sizes of the first doped semiconductor, the second doped semiconductor and the third doped semiconductor are the same, the first doped semiconductor is connected with the bottom end of the memory chain, and the third doped semiconductor is connected with the word line.
9. The highly integrated phase change memory array structure of claim 1, wherein: the bit lines and the word lines are in a rectangular shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110779718.5A CN113571544A (en) | 2021-07-09 | 2021-07-09 | High-integration phase change memory array structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110779718.5A CN113571544A (en) | 2021-07-09 | 2021-07-09 | High-integration phase change memory array structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113571544A true CN113571544A (en) | 2021-10-29 |
Family
ID=78164338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110779718.5A Pending CN113571544A (en) | 2021-07-09 | 2021-07-09 | High-integration phase change memory array structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113571544A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011233831A (en) * | 2010-04-30 | 2011-11-17 | Hitachi Ltd | Semiconductor memory device |
| US20110284817A1 (en) * | 2010-05-18 | 2011-11-24 | Hitachi, Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
| US20140218999A1 (en) * | 2011-06-10 | 2014-08-07 | Yoshitaka Sasago | Semiconductor storage device |
| CN105304638A (en) * | 2015-11-16 | 2016-02-03 | 上海新储集成电路有限公司 | Three-dimensional phase change memory structure and manufacturing structure |
| CN112234141A (en) * | 2020-12-11 | 2021-01-15 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
-
2021
- 2021-07-09 CN CN202110779718.5A patent/CN113571544A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011233831A (en) * | 2010-04-30 | 2011-11-17 | Hitachi Ltd | Semiconductor memory device |
| US20110284817A1 (en) * | 2010-05-18 | 2011-11-24 | Hitachi, Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
| US20140218999A1 (en) * | 2011-06-10 | 2014-08-07 | Yoshitaka Sasago | Semiconductor storage device |
| CN105304638A (en) * | 2015-11-16 | 2016-02-03 | 上海新储集成电路有限公司 | Three-dimensional phase change memory structure and manufacturing structure |
| CN112234141A (en) * | 2020-12-11 | 2021-01-15 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI520272B (en) | Three dimensional memory array architecture | |
| JP5324787B2 (en) | Memory device including thermal conductor located between program volumes | |
| US9590016B2 (en) | 3D semiconductor memory device having variable resistance memory elements | |
| KR100504700B1 (en) | Phase random access memory with high dencity | |
| US8169819B2 (en) | Semiconductor storage device | |
| US8441040B2 (en) | Semiconductor memory device | |
| CN110808332B (en) | Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell | |
| US20030222292A1 (en) | Phase changeable memory devices having multi-level data storage elements and methods of fabricating the same | |
| US20110287602A1 (en) | Phase change memory device having a bent heater and method for manufacturing the same | |
| KR100790449B1 (en) | Phase change ram device and method of manufacturing the same | |
| JP2010287744A (en) | Solid-state memory, data processing system, and data processing apparatus | |
| JP2007149913A (en) | Nonvolatile memory element and method of manufacturing same | |
| CN110943102B (en) | Three-dimensional integrated circuit structure of high-density phase change memory | |
| JP2007129199A (en) | Non-volatile memory element and manufacturing method thereof | |
| KR101511421B1 (en) | 3-Dimensional Memory of using Multi-layered Phase Change Material | |
| CN111029362B (en) | Preparation method of three-dimensional integrated circuit structure of high-density phase change memory | |
| Li et al. | Phase change memory | |
| Yoo et al. | Electro-thermal model for thermal disturbance in cross-point phase-change memory | |
| CN103545338A (en) | Memory device with thermally-confined spacer and manufacturing method thereof | |
| US7884344B2 (en) | Phase change memory device resistant to stack pattern collapse and a method for manufacturing the same | |
| CN113571544A (en) | High-integration phase change memory array structure | |
| CN107154273A (en) | Semiconductor storage | |
| KR100967676B1 (en) | Phase change RAM device and method of manufacturing the same | |
| KR20070102295A (en) | Unit cell for phase change random access memory device with multiple bits per cell | |
| KR100858089B1 (en) | Phase change memory device and methods of manufacturing and operating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |