CN113571427A

CN113571427A - Method for forming embedded chip structure

Info

Publication number: CN113571427A
Application number: CN202110625227.5A
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-06-04
Filing date: 2021-06-04
Publication date: 2021-10-29

Abstract

Embodiments of the present application provide a method of forming a buried wafer structure, comprising: providing a chip stack, wherein the chip stack comprises a first chip and a second chip which are arranged in a stacking mode, and a heat dissipation layer located between the first chip and the second chip; the chip stack is disposed in the first opening of the leadframe, and the heat dissipation layer of the chip stack is bonded to the leadframe. The invention aims to provide an embedded wafer structure and a forming method thereof, so as to improve the heat dissipation of the embedded wafer structure.

Description

Method for forming embedded chip structure

Technical Field

Embodiments of the invention relate to buried wafer structures and methods of forming the same.

Background

The conventional embedded chip package structure mainly includes an organic substrate base and a lead frame base, and if the heat dissipation problem is considered, the lead frame base is adopted mainly because most of the embedded chips are high-power chips.

In the existing embedded chip package structure having the lead frame substrate, the main feature is the stacked chips, i.e. the chips are stacked on the upper and lower surfaces of the lead frame substrate, however, if the thickness of the whole package structure is to be reduced, the lead frame substrate needs to be dug to accommodate the chips, but for the lead frame which is becoming smaller (for example, the thickness is less than 50 μm), the grooves are formed on both sides of the lead frame and the chip pads are retained, which is difficult to operate.

Disclosure of Invention

In view of the problems in the related art, an object of the present invention is to provide a buried wafer structure and a method for forming the same, so as to improve the heat dissipation of the buried wafer structure.

Embodiments of the present application provide a method of forming a buried wafer structure, comprising: providing a chip stack, wherein the chip stack comprises a first chip and a second chip which are arranged in a stacking mode, and a heat dissipation layer located between the first chip and the second chip; the chip stack is disposed in the first opening of the leadframe, and the heat dissipation layer of the chip stack is bonded to the leadframe.

In some embodiments, the leadframe is heated to increase a width of the first opening of the leadframe before the chip stack is disposed in the first opening of the leadframe, and the leadframe is cooled to bond sidewalls of the heat dissipation layer of the chip stack to the leadframe after the chip stack is disposed in the first opening of the leadframe.

In some embodiments, the sidewalls of the first chip are aligned with the sidewalls of the heat spreading layer, which are also bonded to the leadframe.

In some embodiments, the forming of the chip stack comprises: attaching a monolithic first chip and a plurality of spaced apart second chips on either side of the monolithic heat dissipation layer, respectively, and cutting the monolithic heat dissipation layer and the monolithic first chip to form a singulated chip stack, the singulated chip stack including one second chip.

In some embodiments, the second chip has a width less than a width of the first chip, the second chip being spaced apart from the leadframe.

In some embodiments, the first opening is formed to include a first section and a second section, the first section having a width greater than a width of the second section, the heat spreading layer engaging an inner wall of the second section.

In some embodiments, after the chip stack is disposed in the first opening of the leadframe, the chip stack and the leadframe are encapsulated into a molding compound.

In some embodiments, the leadframe has a second opening beside the first opening, the molding compound in the second opening is drilled, and a via is formed in the formed first opening.

In some embodiments, the drilling is performed using a laser drilling process.

In some embodiments, the molding compound is on the first circuit layer, and the chip stack and the leadframe are over the first circuit layer after the chip stack and the leadframe are encapsulated into the molding compound.

An embodiment of the present application provides a buried wafer structure, including: a lead frame having a first opening; and the chip stack is positioned in the first opening and comprises a first chip and a second chip which are arranged in a stacking mode and a heat dissipation layer positioned between the first chip and the second chip, and the heat dissipation layer is in contact with the lead frame.

In some embodiments, the heat spreading layer contacts the leadframe for heat transfer therebetween.

In some embodiments, the heat dissipation layer includes an intermediate metal layer and first and second solder materials disposed on lower and upper sides of the intermediate metal layer, respectively, the first and second solder materials being bonded to the lead frame.

In some embodiments, the first opening has a first section and a second section located over the first section, the second section having a width less than the width of the first section, the sidewalls of the first chip and the heat spreading layer are aligned, and the first chip and the heat spreading layer contact the inner walls of the first section of the opening, the second chip being spaced apart from the inner walls of the second section of the opening.

In some embodiments, the first solder material and the sidewalls of the intermediate metal layer engage inner walls of a first section of the first opening, the second solder material engages a bottom surface of a projection of the leadframe at the second section, the second solder material also contacting portions of the inner walls of the second section of the first opening.

In some embodiments, the second solder material has a chamfer at the location of contact with the leadframe.

In some embodiments, further comprising: a first circuit layer located below the chip stack; a second circuit layer located above the chip stack; and a through hole extending through the second opening of the lead frame and connecting the first circuit layer and the second circuit layer.

In some embodiments, the width of the second opening is constant.

In some embodiments, further comprising: and a molding compound between the first and second circuit layers, the lead frame and the chip stack being in the molding compound.

In some embodiments, the first chip and the second chip are attached to the heat dissipation layer by a first adhesive layer and a second adhesive layer, respectively.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 to 10 show a process of forming a wiring layer of the present application.

Fig. 11 to 20 show a process of forming a chip stack of the present application.

Fig. 21 to 24 show a process of assembling the chip stack and the lead frame.

Fig. 25-38 illustrate a process of assembling a buried wafer structure forming the present application.

Fig. 39-47 illustrate different embodiments of the buried wafer structure of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In the conventional process of fabricating the buried chip structure, it is very difficult or even impossible to use a lead frame with a thickness of less than 50 μm. Existing embedded die structure packages are thicker (e.g., greater than 0.6mm) because of the typically thicker lead frame (e.g., greater than 100 μm).

The buried wafer structure and the method for forming the same of the present application will be described in detail with reference to the accompanying drawings.

Referring to fig. 1, a first dielectric layer 12 is formed on a first carrier 10. In some embodiments, the first dielectric layer 12 includes a Polyamide (PA) material, and the first exposure process 11 is performed on the first dielectric layer 12 to cure.

Referring to fig. 2, the first dielectric layer 12 is patterned, and a first seed layer 20 is formed on the patterned first dielectric layer 12.

Referring to fig. 3, a first mask layer 30 is formed on the first seed layer 20. In some embodiments, the first mask layer 30 includes a Photoresist (PR) material, and a second exposure process 31 is performed to cure the first mask layer 30.

Referring to fig. 4, the first mask layer 30 is patterned to expose the first seed layer 20, and a first metal layer 40 is formed on the first seed layer 20.

Referring to fig. 5, the remaining first mask layer 30 is removed, leaving the first seed layer 20 and the first metal layer 40.

Referring to fig. 6, a second dielectric layer 60 is formed on the first seed layer 20 and the first metal layer 40. In some embodiments, the second dielectric layer 60 comprises a Polyamide (PA) material, and the second dielectric layer 60 is subjected to a third exposure process 61 for curing.

Referring to fig. 7, the second dielectric layer 60 is patterned, and a second seed layer 70 is formed on the patterned second dielectric layer 60. The second seed layer 70 contacts the first metal layer 40.

Referring to fig. 8, a second mask layer 80 is formed on the second seed layer 70. In some embodiments, the second mask layer 80 includes a Photoresist (PR) material, and a fourth exposure process 81 is performed to cure the second mask layer 80.

Referring to fig. 9, the second mask layer 80 is patterned to expose the second seed layer 70, and a second metal layer 90 is formed on the second seed layer 70.

Referring to fig. 10, the remaining second mask layer 80 is removed, and the second seed layer 70 is patterned using the second metal layer 90 as a mask. To this end, the first wiring layer 100 of the present application on the first carrier 10 is formed.

Referring to fig. 11, a third dielectric layer 110 and a pad 112 on the third dielectric layer 110 are provided, and a fourth dielectric layer 114 covers the pad 112. In an embodiment, the fourth dielectric layer 114 is an organic layer.

Referring to fig. 12, the structure shown in fig. 11 is inverted, and an adhesive seed layer 120 is formed on the third dielectric layer 11. In some embodiments, the adhesion seed layer 120 comprises titanium.

Referring to fig. 13, a solder seed layer 130 is formed on the adhesion seed layer 120. In an embodiment, the solder seed layer 130 includes copper.

Referring to fig. 14, the structure shown in fig. 13 is again flipped so that the fourth dielectric layer 114 is over. Thus, a wafer 140 is formed.

Referring to fig. 15, a heat dissipation layer 150 is provided, the heat dissipation layer 150 including an intermediate metal layer 151, a first solder material 152 and a second solder material 154 on upper and lower sides of the intermediate metal layer.

Referring to fig. 16, the solder seed layer 130 of the wafer 140 is attached to the second solder material 154 of the heat spreading layer 150.

Referring to fig. 17, the structure shown in fig. 16 is inverted and a plurality of second chips 170 are disposed on the first solder material 152 of the heat dissipation layer 150 using clips 172. In an embodiment, a vacuum environment is configured within the clamp 172 when clamping the second chip 170.

Referring to fig. 18, the fifth dielectric layer 180 on the second chip 170 and the fourth dielectric layer 114 of the wafer 140 are removed using a first etching process 181. In an embodiment, the fifth dielectric layer 180 includes an organic and the first etching process 181 is a chemical etching.

Referring to fig. 19, a dicing tool 191 is used to singulate the heat dissipation layer 150 and the wafer 140 into a chip stack 190, where the chip stack 190 includes a first chip 192 and a second chip 170 arranged in a stacked manner, and the heat dissipation layer 150 is located between the first chip 192 and the second chip 170. In some embodiments, the first chip 192 and the second chip 170 have a thickness of 50 μm to 200 μm.

Referring to fig. 20, the chip stack 190 is held using a second holder 200. In an embodiment, a vacuum environment is configured in the second clamping member 200 when clamping the chip stack 190.

Referring to fig. 21, a lead frame 210 is provided, the lead frame 210 having a first opening 212 and a second opening 214 beside the first opening 212. In some embodiments, the first opening 212 has a first section 2121 and a second section 2122, and the width of the second section 2122 is smaller than the width of the first section 2121. In an embodiment, a chemical etching process is used to form the first opening 212 and the second opening 214 in the leadframe 210.

Referring to fig. 22, the lead frame 210 is heated such that the width of the first opening 212 becomes large. As shown, the lead frames 210 on both sides of the first opening 212 move from a position a, which is originally indicated by a dotted line, to a position B, which is indicated by a solid line.

Referring to fig. 23, chip stack 190 is placed in first opening 212 using third clamp 231. In an embodiment, a vacuum environment is configured in the third clamping member 231 when clamping the chip stack 190.

Referring to fig. 24, after the chip stack 190 is placed in the first opening 212, the lead frame 210 is cooled so that the lead frames on both sides of the first opening 212 move from a position C (corresponding to a position B shown by a solid line in fig. 22 and 23) originally shown by a dotted line to a position D (corresponding to a position a shown by a dotted line in fig. 22 and 23) shown by a solid line. After moving to position D, the first solder material 152 is soldered to the lead frame 210 to form a chamfer 240 on the sidewall of the first opening 212. The intermediate metal layer 151 contacts the lead frame 210 to enhance thermal conductivity between the chip stack 190 and the lead frame 210 to enhance heat dissipation of the structure. In some embodiments, the intermediate metal layer 151 includes a graphene material having a high electrical conductivity, which is advantageous for heat dissipation. In some embodiments, the graphene material has a thickness of 1nm to 5 nm.

Referring to fig. 25, the molding compound 250 is disposed on the first circuit layer 100, placing the leadframe 210 upside down on the first circuit layer 100.

Referring to fig. 26, the molding compound 250 in the second opening 214 is apertured using a laser drilling process 261.

Referring to fig. 27, a third sub-layer 270 is formed in the openings and over the molding compound 250.

Referring to fig. 28, a third mask layer 280 is formed on the third sub-layer 270. In some embodiments, the third mask layer 280 includes a Photoresist (PR) material, and a fifth exposure process 281 is performed to cure the third mask layer 280.

Referring to fig. 29, the third mask layer 280 is patterned to expose the third sub-layer 270, and a third metal layer 290 is formed on the third sub-layer 270.

Referring to fig. 30, the remaining third mask layer 280 is removed, leaving the third sub-layer 270 and the third metal layer 290. In some embodiments, the via formed in the second opening 214 and composed of the third sub-layer 270 and the third metal layer 290 has an aspect ratio of 2.5 to 3.5, wherein the height is 120 μm to 350 μm. The third seed layer 270 is laterally spaced from the leadframe 210 by a distance of 50 to 20 μm.

Referring to fig. 31, a sixth dielectric layer 310 is formed on the molding compound 250, and a second wiring layer 312 is disposed on the sixth dielectric layer 310, the second wiring layer 312 being disposed on a second carrier 314. In some embodiments, the second circuit layer 312 is formed by the same forming method as the first circuit layer 100. In some embodiments, the molding compound 250 has a thickness of 150 to 400 μm and the sixth dielectric layer 310 has a thickness of 10 to 30 μm.

Referring to fig. 32, the first and

second carriers

10 and 314 are removed.

Referring to fig. 33, a second laser drilling process 331 is used to drill the second circuit layer 312, the sixth dielectric layer 310.

Referring to fig. 34, a fourth sub-layer 340 is formed in the opening and on the second circuit layer 312.

Referring to fig. 35, a fourth mask layer 350 is formed on the fourth sub-layer 340. In some embodiments, the fourth mask layer 350 includes a Photoresist (PR) material, and a sixth exposure process 351 is performed to cure the fourth mask layer 350.

Referring to fig. 36, the fourth mask layer 350 is patterned to expose the fourth sub-layer 340, and a fourth metal layer 360 is formed on the fourth sub-layer 340.

Referring to fig. 37, the remaining fourth mask layer 350 is removed, and the fourth sub-layer 340 is patterned using the fourth metal layer 360 as a mask. In an embodiment, the fourth metal layer 360 is Cu, Au, Ag, or the like. In some embodiments, the aspect ratio of the via formed by the fourth sub-layer 340 and the fourth metal layer is 0.5 to 2, wherein the height is 30 μm to 60 μm.

Referring to fig. 38, a solder ball 382 is formed on the fourth metal layer 360. Thus, the buried wafer structure 380 of the present application is formed. In the drawings of the embodiments of the present application, a single buried wafer structure 380 is taken as an example, and in actual industrial production, a whole structure includes a plurality of buried wafer structures 380, and then a dicing process is performed to obtain a singulated buried wafer structure 380. In some embodiments, the various sub-layers and metal layers of the present application are formed by sputtering, electroplating, electroless plating, and/or printing, laminating, or potting. In some embodiments, the material of each metal layer of the present application is selected from Cu, Ag, Au, Ni, Pd, etc., and the material of each sub-layer is selected from Ti, W, Ni, etc

Fig. 39 shows a different embodiment of the present application, in which a solder material 390 is formed in the fourth metal layer 360, as compared to fig. 38. In an embodiment, the solder material 390 is the same material as the solder balls 382.

Fig. 40 shows a different embodiment of the present application, in contrast to fig. 38, the molding compound 250 of fig. 40 is formed in the second opening 214 of the lead frame 210, and the seventh dielectric layer 400 encapsulates the lead frame 210. In an embodiment, the sixth dielectric layer 310 and the seventh dielectric layer 400 include organic substances such as Polyimide (PI), epoxy (epoxy), Polybenzoxazole (PBO), flame retardant 4-grade material (FR4), prepreg (PP), Ajinomotobuild-up film (ABF), bismaleimide triazine resin (BT); or/and inorganic substances, such as silicon, glass, ceramics, oxides (e.g., SiOx, TaOx), nitrides (e.g., SiNx). The sixth dielectric layer 310 and the seventh dielectric layer 400 may comprise the same material, or the sixth dielectric layer 310 and the seventh dielectric layer 400 may comprise different materials.

Fig. 41 shows a different embodiment of the present application, in comparison to fig. 38, where wire 410 joins third metal layer 290 and chip stack 190.

Fig. 42 shows a different embodiment of the present application, which further comprises a passive component 420, compared to fig. 38, and the fourth metal layer 360 is connected to the chip stack 190 through the passive component 420.

Fig. 43 shows a different embodiment of the present application, in which fibers 430 are formed in the sixth dielectric layer 310 and the molding compound 250, as compared to fig. 38.

Fig. 44 shows a different embodiment of the present application, in which, compared to fig. 38, the heat dissipation layer 150 of the chip stack 190 and the sidewalls of the first chip 192 contact the lead frame 210, the second chip 170 is disposed on the lead frame 210, and the second chip 170 contacts the top surface of the lead frame 210.

Fig. 45 shows a different embodiment of the present application, in which two adjacent chip stacks 190 are provided in a lead frame 210, as compared to fig. 38.

Fig. 46 shows a different embodiment of the present application, where the thickness of the chip stack 190 is larger than in fig. 38, such that the bottom surface of the chip stack 190 is lower than the bottom surface of the lead frame 210.

Fig. 47 shows a different embodiment of the present application, in which, compared to fig. 38, the lead frame 210 in fig. 38 has a single stair structure 383 in contact with the chip stack 190, and the lead frame 210 in fig. 47 has two stair structures, one of which 471 is in contact with the chip stack 190 and the other of which 472 is spaced apart from the chip stack 190.

Embodiments of the present application provide a buried die structure in which the heat dissipation of the structure is improved by making holes in the lead frame and providing a heat dissipation layer in contact with the lead frame in the chip stack. Moreover, the embodiment of the application allows a thicker lead frame to be used, and the stability of the packaging structure is enhanced. The buried wafer structure of the present application is lower in process cost compared to redistribution layers (RDLs) and has higher performance (e.g., many input/output quantities) than organic substrates.

According to the embodiment of the scheme, the opening is directly formed on the lead frame, and the chip stack is placed in the opening, so that the thickness of the packaging piece is reduced, and the yield loss caused by the existing thin lead frame is avoided. When the chip stacking member is provided, the heat dissipation layer is provided, and then different chips are respectively bonded to two sides of the heat dissipation layer, so as to construct the chip stacking member with a heat dissipation mechanism. The embodiment of the application heats and cools the lead frame, so that the lead frame can contact the heat dissipation layer, and the heat dissipation performance is improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of forming a buried wafer structure, comprising:

providing a chip stack, wherein the chip stack comprises a first chip and a second chip which are arranged in a stacking mode, and a heat dissipation layer located between the first chip and the second chip;

disposing the chip stack in a first opening of a leadframe, a heat spreading layer of the chip stack being bonded to the leadframe.

2. The method of forming a buried die structure according to claim 1, wherein the lead frame is heated to increase a width of the first opening of the lead frame before the chip stack is disposed in the first opening of the lead frame, and the lead frame is cooled to bond sidewalls of the heat dissipation layer of the chip stack to the lead frame after the chip stack is disposed in the first opening of the lead frame.

3. The method of claim 2, wherein the sidewalls of the first chip are aligned with the sidewalls of the heat spreading layer, the sidewalls of the first chip also being bonded to the leadframe.

4. The method of forming a buried wafer structure of claim 1, wherein the forming of the chip stack includes:

attaching a monolithic piece of the first chip and a plurality of spaced apart second chips on either side of the monolithic piece of the heat spreading layer,

dicing the one-piece heat dissipation layer and the one-piece first chip to form the singulated chip stack, the singulated chip stack including one of the second chips.

5. The method of forming a buried wafer structure according to claim 4, wherein the second die has a width less than a width of the first die, the second die being spaced apart from the lead frame.

6. The method of claim 1, wherein the first opening is formed to include a first section and a second section, the first section having a width greater than a width of the second section, the heat spreading layer engaging an inner wall of the second section.

7. The method of forming a buried die structure of claim 1, wherein the chip stack and the leadframe are encapsulated into a molding compound after the chip stack is disposed in the first opening of the leadframe.

8. The method of claim 7, wherein the leadframe has a second opening beside the first opening, the molding compound in the second opening is drilled, and a via is formed in the formed first opening.

9. The method of forming a buried wafer structure of claim 8, wherein said drilling is performed using a laser drilling process.

10. The method of claim 7, wherein the molding compound is on a first circuit layer, and the die stack and the leadframe are over the first circuit layer after encapsulating the die stack and the leadframe into the molding compound.