CN113568850A - Data transmission method and device, electronic equipment and storage medium - Google Patents
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Abstract
The embodiment of the application provides a data transmission method, a data transmission device, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring a digital code of data to be transmitted; determining general input/output port GPIO level frames corresponding to digital codes of data to be transmitted according to preset frame time and a preset coding level conversion rule to obtain target GPIO level frames, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital codes and the GPIO level frames; and sequentially sending each target GPIO level frame to a receiving end. According to the data transmission method, the data transmission is carried out in the mode of the GPIO level frames, the duration of each single frame GPIO level frame is the preset frame time, and each GPIO level frame can be effectively distinguished through the duration, so that each data can be effectively distinguished, the sampling difficulty is reduced, and the point-to-point single-wire GPIO data transmission is effectively realized.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a data transmission method and apparatus, an electronic device, and a storage medium.
Background
In the point-to-point single WIRE communication protocol, UART (Universal Asynchronous Receiver/Transmitter), 1-WIRE protocol, etc. are most commonly used. In these protocols, the receiving end needs to constantly detect the received signal at a sampling frequency far exceeding the baud rate of the transmitting end, which imposes a very large load on the CPU. Moreover, the conventional UART or 1-WIRE protocol is difficult to implement on a GPIO (General Purpose Input/Output port) through software, and the main reasons are 2 points, where 1 is inaccurate BIT edge sampling, and 2 is difficult to sample multiple continuous 0 or continuous 1 data, and therefore a single-WIRE GPIO data transmission method capable of being effectively applied to point-to-point is urgently needed.
Disclosure of Invention
An object of the embodiments of the present application is to provide a data transmission method, an apparatus, an electronic device, and a storage medium, so as to provide an effective single-wire GPIO data transmission method applied to point-to-point. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a sending end, and the method includes:
acquiring a digital code of data to be transmitted;
determining each general input/output port GPIO level frame corresponding to the digital code of the data to be transmitted according to preset frame time and a preset coding level conversion rule to obtain each target GPIO level frame, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame;
and sequentially sending each target GPIO level frame to a receiving end.
Optionally, the GPIO level frames indicate different digital codes by different levels of interruption times and/or levels of high and low.
Optionally, the digital code is a binary code, the binary code includes 0 and 1, a GPIO level frame corresponding to 0 includes one interrupt, and a GPIO level frame corresponding to 1 includes three interrupts.
Optionally, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Optionally, in the transmission phase, the first digital bit is represented by two frames of GPIO level frames.
Optionally, the sending end is a master device or a slave device, where the communication process is initiated by the master device.
In a second aspect, an embodiment of the present application provides a data transmission method, which is applied to a receiving end, and the method includes:
receiving each GPIO level frame to be decoded sent by a sending end;
and sequentially decoding each GPIO level frame to be decoded into a digital code according to a preset frame time and a preset coding level conversion rule, wherein the preset frame time is the duration of a single frame of GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame.
Optionally, the GPIO level frames indicate different digital codes by different levels of interruption times and/or levels of high and low.
Optionally, the digital code is a binary code, the binary code includes 0 and 1, a GPIO level frame corresponding to 0 includes one interrupt, and a GPIO level frame corresponding to 1 includes three interrupts.
Optionally, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Optionally, in the transmission phase, the first digital bit is represented by two frames of GPIO level frames.
Optionally, the receiving end is a master device or a slave device, wherein a communication process is initiated by the master device.
In a third aspect, an embodiment of the present application provides a data transmission apparatus, which is applied to a sending end, and the apparatus includes:
the digital code acquisition module is used for acquiring a digital code of data to be transmitted;
the GPIO level frame determining module is used for determining each general purpose input/output port GPIO level frame corresponding to the digital code of the data to be transmitted according to preset frame time and a preset coding level conversion rule to obtain each target GPIO level frame, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame;
and the GPIO level frame sending module is used for sending each target GPIO level frame to a receiving end in sequence.
Optionally, the GPIO level frames indicate different digital codes by different levels of interruption times and/or levels of high and low.
Optionally, the digital code is a binary code, the binary code includes 0 and 1, a GPIO level frame corresponding to 0 includes one interrupt, and a GPIO level frame corresponding to 1 includes three interrupts.
Optionally, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Optionally, in the transmission phase, the first digital bit is represented by two frames of GPIO level frames.
Optionally, the sending end is a master device or a slave device, where the communication process is initiated by the master device.
In a fourth aspect, an embodiment of the present application provides a data transmission apparatus, which is applied to a receiving end, where the apparatus includes:
the GPIO level frame receiving module is used for receiving each GPIO level frame to be decoded sent by the sending end;
and the digital coding conversion module is used for sequentially decoding each GPIO level frame to be decoded into a digital code according to a preset frame time and a preset coding level conversion rule, wherein the preset frame time is the duration of a single frame of the GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame.
Optionally, the GPIO level frames indicate different digital codes by different levels of interruption times and/or levels of high and low.
Optionally, the digital code is a binary code, the binary code includes 0 and 1, a GPIO level frame corresponding to 0 includes one interrupt, and a GPIO level frame corresponding to 1 includes three interrupts.
Optionally, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Optionally, in the transmission phase, the first digital bit is represented by two frames of GPIO level frames.
Optionally, the receiving end is a master device or a slave device, wherein a communication process is initiated by the master device.
In a fifth aspect, an embodiment of the present application provides an electronic device, including a memory and at least two processors, where the at least two processors are connected through a GPIO;
the memory is used for storing a computer program;
the processor is configured to implement any one of the above data transmission methods when executing the program stored in the memory.
In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program, when executed by a processor, implements any of the data transmission methods described above.
The data transmission method, the data transmission device, the electronic equipment and the storage medium provided by the embodiment of the application acquire the digital code of the data to be transmitted; determining general input/output port GPIO level frames corresponding to digital codes of data to be transmitted according to preset frame time and a preset coding level conversion rule to obtain target GPIO level frames, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital codes and the GPIO level frames; and sequentially sending each target GPIO level frame to a receiving end. The data transmission mode based on the GPIO level frame is characterized in that the data transmission mode is carried out in the form of the GPIO level frame, the duration of each single-frame GPIO level frame is preset frame time, each GPIO level frame can be effectively distinguished according to the duration, even if a plurality of continuous 0 or 1 frames are sent, effective distinguishing can be carried out according to the duration, the sampling difficulty is reduced, and point-to-point single-wire GPIO data transmission is effectively achieved. Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a data transmission method applied to a sending end according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an application scenario according to an embodiment of the present application;
fig. 3 is a schematic diagram of levels in a data transmission method according to an embodiment of the present application;
fig. 4 is a schematic diagram of a data transmission method applied to a receiving end according to an embodiment of the present application;
fig. 5 is a schematic diagram of a data transmission apparatus applied to a transmitting end according to an embodiment of the present application;
fig. 6 is a schematic diagram of a data transmission apparatus applied to a receiving end according to an embodiment of the present application;
fig. 7 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
First, terms of art in the embodiments of the present application are explained:
GPIO: the General Purpose Input/Output (i/o) port is a controllable pin of the embedded device, and is connected with the external device, thereby realizing the functions of external communication, control and data acquisition.
Interrupting: when some accident occurs and the host computer is needed to intervene in the running process of the computer, the machine can automatically stop the running program and transfer to the program for processing the new condition, and after the processing is finished, the original suspended program is returned to continue running. The interruption of the GPIO level frame of the embodiment of the application is triggered by the rising edge and the falling edge of the level.
Embedding: a device for controlling, monitoring or assisting in the operation of machines and equipment is a special purpose computer system with strict requirements on functions, reliability, cost, volume, power consumption, etc., and is a complex of software and hardware.
Baud rate: the number of symbols transmitted per second is an index for measuring the data transmission rate, and is expressed by the number of times the carrier modulation state changes per unit time.
A CPU: the Central Processing Unit (cpu) is an ultra-large scale integrated circuit, and is an arithmetic Core (Core) and a Control Core (Control Unit) of a computer. Its functions are mainly to interpret computer instructions and to process data in computer software.
GPIO is widely applied to the existing CPU chip, in many communication modes, one device can be divided into a plurality of sub-boards, in many cases, signal interfaces between the sub-boards are fewer, but communication needs to be realized between the modules. In the prior art, network communication is adopted among modules, but the network communication cannot be used when an IP address and an MAC address are not configured among daughter boards.
In view of this, an embodiment of the present application provides a data transmission method, which is applied to a sending end, and referring to fig. 1, the method includes:
s101, digital codes of data to be transmitted are obtained.
The data transmission method applied to the sending end in the embodiment of the application can be realized through electronic equipment, specifically, can be realized through a CPU of the electronic equipment, the receiving end and the sending end can be different CPUs, for example, referring to FIG. 2, only one GPIO signal connecting line is needed for data transmission between two pieces of equipment. When interface signals between two devices are few and network communication is not established, the embodiment of the application can meet the requirement of simple communication between the two devices. Because the most common GPIO interface in the chip, and GPIO has low-power consumption, the simple advantage of wiring, and the suitability is strong, so adopt GPIO to communicate in this application embodiment.
The data to be transmitted may be transmitted in the form of digital codes, and the data to be transmitted is converted into digital codes, for example, binary codes or decimal codes, to obtain the digital codes of the data to be transmitted.
And S102, determining each GPIO level frame corresponding to the digital code of the data to be transmitted according to preset frame time and a preset coding level conversion rule to obtain each target GPIO level frame, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame.
In the embodiment of the application, data transmission is carried out in the form of GPIO level frames. The GPIO level frame refers to GPIO level in unit time length, the unit time length is preset frame time, and the GPIO level frame can be set in a user-defined mode according to actual conditions. The preset coding level conversion rule is a corresponding rule of digital coding and GPIO level frames. Different digital codes correspond to different GPIO level frames. The data transmission in the embodiment of the present application can be divided into three stages, including: start, Trans, and Stop. Start denotes the Start of data transmission, Trans denotes the specific data transmitted, i.e. the data to be transmitted, and Stop denotes the Stop of data transmission. And sequentially generating each GPIO level frame corresponding to the digital code of the data to be transmitted, namely each target GPIO level frame by taking the preset frame time as the duration of each frame of the GPIO level frame according to a preset coding level conversion rule.
In one possible implementation, the GPIO level frames represent different digital codes by different levels of interruption times and/or levels of high and low.
In the embodiment of the application, the interruption of the level is triggered by the rising edge and the falling edge of the level, when the level is converted from the low level to the high level, the interruption of the level is triggered once, and similarly, when the level is converted from the high level to the low level, the interruption of the level is triggered once. The number of level interruptions and/or the high or low of the level (i.e., high or low) within a unit time duration (i.e., within one frame of GPIO level) may be used to distinguish between different digital codes, Start, Stop, etc.
In the embodiment of the application, the number of interruptions is used to represent different digital codes, so that the selection of the counting time point is particularly important, and in order to avoid confusion of counting between different stages and between BYTEs, after the transmission of each stage and each BIT is finished, the frame time (preset frame time) is introduced, so that the GPIO level frames are distinguished. The inter-period of the baud rate successive interruptions is negligible compared to the frame time.
And S103, sequentially sending each target GPIO level frame to a receiving end.
And the sending end sends each target GPIO level frame to the receiving end in sequence.
In the embodiment of the application, a data transmission mode based on GPIO level frames is provided, data transmission is performed in the form of GPIO level frames, the duration of each single-frame GPIO level frame is preset frame time, each GPIO level frame can be effectively distinguished according to the duration, even if multiple continuous 0 or 1 frames are sent, effective distinguishing can be performed according to the duration, the sampling difficulty is reduced, and point-to-point single-wire GPIO data transmission is effectively achieved.
For binary coding, for example, the number of interrupts of 0(BIT0) and 1(BIT1) in the Trans phase is adjustable and can be set by self according to practical situations. In one possible embodiment, the digital code is a binary code, which, referring to fig. 3, includes 0 and 1, where the GPIO level frame for 0 includes one interrupt and the GPIO level frame for 1 includes three interrupts.
The GPIO level frames are distinguished by taking frame time as an interval, and are combined with counting characteristics of different stages to calculate the interruption times, and finally, each target GPIO level frame corresponding to data to be sent is calculated. Intermediate the Start and Stop phases is the Trans phase. In the Trans phase, a BYTE consists of eight BITs, each of which may be either 0 or 1. To distinguish BIT0 from BIT1, BIT0 may be designed as 1 interrupt and BIT1 as 3 consecutive interrupts.
In one possible embodiment, referring to fig. 3, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
The Start signal indicates Start, i.e., Start of transmission; the Stop signal indicates Stop, i.e. the end of the transmission. In the Start phase, there are 5 consecutive interrupts, and in the Stop phase, there are 5 consecutive interrupts. Although both the Start and Stop phases are 5 interrupts in succession, the Start and Stop phases may be distinguished by different Start levels. For example, the Start phase Start level is high and the 5 flipped levels remain low, while the Stop phase Start level is low and the 5 flipped levels remain high. Of course, the starting levels of the Start phase and the Stop phase can be switched, and can be set according to practical situations.
In the embodiment of the present application, the Start signal and the end signal have different Start levels, so that the Start phase and the Stop phase can be effectively distinguished.
In one possible implementation, the first digital bit is represented by two frames of GPIO level frames during the transmit phase.
In the Trans phase, for the counting of the first digital BIT, only one frame of GPIO level is used, and it is not possible to effectively distinguish BIT0 from BIT1, so the Trans phase is divided into two parts: the first digital bit and other bits.
For the first digital bit, two frames of GPIO level frames are selected, namely, the frame time after the Start is finished and the frame time after one digital bit is finished are added. For example, for the case that a single frame BIT0 is 1 interrupt and a single frame BIT1 is 3 continuous interrupts, if the first digital BIT is BIT0, the GPIO interrupt count is 2 after the two frames are ended; if the first digital BIT is BIT1, the GPIO interrupt count is 4 after the two frames are over.
Counting other bits except the first digital bit in the Trans stage only needs one frame of GPIO level frame, and the counting end time is the frame time after the bit ends. If a BIT except the first digital BIT is BIT0, after the GPIO level frame of the BIT is finished, the GPIO interruption count is 1; if a BIT other than the first digital BIT is BIT1, the GPIO interrupt count is 3 after the GPIO level frame for that BIT is over.
In a possible implementation, the sending end is a master device or a slave device, wherein the communication process is initiated by the master device.
In the single GPIO mode, in order to prevent both GPIO connections from preempting GPIO transmission, one is defined as HOST (master device) and the other is defined as SLAVE (SLAVE device), and all communication procedures must be initiated by HOST, that is, data transmitted by SLAVE is initiated after HOST notification, so that it is possible to avoid the situation that both ends transmit data simultaneously, which causes an abnormality.
An embodiment of the present application further provides a data transmission method, applied to a receiving end, referring to fig. 4, where the method includes:
s201, receiving each GPIO level frame to be decoded sent by a sending end.
And S202, sequentially decoding each GPIO level frame to be decoded into a digital code according to a preset frame time and a preset coding level conversion rule, wherein the preset frame time is the duration of a single frame of the GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame.
In one possible implementation, the GPIO level frames represent different digital codes by different levels of interruption times and/or levels of high and low.
In one possible embodiment, the digital code is a binary code, the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
In one possible implementation, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
In one possible implementation, the first digital bit is represented by two frames of GPIO level frames during the transmit phase.
In a possible implementation, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.
The GPIO interrupt mode is set to rising edge and falling edge triggered. The counting is distinguished by the frame time as an interval, and the interruption number comparison is carried out by combining the counting characteristics of different stages, and finally the transmission data is calculated.
In the Start stage and the Stop stage, the number of the interrupts of the Start stage and the Stop stage is different from that of the transit stage, the level state of the Start stage and the Stop stage is also different after the transmission is finished, the level is low after the Start transmission is finished, and the level is high after the Stop transmission is finished, so that the Start stage and the Stop stage are very easy to discriminate in time sequence.
In the Trans phase, for the first BIT count, it is impossible to determine whether BIT0 or BIT1 is a frame time, so the count is divided into two parts: the count of the first bit and the other bits. For the first BIT, two frame times are selected, namely, the frame time after the Start is finished and the frame time after the first BIT is finished, if the first BIT is BIT0, the GPIO interruption count is 2 after the two frames are finished; if the first BIT is BIT1, the GPIO interrupt count is 4 after the two frames are over.
For counting the other bits except the first bit in the Trans phase, only one frame time is needed, and the frame time is the frame time after the end of the bit. If the first BIT is BIT0, after the frame is finished, the GPIO interruption count is 1; if the first BIT is BIT1, the GPIO interrupt count is 3 after the frame is over.
Although the Stop phase is defined as 5 interrupts, the Stop bit is left with only 4 interrupts in the actual judgment since the count per bit of the Trans phase is the frame time after the bit.
In the embodiment of the application, a data transmission mode based on the GPIO level frame is provided, and point-to-point single-wire GPIO data transmission is effectively realized.
An embodiment of the present application further provides a data transmission apparatus, refer to fig. 5, applied to a sending end, where the apparatus includes:
a digital code obtaining module 11, configured to obtain a digital code of data to be sent;
a GPIO level frame determining module 12, configured to determine, according to a preset frame time and a preset coding level conversion rule, each GPIO level frame of the general input/output ports corresponding to the digital coding of the data to be transmitted, to obtain each target GPIO level frame, where the preset frame time is a duration of a single frame GPIO level frame, and the preset coding level conversion rule is a correspondence rule between the digital coding and the GPIO level frame;
and a GPIO level frame transmitting module 13, configured to sequentially transmit each target GPIO level frame to a receiving end.
Optionally, the GPIO level frames indicate different digital codes by different levels of interruption times and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and 1, a GPIO level frame corresponding to 0 includes one interrupt, and a GPIO level frame corresponding to 1 includes three interrupts.
Optionally, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Optionally, in the transmission phase, the first digital bit is represented by two frames of GPIO level frames.
Optionally, the sending end is a master device or a slave device, wherein the communication process is initiated by the master device.
An embodiment of the present application further provides a data transmission apparatus, see fig. 6, which is applied to a receiving end, where the apparatus includes:
a GPIO level frame receiving module 21, configured to receive each GPIO level frame to be decoded sent by the sending end;
and the digital coding conversion module 22 is configured to sequentially decode each GPIO level frame to be decoded into a digital code according to a preset frame time and a preset coding level conversion rule, where the preset frame time is a duration of a single frame of GPIO level frame, and the preset coding level conversion rule is a corresponding rule between the digital code and the GPIO level frame.
Optionally, the GPIO level frames indicate different digital codes by different levels of interruption times and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and 1, a GPIO level frame corresponding to 0 includes one interrupt, and a GPIO level frame corresponding to 1 includes three interrupts.
Optionally, the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Optionally, in the transmission phase, the first digital bit is represented by two frames of GPIO level frames.
Optionally, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.
The embodiment of the present application further provides an electronic device, see fig. 7, including a memory 32 and at least two processors 31, where the at least two processors 31 are connected through a GPIO;
the memory 32 is used for storing computer programs;
the processor 31 is configured to implement any one of the above data transmission methods when executing the program stored in the memory 32.
The Memory may include a RAM (Random Access Memory) or an NVM (Non-Volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a DSP (Digital Signal Processing), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.
An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements any of the data transmission methods described above.
It should be noted that, in this document, the technical features in the various alternatives can be combined to form the scheme as long as the technical features are not contradictory, and the scheme is within the scope of the disclosure of the present application. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments of the apparatus, the electronic device, and the storage medium, since they are substantially similar to the method embodiments, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiments.
The above description is only for the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (16)
1. A data transmission method, applied to a transmitting end, the method comprising:
acquiring a digital code of data to be transmitted;
determining each general input/output port GPIO level frame corresponding to the digital code of the data to be transmitted according to preset frame time and a preset coding level conversion rule to obtain each target GPIO level frame, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame;
and sequentially sending each target GPIO level frame to a receiving end.
2. The method of claim 1, wherein the GPIO level frames represent different digital codes by different levels of interruption times and/or levels of high and low.
3. The method of claim 2, wherein the digital code is a binary code, wherein the binary code comprises 0 and 1, wherein a frame of GPIO levels for 0 comprises one interrupt and wherein a frame of GPIO levels for 1 comprises three interrupts.
4. The method of claim 1, wherein each corresponding GPIO level frame of a start signal and an end signal comprises 5 interrupts, and wherein the start signal and the end signal have different starting levels.
5. The method of claim 1, wherein during the transmit phase, the first digital bit is represented by a two frame GPIO level frame.
6. The method of claim 1, wherein the sender is a master device or a slave device, and wherein the communication process is initiated by the master device.
7. A data transmission method, applied to a receiving end, the method comprising:
receiving each GPIO level frame to be decoded sent by a sending end;
and sequentially decoding each GPIO level frame to be decoded into a digital code according to a preset frame time and a preset coding level conversion rule, wherein the preset frame time is the duration of a single frame of GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame.
8. The method of claim 7, wherein the GPIO level frames represent different digital codes by different levels of interruption times and/or levels of high and low.
9. The method of claim 8, wherein the digital code is a binary code, wherein the binary code comprises 0 and 1, wherein a frame of GPIO levels for 0 comprises one interrupt and wherein a frame of GPIO levels for 1 comprises three interrupts.
10. The method of claim 7, wherein each corresponding GPIO level frame of a start signal and an end signal comprises 5 interrupts, and wherein the start signal and the end signal have different starting levels.
11. The method of claim 7, wherein during the transmit phase, the first digital bit is represented by a two frame GPIO level frame.
12. The method of claim 7, wherein the receiving end is a master device or a slave device, and wherein the communication process is initiated by the master device.
13. A data transmission apparatus, applied to a transmitting end, the apparatus comprising:
the digital code acquisition module is used for acquiring a digital code of data to be transmitted;
the GPIO level frame determining module is used for determining each general purpose input/output port GPIO level frame corresponding to the digital code of the data to be transmitted according to preset frame time and a preset coding level conversion rule to obtain each target GPIO level frame, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame;
and the GPIO level frame sending module is used for sending each target GPIO level frame to a receiving end in sequence.
14. A data transmission apparatus, applied to a receiving end, the apparatus comprising:
the GPIO level frame receiving module is used for receiving each GPIO level frame to be decoded sent by the sending end;
and the digital coding conversion module is used for sequentially decoding each GPIO level frame to be decoded into a digital code according to a preset frame time and a preset coding level conversion rule, wherein the preset frame time is the duration of a single frame of the GPIO level frame, and the preset coding level conversion rule is a corresponding rule of the digital code and the GPIO level frame.
15. The electronic equipment is characterized by comprising a memory and at least two processors, wherein the at least two processors are connected through GPIO;
the memory is used for storing a computer program;
the processor is configured to implement the data transmission method according to any one of claims 1 to 12 when executing the program stored in the memory.
16. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the data transmission method according to any one of claims 1 to 12.
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