CN113567884A - Short circuit detection method for power supply ground network in circuit layout design - Google Patents
Short circuit detection method for power supply ground network in circuit layout design Download PDFInfo
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- CN113567884A CN113567884A CN202110828298.5A CN202110828298A CN113567884A CN 113567884 A CN113567884 A CN 113567884A CN 202110828298 A CN202110828298 A CN 202110828298A CN 113567884 A CN113567884 A CN 113567884A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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Abstract
The invention provides a short circuit detection method of a power supply ground network in circuit layout design, which comprises the following steps: step S1, extracting a power ground network; step S2, obtaining detection precision; step S3, planning detection points based on the power ground network and the detection precision, and marking the detection points in the graphic data of the mask plate; and step S4, performing layout verification on the mask graphics data marked with the detection points to generate a report of the positions of the short-circuit points. The short circuit detection method of the power supply ground network in the circuit layout design has the following advantages: 1) the generation of the detection points is carried out automatically; 2) the selection of the detection point is independent of the user experience; 3) the detection precision is high and adjustable; 4) the method supports multi-point detection, does not need iteration, and can find all short-circuit points at one time; 5) the detection time is short.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a short circuit detection method of a power supply ground network in circuit layout design.
Background
The integrated circuit design scale is getting bigger and more complex, and it is very common that short circuit occurs between power supply ground networks, but at present, EDA (design automation) tools can only detect the short circuit path and can not effectively indicate the physical location of the short circuit. US patent No. US7503023B1 discloses a prior art detection method for locating a short-circuit point by manually adding 4 detection points.
It has some limitations as follows:
1) a detection point needs to be manually added;
2) the selection of the detection point is based on user experience;
3) the detection result may be a public path, and a real short circuit point still needs to be found on the public path;
4) for a multipoint short circuit, multiple iterations are required;
5) the detection accuracy cannot be controlled.
Disclosure of Invention
In view of the defects of the prior art, the invention aims to provide a short circuit detection method for a power supply ground network in a circuit layout design, which has the advantages of automatic detection point formation, high detection precision and adjustability.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
a short circuit detection method for a power supply ground network in circuit layout design comprises the following steps:
step S1, extracting a power ground network;
step S2, obtaining detection precision;
step S3, planning detection points based on the power ground network and the detection precision, and marking the detection points in the graphic data of the mask plate;
and step S4, performing layout verification on the mask graphics data marked with the detection points to generate a report of the positions of the short-circuit points.
Further, in step S1, the power ground network is extracted by obtaining a design exchange file and a library exchange file of the circuit layout design, and the power and ground network is physically extracted in the layout and routing tool based on the design exchange file and the library exchange file to obtain physical graphic information of the power ground network.
Further, the physical graphic information of the power ground network includes a physical layer number, a graphic position and a graphic size.
Further, in step S2, the detection accuracy is obtained and input by a user, and the user may set and input the detection accuracy based on the scale of the circuit layout design and the possible operation time of the detection process.
Further, the step S3, planning detection points based on the power ground network and the detection accuracy, includes the following steps:
step S31, determining a step size based on the detection accuracy;
step S32, determining the graph length and the total step number based on the graph size and the step size;
step S33, selecting a stepping mode based on the graph size;
and step S34, generating detection point coordinates one by one from a preset starting point for each layer of physical graph based on the step length, the total step number and the stepping mode.
Further, in the present invention,
in step S31, the step size is determined based on the detection accuracy, and is:
step is detection precision/2, and step is step length;
in step S32, determining the pattern length and the total number of steps based on the pattern size and the step size, including:
if the transverse length of the pattern size is larger than the longitudinal length, taking the transverse length as the pattern length;
if the transverse length of the pattern size is less than or equal to the longitudinal length, taking the longitudinal length as the pattern length;
num is L/step, num is the total step number, and L is the graph length;
in step S33, a step manner is selected based on the size of the graph, and the step manner is:
if the transverse length of the pattern size is larger than the longitudinal length, a transverse stepping mode is selected,
if the transverse length of the graph size is less than or equal to the longitudinal length, selecting a longitudinal stepping mode;
step S34, based on the step size, the total number of steps, and the stepping manner, generating detection point coordinates one by one for each layer of physical graphics from a preset starting point, where the detection point coordinates are:
X(i)＝X+x_step*i，
y (i) ═ Y + Y _ step × i, X is a preset starting point abscissa, i is the total number, and takes a value of 1 to num, and Y is a preset starting point ordinate; x (i), Y (i) are detected point coordinates.
Further, the preset starting point is a lower left corner of the graph, or an upper left corner of the graph, or a lower right corner of the graph, or an upper right corner of the graph.
The short circuit detection method of the power supply ground network in the circuit layout design has the following advantages:
1) the generation of the detection points is carried out automatically;
2) the selection of the detection point is independent of the user experience;
3) the detection precision is high and adjustable;
4) the method supports multi-point detection, does not need iteration, and can find all short-circuit points at one time;
5) the detection time is short.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a short circuit detection method for a power supply ground network in a circuit layout design according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a step S3 in the short circuit detection method for the power supply ground network in the circuit layout design according to an embodiment of the present invention, where detection points are planned based on the power supply ground network and the detection accuracy;
FIG. 3 is a schematic diagram showing the relationship between the detection accuracy and the step length according to the present invention;
FIG. 4 is a diagram of a reticle graphic marked with detection points obtained in accordance with an embodiment of the present invention;
fig. 5 is a schematic diagram of a short-circuit point actually detected according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a short circuit detection method for a power ground network in a circuit layout design according to an embodiment of the present invention includes the following steps:
step S1, extracting a power ground network;
step S2, obtaining detection precision;
step S3, planning detection points based on the power ground network and the detection precision, and marking the detection points in the graphic data of the mask plate;
and step S4, performing layout verification on the mask graphics data marked with the detection points to generate a report of the positions of the short-circuit points.
Specifically, in step S1, the power ground network is extracted by obtaining a design exchange file and a library exchange file of the circuit layout design, and the power ground network is physically extracted in the layout and routing tool based on the design exchange file and the library exchange file to obtain physical graphic information of the power ground network. Wherein the Design Exchange File (DEF) includes layout logic and physical information, and the Library Exchange File (LEF) includes layout design usage ports and physical information.
Further, the physical graphic information of the power ground network includes a physical layer number, a graphic position and a graphic size.
In step S2, the detection accuracy is obtained, where the detection accuracy may be directly obtained by setting a fixed value in advance, or may be input by a user, and the user may set and input different detection accuracies based on the scale of the circuit layout design and the possible operation time of the detection process. Therefore, the detection precision can be adjusted at will according to the needs, and can be set to be higher according to the needs.
Referring to fig. 2, in the step S3, a schematic flow chart of planning detection points based on the power ground network and the detection accuracy is shown. The step S3, planning detection points based on the power ground network and the detection accuracy, includes the following steps:
step S31, determining a step size based on the detection accuracy;
step S32, determining the graph length and the total step number based on the graph size and the step size;
step S33, selecting a stepping mode based on the graph size;
and step S34, generating detection point coordinates one by one from a preset starting point for each layer of physical graph based on the step length, the total step number and the stepping mode.
In particular, the method comprises the following steps of,
in step S31, the step size is determined based on the detection accuracy, and is:
step is detection precision/2, and step is step length;
please refer to fig. 3, which illustrates a relationship between the detection accuracy and the step size. The detection accuracy is the minimum range in which a short-circuit point can be detected. In an extreme case, the adjacent edges of the two physical patterns are short-circuited, and the detection precision which can be achieved at this time is the distance between the nearest two power ground detection points, namely 2 times of the step length, so that the step length is half of the precision under the condition of determining the detection precision.
In step S32, determining the pattern length and the total number of steps based on the pattern size and the step size, including:
if the transverse length of the pattern size is larger than the longitudinal length, taking the transverse length as the pattern length;
if the transverse length of the pattern size is less than or equal to the longitudinal length, taking the longitudinal length as the pattern length;
num is L/step, num is the total step number, and L is the graph length;
in step S33, a step manner is selected based on the size of the graph, and the step manner is:
if the transverse length of the pattern size is larger than the longitudinal length, a transverse stepping mode is selected,
if the transverse length of the graph size is less than or equal to the longitudinal length, selecting a longitudinal stepping mode;
step S34, based on the step size, the total number of steps, and the stepping manner, generating detection point coordinates one by one for each layer of physical graphics from a preset starting point, where the detection point coordinates are:
X(i)＝X+x_step*i，
y (i) ═ Y + Y _ step × i, X is a preset starting point abscissa, i is the total number, and takes a value of 1 to num, and Y is a preset starting point ordinate; x (i), Y (i) are detected point coordinates.
The preset starting point can be set to any position in the graph as required, preferably the lower left corner of the graph, or the upper left corner of the graph, or the lower right corner of the graph, or the upper right corner of the graph.
Referring to FIG. 4, a mask pattern marked with detection points is obtained by performing a detection with a detection precision of 100um according to an embodiment.
Mask layout pattern data (GDS) is the data that is ultimately used for reticle fabrication, and must pass layout verification checks, i.e., circuit and layout consistency checks (LVS), where the presence or absence of a short is a priority check item, i.e., finding the shortest path between power and ground detection points. Therefore, in step S4, the report of the position of the short-circuit point can be generated by performing layout verification on the reticle graphic data marked with the detection point. Fig. 5 is a schematic diagram of a short-circuit point actually detected according to an embodiment.
Please refer to the table below, which takes a million gate-level automobile controller chip as a test case, wherein the digital-analog hybrid, multi-voltage domain. Compared with the detection result in the prior art, the actual detection result reduces the possible short circuit amount by about 91 percent, thereby shortening the debugging time; the short path length is reduced by about 99%. The detection precision is improved, and the short circuit point is positioned efficiently; the time consumed by the whole detection and analysis is greatly reduced, and the detection efficiency is improved.
The short circuit detection method of the power supply ground network in the circuit layout design has the following advantages:
1) the generation of the detection points is carried out automatically;
2) the choice of detection point is independent of user experience:
3) the detection precision is high and adjustable:
4) the method supports multi-point detection, does not need iteration, and can find all short-circuit points at one time;
5) the detection time is short.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention disclosed herein are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. A short circuit detection method of a power supply ground network in circuit layout design is characterized by comprising the following steps:
step S1, extracting a power ground network;
step S2, obtaining detection precision;
step S3, planning detection points based on the power ground network and the detection precision, and marking the detection points in the graphic data of the mask plate;
and step S4, performing layout verification on the mask graphics data marked with the detection points to generate a report of the positions of the short-circuit points.
2. The short circuit detection method according to claim 1, wherein in step S1, the extracting the power ground network is to obtain a design exchange file and a library exchange file of the circuit layout design, and perform physical extraction on the power and ground networks in the placement and routing tool based on the design exchange file and the library exchange file to obtain physical graphic information of the power and ground networks.
3. The short circuit detection method according to claim 2, wherein the physical pattern information of the power ground network includes a physical layer number, a pattern position, and a pattern size.
4. The short circuit detection method according to claim 1, wherein the step S2 for obtaining the detection accuracy is inputted by a user, and the user can set and input the detection accuracy based on the scale of the circuit layout design and the possible operation time of the detection process.
5. The short circuit detection method according to claim 3, wherein the step S3 of planning detection points based on the power ground network and detection precision comprises the steps of:
step S31, determining a step size based on the detection accuracy;
step S32, determining the graph length and the total step number based on the graph size and the step size;
step S33, selecting a stepping mode based on the graph size;
and step S34, generating detection point coordinates one by one from a preset starting point for each layer of physical graph based on the step length, the total step number and the stepping mode.
6. The short circuit detection method according to claim 5,
in step S31, the step size is determined based on the detection accuracy, and is:
step = detection accuracy/2, step being a step length;
in step S32, determining the pattern length and the total number of steps based on the pattern size and the step size, including:
if the transverse length of the pattern size is larger than the longitudinal length, taking the transverse length as the pattern length;
if the transverse length of the pattern size is less than or equal to the longitudinal length, taking the longitudinal length as the pattern length;
num = L/step, num is the total number of steps, L is the graph length;
in step S33, a step manner is selected based on the size of the graph, and the step manner is:
if the transverse length of the pattern size is larger than the longitudinal length, a transverse stepping mode is selected,
if the transverse length of the graph size is less than or equal to the longitudinal length, selecting a longitudinal stepping mode;
step S34, based on the step size, the total number of steps, and the stepping manner, generating detection point coordinates one by one for each layer of physical graphics from a preset starting point, where the detection point coordinates are:
X(i)=X+x_step*i，
y (i) = Y + Y _ step X, X is a preset starting point abscissa, i is a total number, and takes a value of 1 to num, and Y is a preset starting point ordinate; x (i), Y (i) are detected point coordinates.
7. The short circuit detection method according to claim 5, wherein the preset starting point is a lower left corner of the graph, or an upper left corner of the graph, or a lower right corner of the graph, or an upper right corner of the graph.
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| CN202110828298.5A CN113567884A (en) | 2021-07-26 | 2021-07-26 | Short circuit detection method for power supply ground network in circuit layout design |
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| CN202110828298.5A CN113567884A (en) | 2021-07-26 | 2021-07-26 | Short circuit detection method for power supply ground network in circuit layout design |
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| CN202110828298.5A Withdrawn CN113567884A (en) | 2021-07-26 | 2021-07-26 | Short circuit detection method for power supply ground network in circuit layout design |
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