CN113555202B - Adjustable differential active inductance circuit - Google Patents
Adjustable differential active inductance circuit Download PDFInfo
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- CN113555202B CN113555202B CN202110763089.7A CN202110763089A CN113555202B CN 113555202 B CN113555202 B CN 113555202B CN 202110763089 A CN202110763089 A CN 202110763089A CN 113555202 B CN113555202 B CN 113555202B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/42—Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils
Abstract
The invention discloses an adjustable differential active inductance circuit which comprises a variable capacitor, an adjustable PMOS (P-channel metal oxide semiconductor) transistor load, a first cross coupling NMOS (N-channel metal oxide semiconductor) transistor pair and a second cross coupling NMOS transistor pair, wherein the second cross coupling NMOS transistor pair is connected with two variable capacitors Cb, the second cross coupling NMOS transistor pair is connected with the adjustable PMOS transistor load through the first cross coupling NMOS transistor pair, and an input end Vin + and an input end Vin-are connected between the adjustable PMOS transistor load and the first cross coupling NMOS transistor pair. The adjustable differential active inductance circuit expands the adjustment range of the inductance value and the tuning range of the Q value by adjusting the variable resistor and the grid voltage of the load transistor, and has higher inductance value adjustment precision and chip integration level.
Description
Technical Field
The invention belongs to the technical field of active inductor manufacturing, and particularly relates to an adjustable differential active inductor circuit.
Background
With the continuous development of CMOS technology, the size of large-scale integrated circuits is continuously reduced, and in the application of high-frequency communication technology, the passive inductor device occupies a larger area of a chip system, such as in modules of voltage-controlled oscillators, equalizers, low-noise amplifiers, filters, and the like, and the application of the passive inductor inevitably increases the chip cost.
The active inductance technology utilizes a gyrator circuit to generate an equivalent inductance value, and can replace a passive inductor in a communication chip system in some application scenes. However, due to parasitic impedance and parasitic capacitance of the transistor, the effective operating frequency range and the inductance adjusting range of the inductor are limited; meanwhile, the active inductor is designed by using the operational amplifier, so that the structure is complex, high power consumption and noise can be generated, and the resonance frequency of the inductor is reduced.
Therefore, how to reduce the chip area and improve the inductance adjustment range and the operating frequency adjustment range without increasing much circuit power consumption is a technical problem to be solved in the active inductance research at present.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a circuit for equivalently converting variable capacitance into variable inductance based on an impedance conversion technology, which can reduce the area of a chip and improve the utilization efficiency of the chip, and has the advantages of low power consumption, high adjustable range and easy realization.
The purpose of the invention is realized by the following technical scheme:
an adjustable differential active inductance circuit comprises a variable capacitor Cb, an adjustable PMOS transistor load, a first cross-coupled NMOS transistor pair and a second cross-coupled NMOS transistor pair, wherein the second cross-coupled NMOS transistor pair is connected with the two variable capacitors Cb, the second cross-coupled NMOS transistor pair is connected with the adjustable PMOS transistor load through the first cross-coupled NMOS transistor pair, and an input terminal Vin + and an input terminal Vin-are connected between the adjustable PMOS transistor load and the first cross-coupled NMOS transistor pair.
The invention expands the adjusting range of the inductance value and the tuning range of the Q value by adjusting the variable resistor Cb and the grid voltage of the load transistors M1 and M2, and has higher inductance value adjusting precision and chip integration level.
The invention is based on the impedance conversion technology, adopts the equivalent conversion of the variable capacitor into the variable inductor, can reduce the area of the chip and improve the utilization efficiency of the chip, and has the advantages of lower power consumption, high adjustable range and the like.
Preferably, the adjustable PMOS transistor load includes a first P-type MOS transistor M1 and a second P-type MOS transistor M2, the source of the first P-type MOS transistor M1 is connected to the source of the second P-type MOS transistor M2 and then connected to the power supply VDD, the gate of the first P-type MOS transistor M1 is connected to the gate of the second P-type MOS transistor M2 and then connected to the regulation voltage Vtune, the drain of the first P-type MOS transistor M1 is connected to the input terminal Vin + of the novel active inductor circuit, and the drain of the second P-type MOS transistor M2 is connected to the other input terminal Vin-.
Preferably, the first cross-coupled NMOS transistor pair includes a third N-type MOS transistor M3 and a fourth N-type MOS transistor M4; the grid electrode of the third N-type MOS tube M3 and the drain electrode of the fourth N-type MOS tube M4 are connected together and then connected with the input end Vin-of the power inductor circuit; the drain of the third N-type MOS transistor M3 is connected to the gate of the fourth N-type MOS transistor M4, and further connected to the other input terminal Vin +.
Preferably, the second cross-coupled NMOS transistor pair (4) includes a fifth N-type MOS transistor M5 and a sixth N-type MOS transistor M6, the drain of the fifth N-type MOS transistor is connected to the gate of the sixth N-type MOS transistor, and then connected to one end V1 of the variable capacitor Cb; the grid electrode of the fifth N-type MOS tube is connected with the drain electrode of the sixth N-type MOS tube and then connected with one end V2 of another variable capacitor Cb. The inductance value, the Q value and the working frequency range of the novel differential active inductance circuit are adjusted by adjusting the variable capacitor Cb and the load adjusting voltage Vtune.
Preferably, the variable capacitor Cb includes a switch Sc, three switch-controlled MOS transistor capacitors and a voltage-controlled MOS transistor capacitor connected in parallel, switches S1, S2 and S3 are respectively connected in series with the MOS transistors M7, M8 and M9, one end of the switch is a first end of the variable capacitor Cb, the other end of the switch is connected to the gate of the MOS transistor, and the drain and the source of the MOS transistor are both grounded; three MOS transistor capacitor branches controlled by a switch are connected in parallel with a switch Sc; the voltage-regulated MOS transistor capacitor comprises two MOS transistors, the drains and the sources of the two MOS transistors are connected with a regulated voltage Vc, the grid of one MOS transistor is used as a first end of the variable capacitor Cb, and the grid of the other MOS transistor is grounded.
Preferably, the capacitance values of the MOS transistor capacitors controlled by the three switches are sequentially increased, the voltage control MOS transistors realize continuous adjustment of the capacitance values, the adjustment range of the capacitance values can cover the resolution of the capacitance values of the MOS transistors controlled by the switches, continuous adjustment of the capacitance values combined by thickness and fineness is realized, and the on-off of the switch Sc realizes whether the variable capacitor Cb is short-circuited or not so as to control the work of Cb.
The invention adopts two pairs of transistor cross coupling pairs and variable capacitors to convert the variable capacitors into adjustable active inductors, and improves the adjustment range and the adjustment precision of the inductance value by changing the variable capacitors combined by thick and thin capacitors and the load bias current.
The adjustable differential active inductance circuit provided by the invention has the advantages of high chip integration level, simple design, low power consumption, adjustable range, high precision and the like.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration of an adjustable differential active inductor according to a preferred embodiment of the present invention;
fig. 2 is a schematic diagram of a variable capacitor structure according to a preferred embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the adjustable differential active inductance circuit of the present embodiment includes: variable capacitance Cb (1), adjustable PMOS transistor loads M1, M2(2), first cross-coupled NMOS transistor pair M3, M4(3), second cross-coupled NMOS transistor pair M5, M6 (4).
The adjustable PMOS transistor load comprises a first P-type MOS transistor M1 and a second P-type MOS transistor M2, the source electrode of the first P-type MOS transistor M1 is connected with the source electrode of the second P-type MOS transistor M2 and then connected with a power supply VDD, the grid electrode of the first P-type MOS transistor M1 is connected with the grid electrode of the second P-type MOS transistor M2 and then connected with an adjusting voltage Vtune, the drain electrode of the first P-type MOS transistor M1 is connected with the input end Vin + of the novel active inductance circuit, and the drain electrode of the second P-type MOS transistor M2 is connected with the other input end Vin-.
The first cross-coupled NMOS transistor pair comprises a third N-type MOS transistor M3 and a fourth N-type MOS transistor M4, wherein the grid electrode of the third N-type MOS transistor M3 is connected with the drain electrode of the fourth N-type MOS transistor M4 and is connected with the input end Vin-of the active inductance circuit; the drain of the third N-type MOS transistor M3 and the gate of the fourth N-type MOS transistor M4 are connected together and connected to the other input terminal Vin + of the active inductor circuit.
The second cross-coupled NMOS transistor pair (4) comprises a fifth N-type MOS transistor M5 and a sixth N-type MOS transistor M6, wherein the drain electrode of the fifth N-type MOS transistor is connected with the gate electrode of the sixth N-type MOS transistor and is connected with one end V1 of the variable capacitor Cb; the grid electrode of the fifth N-type MOS tube and the drain electrode of the sixth N-type MOS tube are connected together and connected to one end V2 of the other variable capacitor Cb, and the source electrode of the fifth N-type MOS tube and the source electrode of the sixth N-type MOS tube are grounded. The other end of the variable capacitor Cb is grounded.
In this embodiment, the impedance at the junction of the active inductor circuits V1 and V2 is represented as:
the input impedance of the active inductor circuit is expressed as:
the relationship between the equivalent inductance value at low frequency and the variable capacitance Cb and the transistor transconductance M5(M6) is expressed as:
from the above formula, by changing the variable capacitance Cb and transconductance gmAnd (adjusting load bias voltage Vtune) to realize adjustment of the inductance value, the Q value and the working frequency range of the novel differential active inductance circuit.
As shown in fig. 2, a preferred coarse-fine tuning tunable capacitor circuit includes three MOS transistor capacitors controlled by three switches respectively, a voltage-tuned MOS transistor capacitor pair, and a switch connected in parallel. The MOS transistor capacitor parallel branch circuit controlled by a switch, wherein three switches S1, S2 and S3 are respectively connected with three MOS transistors M7, M8 and M9 in series, one end of each switch is one end of a variable capacitor Cb, the other end of each switch is connected with the grid of the MOS transistor, and the drain and the source of each MOS transistor are connected together and grounded; three MOS transistor capacitance branches controlled by the switch are connected in parallel, one end of the three MOS transistor capacitance branches is used as one end V1(2) of the variable capacitor Cb, and the other end of the three MOS transistor capacitance branches is grounded.
The voltage-regulated MOS transistor capacitor pair is composed of two MOS transistors M10, M12, the drains and sources of which are connected together and connected to the regulated voltage Vc, the gate of one of which is used as one end V1(2) of the variable capacitor Cb, and the gate of the other of which is grounded. One end of the parallel switch Sc in the variable capacitor Cb serves as one end V1(2) of the variable capacitor Cb, and the other end is grounded. The capacitance values of the three switch-controlled MOS transistor capacitors are sequentially improved, the voltage-controlled MOS transistors realize continuous adjustment of the capacitance values, the adjustment range of the capacitance values can cover the resolution of the capacitance values of the switch-controlled MOS transistors, and the thickness-combined continuous adjustment of the capacitance values is realized. And the on-off of the switch Sc realizes whether the variable capacitor Cb is short-circuited or not, so that the work of Cb is controlled. The voltage Vc controls the transistor capacitor to continuously and finely adjust the capacitor, the maximum capacitor of the finely adjusted capacitor is the adjustment resolution of the coarsely adjusted capacitor, the adjustment resolution of the adjustable capacitor Cb is guaranteed to be the minimum change step diameter of the finely adjusted capacitor, and the maximum change value of the adjustable capacitor is the maximum value of the capacitor array.
The invention provides a variable capacitor structure with thick and thin combination by utilizing the technology of converting capacitive load impedance into inductance by utilizing a transistor cross coupling structure, has wide adjustment range and high adjustment precision, and improves the adjustment range and precision of active inductance. The invention has the characteristics of wide inductance adjusting range, high adjusting precision, uniform adjustment, easy integration, low power consumption and the like, and is suitable for industrial application.
Claims (5)
1. An adjustable differential active inductance circuit, characterized by: the variable capacitor Cb, an adjustable PMOS transistor load, a first cross-coupling NMOS transistor pair and a second cross-coupling NMOS transistor pair are included, the second cross-coupling NMOS transistor pair is connected with the two variable capacitors Cb, the second cross-coupling NMOS transistor pair is connected with the adjustable PMOS transistor load through the first cross-coupling NMOS transistor pair, and an input end Vin + and an input end Vin-are connected between the adjustable PMOS transistor load and the first cross-coupling NMOS transistor pair;
the variable capacitor Cb comprises three MOS transistor capacitors M7, M8, M9, a voltage-regulated MOS transistor capacitor pair and three switches S1, S2 and S3, wherein the three switches S1, S2 and S3 are respectively connected with three MOS transistor capacitors M7, M8 and M9 in series, one ends of the three switches S1, S2 and S3 are first ends of the variable capacitor Cb, the other ends of the three switches S1, S2 and S3 are respectively connected with gates of the three MOS transistor capacitors M7, M8 and M9, and drains and sources of the three MOS transistor capacitors M7, M8 and M9 are all grounded; three branches formed by controlling MOS transistor capacitors M7, M8 and M9 by switches S1, S2 and S3 respectively are connected with the switch Sc in parallel; the voltage-regulated MOS transistor capacitor pair comprises two MOS transistors, the drains and the sources of the two MOS transistors are connected to the regulated voltage Vc, the grid of one MOS transistor is connected with the first end of the variable capacitor Cb, and the grid of the other MOS transistor is grounded.
2. The adjustable differential active inductance circuit according to claim 1, wherein: and the capacitance values of the three MOS transistor capacitors are sequentially improved.
3. The adjustable differential active inductance circuit according to claim 1, wherein: the adjustable PMOS transistor load comprises a first P-type MOS transistor M1 and a second P-type MOS transistor M2, the source electrode of the first P-type MOS transistor M1 is connected with the source electrode of the second P-type MOS transistor M2 and then connected with a power supply VDD, the grid electrode of the first P-type MOS transistor M1 is connected with the grid electrode of the second P-type MOS transistor M2 and then connected with an adjusting voltage Vtune, the drain electrode of the first P-type MOS transistor M1 is connected with an input end Vin +, and the drain electrode of the second P-type MOS transistor M2 is connected with the other input end Vin-.
4. An adjustable differential active inductance circuit according to claim 1 or 3, wherein: the first cross-coupled NMOS transistor pair comprises a third N-type MOS transistor M3 and a fourth N-type MOS transistor M4, the grid electrode of the third N-type MOS transistor M3 is connected with the drain electrode of the fourth N-type MOS transistor M4 and is connected with an input end Vin-; the drain of the third N-type MOS transistor M3 and the gate of the fourth N-type MOS transistor M4 are connected together and to the other input terminal Vin +.
5. An adjustable differential active inductance circuit according to any one of claims 1-2, wherein: the second cross-coupled NMOS transistor pair comprises a fifth N-type MOS transistor M5 and a sixth N-type MOS transistor M6, wherein the drain electrode of the fifth N-type MOS transistor and the gate electrode of the sixth N-type MOS transistor are connected together and connected to the first end V1 of the variable capacitor Cb; the grid electrode of the fifth N-type MOS tube and the drain electrode of the sixth N-type MOS tube are connected together and connected to the first end V2 of the other variable capacitor Cb, and the source electrode of the fifth N-type MOS tube and the source electrode of the sixth N-type MOS tube are grounded.
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| US6621362B2 (en) * | 2001-05-18 | 2003-09-16 | Broadcom Corporation | Varactor based differential VCO band switching |
| US8093958B2 (en) * | 2007-12-05 | 2012-01-10 | Integrated Device Technology, Inc. | Clock, frequency reference, and other reference signal generator with a controlled quality factor |
| KR20090063629A (en) * | 2007-12-14 | 2009-06-18 | 삼성전자주식회사 | Digitally controled oscillator |
| CN103956986B (en) * | 2014-05-05 | 2017-02-15 | 北京工业大学 | Differential active inductor with tunable high Q value |
| US9698727B1 (en) * | 2015-12-10 | 2017-07-04 | Qualcomm Incorporated | Coupled inductor-based resonator |
| CN108365846A (en) * | 2018-01-09 | 2018-08-03 | 浙江大学 | A kind of current-mode phase-locked loop structures based on active inductance transformer |
| CN111371437A (en) * | 2018-12-26 | 2020-07-03 | 恩智浦美国有限公司 | Latching comparator circuit and method |
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