CN113554155B - Neural network circuit and Hall strip synapse based on SDSP and WTA algorithm - Google Patents
Neural network circuit and Hall strip synapse based on SDSP and WTA algorithm Download PDFInfo
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- 210000000225 synapse Anatomy 0.000 title claims abstract description 51
- 238000004422 calculation algorithm Methods 0.000 title claims abstract description 32
- 238000013528 artificial neural network Methods 0.000 title claims abstract description 27
- 210000002569 neuron Anatomy 0.000 claims abstract description 141
- 230000002401 inhibitory effect Effects 0.000 claims abstract description 18
- 230000005669 field effect Effects 0.000 claims description 336
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- 238000002955 isolation Methods 0.000 claims description 37
- 230000001242 postsynaptic effect Effects 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- BHPQYMZQTOCNFJ-UHFFFAOYSA-N Calcium cation Chemical compound [Ca+2] BHPQYMZQTOCNFJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910001424 calcium ion Inorganic materials 0.000 claims description 23
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 20
- 230000005294 ferromagnetic effect Effects 0.000 claims description 19
- 239000012528 membrane Substances 0.000 claims description 18
- 230000005764 inhibitory process Effects 0.000 claims description 13
- 229910001385 heavy metal Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 11
- 210000005215 presynaptic neuron Anatomy 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 230000008054 signal transmission Effects 0.000 claims description 6
- 230000003956 synaptic plasticity Effects 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 5
- 239000000395 magnesium oxide Substances 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 4
- 230000007774 longterm Effects 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910019236 CoFeB Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 230000003321 amplification Effects 0.000 claims description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- ZDZZPLGHBXACDA-UHFFFAOYSA-N [B].[Fe].[Co] Chemical compound [B].[Fe].[Co] ZDZZPLGHBXACDA-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 2
- 230000000638 stimulation Effects 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
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- 210000004205 output neuron Anatomy 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- 239000010409 thin film Substances 0.000 description 1
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Abstract
The invention discloses a neural network circuit and a Hall strip synapse based on SDSP and WTA algorithms; the neural network comprises an input layer neuron, a hidden layer neuron, a suppressed neuron, an output layer neuron and a Hall stripe synapse; the input layer neuron, the hidden layer neuron and the output layer neuron are activated neurons; the input layer neuron is connected with the hidden layer neuron through a first Hall strip synapse, the hidden layer neuron is connected with the inhibitory type neuron through a second Hall strip synapse, and the inhibitory type neuron is connected with the output layer neuron; the neural network analog circuit which is more in accordance with biology is constructed based on Hall strip synapses, and the neural network analog circuit has the advantages of low delay, easiness in integration and the like.
Description
Technical Field
The invention relates to the field of impulse neural networks, in particular to a neural network based on SDSP and WTA algorithms.
Background
With the arrival of big data age, the calculated amount to be processed by a computer is increased, the traditional von neumann system is separated from the computer, a great part of energy is wasted in the storage and the reading of the data, so that the computer energy efficiency is lower, the brain-like calculation is more and more widely valued due to the integration of the storage and the calculation, the brain-like calculation is similar to the intelligence of the brain, the brain-like calculation has the advantages of high complex problem solving capability, calculation efficiency, low energy efficiency and the like, the brain-like calculation mainly aims to develop a brain-like chip mainly composed of neurons and synapses, the Hall strip can be used as a good artificial synapse due to the advantages of nonvolatile storage, continuous change, simple preparation, easiness in connection and the like of the Hall strip, and the pulse neural network (Spiking Neural Network, SNN) can be used as a third-generation neural network to simulate the calculation of the nerve morphology according to biology, so that the energy consumption can be greatly reduced, and a platform for the nerve morphology calculation is provided for the brain-like calculation.
The pulse neural network is mainly implemented by software, so that time delay and energy consumption for processing large-scale data are greatly increased, and large-scale integration like hardware cannot be performed. The pulse neural network learning algorithm is mainly pulse time dependent plasticity (Spike Time Dependent Plasticity, STDP), and the principle is that the synaptic weight value is regulated by utilizing the time difference between the arrival of the pulse of the front neuron and the arrival of the pulse of the rear neuron, and the STDP algorithm regulates the synaptic weight value in a single mode, does not consider biological characteristics such as the membrane potential of the rear neuron and the like, and can not completely simulate the activity of the human brain neurons. Pulse-driven synaptic plasticity (Spike Driven Synaptic Plasticity, SDSP) and Winner Take All (WTA) are also one of the pulse neural network learning algorithms, the former principle being to update the synaptic weight value by using the membrane potential and calcium ion concentration of the pre-neuron pulse signal and the post-neuron, the latter principle being to activate the inhibitory neuron first, which will deliver the activation pulse signal to the corresponding output layer neuron to activate it, while delivering the inhibitory pulse signal to the other output layer neurons to inhibit its activation.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a neural network based on an SDSP and WTA algorithm, and provides a thought for realizing a neural network which is more suitable for biology, low delay and low energy consumption from hardware.
The invention relates to a neural network based on SDSP and WTA algorithm, which comprises an input layer neuron, a hidden layer neuron, a suppression type neuron, an output layer neuron and Hall stripe synapse; the input layer neuron, the hidden layer neuron and the output layer neuron are activated neurons; the input layer neuron is connected with the hidden layer neuron through a first Hall strip synapse, the hidden layer neuron is connected with the inhibitory type neuron through a second Hall strip synapse, and the inhibitory type neuron is connected with the output layer neuron;
the SDSP algorithm circuit is based on pulse-driven synaptic plasticity among the input layer neurons, the first Hall strip synapses and the hidden layer neurons; if the membrane potential of the postsynaptic neuron is greater than a threshold potential Vth, the calcium ion concentration of the postsynaptic neuron is between two concentration thresholds Capl and Caph, and at the moment, the presynaptic neuron transmits a pulse signal to the synapse and transmits an output enhancement signal Out_P to the Hall strip synapse, so that the Hall strip synapse is enhanced for a long time; if the membrane potential of the postsynaptic neuron is less than a threshold potential Vth, the calcium ion concentration of the postsynaptic neuron is between two concentration thresholds Cadl and Cadh, and at the moment, the presynaptic neuron transmits a pulse signal to the synapse and outputs an inhibition signal out_d to the hall bar synapse, so that long-term inhibition of the hall bar synapse can be caused;
wherein, the WTA algorithm circuit is used between the inhibitory type neuron and the output layer neuron based on the winner; a inhibitory neuron first activates, and transmits an activation pulse signal to a corresponding output layer neuron to activate the same, and after the inhibitory neuron is activated, the inhibitory neuron transmits an inhibition pulse signal to an output layer neuron other than the corresponding output layer neuron to inhibit the activation thereof.
Preferably, the pulse-driven synaptic plasticity SDSP algorithm circuit specifically comprises: comprising the following steps: first P-type field effect transistor P1, second P-type field effect transistor P2, third P-type field effect transistor P3, first N-type field effect transistor N1, second N-type field effect transistor N2, third N-type field effect transistor N3, fourth N-type field effect transistor N4, fourth P-type field effect transistor P4, fifth P-type field effect transistor P5, sixth P-type field effect transistor P6, fifth N-type field effect transistor N5, sixth N-type field effect transistor N6, seventh N-type field effect transistor N7, eighth N-type field effect transistor N8, seventh P-type field effect transistor P7, eighth P-type field effect transistor P8, ninth P-type field effect transistor P9, tenth N-type field effect transistor N10, eleventh N-type field effect transistor N11, twelfth N12, thirteenth N-type field effect transistor N13, fourteenth N-type field effect transistor N14, tenth P10 fifteenth N-type field effect transistor N15, first resistor R1, first capacitor C1, eleventh P-type field effect transistor P11, twelfth P-type field effect transistor P12, thirteenth P-type field effect transistor P13, sixteenth N-type field effect transistor N16, seventeenth N-type field effect transistor N17, eighteenth N-type field effect transistor N18, nineteenth N-type field effect transistor N19, fourteenth P-type field effect transistor P14, fifteenth P-type field effect transistor P15, sixteenth P-type field effect transistor P16, twenty N-type field effect transistor N20, twenty-first N-type field effect transistor N21, twenty-first N-type field effect transistor N22, twenty-first N-type field effect transistor N23, seventeenth P-type field effect transistor P17, twenty-first N-type field effect transistor N24, eighteenth P18, twenty-first N-type field effect transistor N25, second resistor R2, and second capacitor C2;
the source electrode of the first P-type field effect transistor P1 is connected with the source electrode of the second P-type field effect transistor P2, the source electrode of the third P-type field effect transistor P3 and a power supply VCC, the grid electrode of the first P-type field effect transistor P1 is connected with the drain electrode of the first P-type field effect transistor P1, the grid electrode of the second P-type field effect transistor P2 and the drain electrode of the first N-type field effect transistor N1, the drain electrode of the second P-type field effect transistor P2 is connected with the drain electrode of the second N-type field effect transistor N2, the grid electrode of the third P-type field effect transistor P3 is connected with the drain electrode of the fourth N-type field effect transistor N4 and used as a first output end Out1, the grid electrode of the first N-type field effect transistor N1 is connected with the post-synaptic neuron membrane potential Vpost, the source electrode of the first N-type field effect transistor N1 is connected with the source electrode of the second N-type field effect transistor P2, the drain electrode of the third N-type field effect transistor N3 is connected with the grid electrode of the third P-type field effect transistor P3, the grid electrode of the third P-type field effect transistor P3 is connected with the fourth N-type field effect transistor P4,
the source electrode of the fourth P-type field effect transistor P4 is connected with the source electrode of the fifth P-type field effect transistor P5, the source electrode of the sixth P-type field effect transistor P6 and a power supply VCC, the grid electrode of the fourth P-type field effect transistor P4 is connected with the drain electrode of the fourth P-type field effect transistor P4, the grid electrode of the fifth P-type field effect transistor P5 and the drain electrode of the fifth N-type field effect transistor N5, the drain electrode of the fifth P-type field effect transistor P5 is connected with the drain electrode of the sixth N-type field effect transistor N6, the grid electrode of the sixth P-type field effect transistor P6 is connected with the drain electrode of the eighth N-type field effect transistor N8 and used as a second output end Out2, the grid electrode of the fifth N-type field effect transistor N5 is connected with the post-synaptic neuron calcium ion concentration Capost, the source electrode of the fifth N-type field effect transistor N5 is connected with the source electrode of the sixth N-type field effect transistor N6, the drain electrode of the seventh N-type field effect transistor N7 is connected with the grid electrode of the seventh N-type field effect transistor P8, the grid electrode of the seventh N-type field effect transistor P8 is connected with the fifth N-type field effect transistor P8,
the source electrode of the seventh P-type field effect transistor P7 is connected with the source electrode of the eighth P-type field effect transistor P8, the source electrode of the ninth P-type field effect transistor P9 and a power supply VCC, the grid electrode of the seventh P-type field effect transistor P7 is connected with the drain electrode of the seventh P-type field effect transistor P7, the grid electrode of the eighth P-type field effect transistor P8 and the drain electrode of the ninth N-type field effect transistor N9, the drain electrode of the eighth P-type field effect transistor P8 is connected with the drain electrode of the tenth N-type field effect transistor N10, the grid electrode of the ninth P-type field effect transistor P9 is connected with the drain electrode of the twelfth N-type field effect transistor N12 and used as a third output end Out3, the grid electrode of the ninth N-type field effect transistor N9 is connected with the post-synaptic neuron calcium ion concentration Capost, the source electrode of the ninth N-type field effect transistor N9 is connected with the source electrode of the tenth N-type field effect transistor N10, the drain electrode of the eleventh N-type field effect transistor N11, the grid electrode of the tenth N-type field effect transistor N10 is connected with the gate electrode of the eleventh N-type field effect transistor N12, the drain electrode of the eleventh N-type field effect transistor N11 is connected with the drain electrode of the twelfth N-type field effect transistor P12,
the drain electrode of the thirteenth N-type field effect transistor N13 is connected with the front neuron stimulation Pre, the grid electrode of the thirteenth N-type field effect transistor N13 is connected with the first output end Out1, the source electrode of the thirteenth N-type field effect transistor N13 is connected with the drain electrode of the fourteenth N-type field effect transistor N14, the grid electrode of the fourteenth N-type field effect transistor N14 is connected with the second output end Out2, the source electrode of the fourteenth N-type field effect transistor N14 is connected with the source electrode of the tenth P-type field effect transistor P10, the grid electrode of the tenth P-type field effect transistor P10 is connected with the third output end Out3, the drain electrode of the tenth P-type field effect transistor P10 is connected with the grid electrode of the fifteenth N-type field effect transistor N15, the source electrode of the fifteenth N-type field effect transistor N15 is connected with one end of the first resistor R1, one end of the first capacitor C1 and the output enhancement signal Out_P are connected, the other end of the first resistor R1 is connected with the other end of the first capacitor C1 and is grounded,
the source electrode of the eleventh P-type field effect transistor P11 is connected with the source electrode of the twelfth P-type field effect transistor P12, the source electrode of the thirteenth P-type field effect transistor P13 and the power supply VCC, the grid electrode of the eleventh P-type field effect transistor P11 is connected with the drain electrode of the eleventh P-type field effect transistor P11, the grid electrode of the twelfth P-type field effect transistor P12 and the drain electrode of the sixteenth N-type field effect transistor N16, the drain electrode of the twelfth P-type field effect transistor P12 is connected with the drain electrode of the seventeenth N-type field effect transistor N17, the grid electrode of the thirteenth P-type field effect transistor P13 is connected with the drain electrode of the nineteenth N-type field effect transistor N19 and serves as a fourth output end Out4, the grid electrode of the sixteenth N-type field effect transistor N16 is connected with the post-synaptic neuron calcium ion concentration cap, the source electrode of the sixteenth N-type field effect transistor N16 is connected with the source electrode of the seventeenth N-type field effect transistor N17, the drain electrode of the sixteenth N-type field effect transistor N18 is connected with the gate electrode of the nineteenth N-type field effect transistor N19, the eighteenth N-type field effect transistor N18 is connected with the nineteenth source electrode of the nineteenth N-type field effect transistor N19,
the source electrode of the fourteenth P-type field effect transistor P14 is connected with the source electrode of the fifteenth P-type field effect transistor P15, the source electrode of the sixteenth P-type field effect transistor P16 and a power supply VCC, the grid electrode of the fourteenth P-type field effect transistor P14 is connected with the drain electrode of the fourteenth P-type field effect transistor P14, the grid electrode of the fifteenth P-type field effect transistor P15 and the drain electrode of the twenty-second N-type field effect transistor N20, the drain electrode of the fifteenth P-type field effect transistor P15 is connected with the drain electrode of the twenty-first N-type field effect transistor N21, the grid electrode of the sixteenth P-type field effect transistor P16 is connected with the drain electrode of the twenty-first N-type field effect transistor N23 and serves as a fifth output end Out5, the grid electrode of the twenty-first N-type field effect transistor N20 is connected with the post-synaptic calcium ion concentration cap, the source electrode of the twenty-first N-second N-type field effect transistor N20 is connected with the source electrode of the twenty-second N-type field effect transistor N21, the drain electrode of the twenty-second N-type field effect transistor N22 is connected with the twenty-second N-type field effect transistor N22, the twenty-second N-type field effect transistor N23 is connected with the drain electrode of the twenty-second N-second P-type field effect transistor N22,
the source electrode of the seventeenth P-type field effect transistor P17 is connected with the front neuron stimulus Pre, the grid electrode of the seventeenth P-type field effect transistor P17 is connected with the first output end Out1, the drain electrode of the seventeenth P-type field effect transistor P17 is connected with the drain electrode of the twenty-fourth N-type field effect transistor N24, the grid electrode of the twenty-fourth N-type field effect transistor N24 is connected with the fourth output end Out4, the source electrode of the twenty-fourth N-type field effect transistor N24 is connected with the source electrode of the eighteenth P-type field effect transistor P18, the grid electrode of the eighteenth P-type field effect transistor P18 is connected with the fifth output end Out5, the drain electrode of the eighteenth P-type field effect transistor P18 is connected with the grid electrode of the twenty-fifth N-type field effect transistor N25, the drain electrode of the twenty-fifth N-type field effect transistor N25 is connected with the power supply VCC, the source electrode of the twenty-fifth N-type field effect transistor N25 is connected with one end of the second resistor R2, one end of the second capacitor C2 and the output inhibition signal Out_D are connected with the other end of the second resistor R2 and grounded.
Preferably, the winner general-eating WTA algorithm circuit specifically comprises: sixteenth N-type field effect transistor N26, third resistor R3, third capacitor C3, seventeenth N-type field effect transistor N27, fourth resistor R4, fourth capacitor C4, twenty-eighth N-type field effect transistor N28, fifth resistor R5, fifth capacitor C5, first three input OR gate OR;
the gate of the twenty-first N-type field effect transistor N26 is connected to the gate of the twenty-first N-type field effect transistor N27, the gate of the twenty-first N-type field effect transistor N28, the output of the first third input OR gate OR, the drain of the twenty-first N-type field effect transistor N26 is connected to the first input signal In1 of the rear neuron, one end of the third resistor R3, one end of the third capacitor C3, the first input of the first third input OR gate OR, the source of the twenty-first N-type field effect transistor N26 is connected to the other end of the third resistor R3, the other end of the third capacitor C3 and the ground, the drain of the twenty-first N-type field effect transistor N27 is connected to the second input signal In2 of the rear neuron, one end of the fourth resistor R4, one end of the fourth capacitor C4, the second input of the first third input OR gate OR, the source of the second seventeenth N-type field effect transistor N27 is connected to the other end of the fourth resistor R4, the other end of the fourth capacitor C4 and the other end of the fifth capacitor C5 is connected to the ground, and the drain of the second N-type field effect transistor N28 is connected to the fifth input signal In3 of the rear neuron, the fifth input of the fifth input OR gate OR the fifth input of the fifth resistor R5.
Preferably, the Hall sensor comprises a Hall strip and a signal transmission unit;
the Hall strip consists of four top electrodes from top to bottom, a metal isolation layer, a ferromagnetic layer, a heavy metal layer, a metal isolation layer, a ferromagnetic layer, an oxide isolation layer and a metal isolation layer;
the metal isolation layer of the Hall strip is tantalum Ta, and the thickness of the metal isolation layer is between 0.2nm and 3nm;
the ferromagnetic layer of the Hall strip refers to one of cobalt iron boron CoFeB, cobalt Co and platinum Pt, and the thickness of the ferromagnetic layer is between 0.3nm and 1.2 nm;
the heavy metal layer of the Hall strip is platinum Pt, and the thickness of the heavy metal layer is 0.3nm;
the oxide isolation layer of the Hall strip is magnesium oxide MgO, and the thickness of the oxide isolation layer is 3nm;
the signal transmission unit is used for representing the connection strength between the front neuron and the rear neuron according to the weight value of the Hall strip, applying pulse current signals of the front neuron to two ends of the Hall strip, and carrying out differential amplification on voltage signals of the other two ends of the Hall strip after the pulse current signals are regulated to transmit the voltage signals to the rear neuron.
Preferably, the tip electrode is one of platinum Pt, gold Au, copper Cu, aluminum Al, specifically: gold Au of 20nm thickness was grown on titanium Ti of 5nm thickness.
Compared with the prior art, the technical scheme provided by the invention has the following effects:
the invention provides a neural network circuit and a Hall stripe synapse based on an SDSP and WTA algorithm, wherein a hardware simulation circuit is used for realizing an SDSP and WTA learning algorithm module, taking biological characteristics of neurons after synapses into consideration, and a first-level inhibitory type neuron is added between a hidden layer neuron and an output layer neuron, so that an activation pulse signal is sent to a corresponding output layer neuron and is activated only if one inhibitory type neuron is activated first, and an inhibition pulse signal is sent to the output layer neuron outside the corresponding output layer neuron and is inhibited from being activated. The Hall strip is used as synapse, and the Hall resistance value is a synapse weight value, so that the method has the advantages of integration, low delay, low power consumption and the like, and the impulse neural network is more similar to a real biological neural network.
Drawings
FIG. 1 is a perspective view of a neural network framework
FIG. 2 is a schematic diagram of a Hall strip according to an embodiment
FIG. 3 is a schematic diagram showing the structure of a three-synapse of an embodiment
FIG. 4 is a schematic diagram of an analog circuit structure of a four SDSP learning algorithm according to an embodiment
Fig. 5 is a schematic diagram of a simulation circuit structure of a five WTA learning algorithm according to an embodiment
Wherein: 1. top electrode, 2, metal isolation layer, 3, ferromagnetic layer, 4, heavy metal layer, 5, metal isolation layer, 6, ferromagnetic layer, 7, oxide isolation layer, 8, metal isolation layer, 9, electrode plate, 10, hall bar.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be further described in detail with reference to the accompanying drawings in the examples of the present invention, and naturally, the specific embodiments described herein are part of the present invention, but not all embodiments, and the detailed description of the embodiments below is only for illustrating the specific embodiments of the present invention and is not intended to limit the scope of the present invention as claimed. Based on the embodiments of the present invention, those skilled in the art may make non-creative modifications to the technical solutions described in the embodiments or make equivalent substitutions for some technical features thereof, which are all within the protection scope of the present invention.
The neural network provided by the invention is based on Hall stripe synapses, combines SDSP and WTA learning algorithms, and has the advantages of low delay, low energy consumption and the like compared with a common neural network.
The invention provides a neural network circuit and a Hall stripe synapse based on SDSP and WTA algorithms, as shown in figure 1, a neuron, a synapse and a learning algorithm circuit; the Hall strip is used as synapses due to the advantages of nonvolatile storage, continuous change and the like of Hall resistances, the learning algorithm circuit comprises a pulse-driven synapse plasticity SDSP algorithm circuit and a winner general eating WTA algorithm circuit, the pulse-driven synapse plasticity SDSP algorithm is used for adjusting a front neuron pulse signal according to a weight value and then transmitting the front neuron pulse signal to a rear neuron, and is also used for receiving the membrane potential and the calcium ion concentration of the rear neuron, updating the synapse weight value according to the membrane potential and the calcium ion concentration of the front neuron pulse signal and the rear neuron, and the winner general eating WTA algorithm is used for creating a winner general eating network through strong inhibition connection between the inhibition type neuron and all neurons in an output layer.
As shown in fig. 3, which is a schematic structural diagram of a hall bar synapse, the change of the weight value of the hall bar synapse can change the pulse current amplitude applied at two ends of the hall bar to flip the magnetic moment of the hall bar, so as to change the resistance value of the hall bar, and the synapse includes: hall bar and signal transmission unit; as shown in fig. 2, the hall bar 10 includes four top electrodes 1, a metal isolation layer 2, a ferromagnetic layer 3, a heavy metal layer 4, a metal isolation layer 5, a ferromagnetic layer 6, an oxide isolation layer 7, a metal isolation layer 8, the oxide isolation layer 7 grown on the metal isolation layer 8, the ferromagnetic layer 6 grown on the oxide isolation layer 7, the metal isolation layer 5 grown on the ferromagnetic layer 6, the heavy metal layer 4 grown on the metal isolation layer 5, the ferromagnetic layer 3 grown on the heavy metal layer 4, the metal isolation layer 2 grown on the ferromagnetic layer 3, the top electrode 1 grown on the metal isolation layer 2, and the thickness of the prepared thin films are all on the order of nanometers. Wherein the material of the top electrode 3 is Au and Ti, the gold Au with the thickness of 20nm grows on the titanium Ti with the thickness of 5nm, the material of the metal isolation layer 4, the metal isolation layer 7 and the metal isolation layer 10 is Ta, the thickness of the metal isolation layer is between 0.2nm and 3nm, the material of the ferromagnetic layer 5 and the ferromagnetic layer 8 is CoFeB, co and Pt, the thickness of the ferromagnetic layer is between 0.3nm and 1.2nm, the material of the heavy metal layer 6 is Pt, the thickness of the heavy metal layer is 0.3nm, the material of the oxide isolation layer 7 is MgO for enhancing magnetic anisotropy, and the thickness of the oxide isolation layer is 3nm.
The signal transmission unit is used for representing the connection strength between the front neuron and the rear neuron according to the weight value of the Hall strip, applying pulse current signals of the front neuron to two ends of the Hall strip through the electrode sheet 9, and carrying out differential amplification on voltage signals of the other two ends of the Hall strip 10 to transmit the voltage signals to the rear neuron after the regulation.
As shown in fig. 4, in the circuit in the initial state, when the membrane potential Vpost of the post-synaptic neuron is greater than the membrane potential Vth of the post-synaptic neuron, the calcium ion concentration Capost of the post-synaptic neuron is greater than the concentration threshold Capl, the calcium ion concentration Capost of the post-synaptic neuron is less than the concentration threshold Caph, the output terminals Out1 and Out2 become high, the output terminal Out3 becomes low, the gate-source voltages of the N-type field effect transistors N13 and N14 reach the on voltage, the gate-source voltage of the P-type field effect transistor P10 reaches the on voltage, the MOS transistors N13, N14 and P10 are turned on, the Pre-synaptic neuron uses a stimulus signal Pre, the gate-source voltage of the N-type field effect transistor N15 reaches the on voltage, the MOS transistor N15 is turned on, the capacitor C1 enters the charging state, the voltages at both ends of the capacitor C1 gradually rise to VCC, the output enhancement signal_p gradually rises to VCC, and when the Pre-signal is ended, the capacitor C1 gradually drops to zero, the voltage at both ends of the capacitor C1 gradually drops to VCC. When the membrane potential Vpost of the post-synaptic neuron is smaller than the membrane potential Vth of the post-synaptic neuron, the calcium ion concentration Capost of the post-synaptic neuron is larger than the concentration threshold Cadl, the calcium ion concentration Capost of the post-synaptic neuron is smaller than the concentration threshold Cadh, the output ends Out1 and Out5 become low level, the output end Out4 becomes high level through a comparison circuit, the gate-source voltages of the P-type field effect transistors P17 and P18 reach the starting voltage, the gate-source voltage of the N-type field effect transistor N24 reach the starting voltage, the MOS transistors P17, P18 and N24 are conducted, the Pre-synaptic neuron comes to a stimulus signal Pre, the gate-source voltage of the N-type field effect transistor N25 reaches the starting voltage, the MOS transistor N25 is conducted and the capacitor C2 enters a charging state, the voltage at two ends of the capacitor C1 gradually rises to VCC, the output suppression signal out_d gradually rises to VCC, and when the Pre signal ends, the capacitor C2 gradually discharges through the resistor R2, the voltage at two ends of the capacitor C2 gradually drops to zero, the output suppression signal out_d gradually drops to VCC.
Specifically, when the membrane potential of the postsynaptic neuron is greater than a threshold potential Vth, the postsynaptic neuron calcium ion concentration is between two concentration thresholds, capl and caps, and at this time, the presynaptic neuron transmits a pulse signal to the synapse and transmits an output enhancement signal out_p to the synapse, thereby causing long-term enhancement of the synapse; when the membrane potential of the postsynaptic neuron is smaller than a threshold potential Vth, the calcium ion concentration of the postsynaptic neuron is between two concentration thresholds Cadl and Cadh, and at the moment, the presynaptic neuron transmits a pulse signal to the synapse and transmits an output inhibition signal Out_D to the synapse, so that long-term inhibition of the synapse is caused; when the membrane potential of the postsynaptic neuron is larger than a threshold potential Vth, the calcium ion concentration of the postsynaptic neuron is smaller than a concentration threshold Capl or larger than a concentration threshold Caph, and the synaptic weight value is not updated; when the membrane potential of the postsynaptic neuron is less than a threshold voltage Vth, the postneuronal calcium ion concentration is less than a concentration threshold Cadl or greater than a concentration threshold Cadh, and the synaptic weight is not updated.
In the initial state of the circuit, as shown In fig. 5, input end signals In1, in2 and In3 are low, three input OR gate OR output signals are low, gate-source voltages of N-type field effect transistors N26, N27 and N28 do not reach the turn-on voltage, MOS transistors N26, N27 and N28 are all turned off, when input end signals In1, in2 and In3 become high, in1> In2> In3, input end signals In1, in2 and In3 charge capacitors C3, C4 and C5 respectively, voltages at two ends of capacitors C3, C4 and C5 are gradually increased, voltages at two ends of capacitor C3, C4 and C5 are the same type and the same value, the output neurons corresponding to capacitor C3 are first activated, three input OR gate OR output signals become high, the sources of N-type field effect transistors N26, N27 and N28 reach the turn-on voltage, and the N26, N27 and N28 are turned-off, the capacitors C3 and C4 and C5 are gradually reduced, and the voltages at two ends of capacitor C3 and C4 and C5 are gradually reduced, so that all the voltages at two ends of capacitor C3 and C4 and C5 are gradually reduced to zero.
Claims (5)
1. The neural network device based on SDSP and WTA algorithm is characterized in that: the neural network comprises an input layer neuron, a hidden layer neuron, a suppressed neuron, an output layer neuron and a Hall stripe synapse; the input layer neuron, the hidden layer neuron and the output layer neuron are activated neurons; the input layer neuron is connected with the hidden layer neuron through a first Hall strip synapse, the hidden layer neuron is connected with the inhibitory type neuron through a second Hall strip synapse, and the inhibitory type neuron is connected with the output layer neuron;
the SDSP algorithm circuit is based on pulse-driven synaptic plasticity among the input layer neurons, the first Hall strip synapses and the hidden layer neurons; if the membrane potential of the postsynaptic neuron is greater than a threshold potential Vth, the calcium ion concentration of the postsynaptic neuron is between two concentration thresholds Capl and Caph, and at the moment, the presynaptic neuron transmits a pulse signal to the synapse and transmits an output enhancement signal Out_P to the Hall strip synapse, so that the Hall strip synapse is enhanced for a long time; if the membrane potential of the postsynaptic neuron is less than a threshold potential Vth, the calcium ion concentration of the postsynaptic neuron is between two concentration thresholds Cadl and Cadh, and at the moment, the presynaptic neuron transmits a pulse signal to the synapse and outputs an inhibition signal out_d to the hall bar synapse, so that long-term inhibition of the hall bar synapse can be caused;
wherein, the WTA algorithm circuit is used between the inhibitory type neuron and the output layer neuron based on the winner; a inhibitory neuron first activates, and transmits an activation pulse signal to a corresponding output layer neuron to activate the same, and after the inhibitory neuron is activated, the inhibitory neuron transmits an inhibition pulse signal to an output layer neuron other than the corresponding output layer neuron to inhibit the activation thereof.
2. The SDSP and WTA algorithm based neural network device of claim 1, wherein: the pulse-driven synaptic plasticity SDSP algorithm circuit specifically comprises the following components: comprising the following steps: first P-type field effect transistor P1, second P-type field effect transistor P2, third P-type field effect transistor P3, first N-type field effect transistor N1, second N-type field effect transistor N2, third N-type field effect transistor N3, fourth N-type field effect transistor N4, fourth P-type field effect transistor P4, fifth P-type field effect transistor P5, sixth P-type field effect transistor P6, fifth N-type field effect transistor N5, sixth N-type field effect transistor N6, seventh N-type field effect transistor N7, eighth N-type field effect transistor N8, seventh P-type field effect transistor P7, eighth P-type field effect transistor P8, ninth P-type field effect transistor P9, tenth N-type field effect transistor N10, eleventh N-type field effect transistor N11, twelfth N12, thirteenth N-type field effect transistor N13, fourteenth N-type field effect transistor N14, tenth P10 fifteenth N-type field effect transistor N15, first resistor R1, first capacitor C1, eleventh P-type field effect transistor P11, twelfth P-type field effect transistor P12, thirteenth P-type field effect transistor P13, sixteenth N-type field effect transistor N16, seventeenth N-type field effect transistor N17, eighteenth N-type field effect transistor N18, nineteenth N-type field effect transistor N19, fourteenth P-type field effect transistor P14, fifteenth P-type field effect transistor P15, sixteenth P-type field effect transistor P16, twenty N-type field effect transistor N20, twenty-first N-type field effect transistor N21, twenty-first N-type field effect transistor N22, twenty-first N-type field effect transistor N23, seventeenth P-type field effect transistor P17, twenty-first N-type field effect transistor N24, eighteenth P18, twenty-first N-type field effect transistor N25, second resistor R2, and second capacitor C2;
the source electrode of the first P-type field effect transistor P1 is connected with the source electrode of the second P-type field effect transistor P2, the source electrode of the third P-type field effect transistor P3 and a power supply VCC, the grid electrode of the first P-type field effect transistor P1 is connected with the drain electrode of the first P-type field effect transistor P1, the grid electrode of the second P-type field effect transistor P2 and the drain electrode of the first N-type field effect transistor N1, the drain electrode of the second P-type field effect transistor P2 is connected with the drain electrode of the second N-type field effect transistor N2, the grid electrode of the third P-type field effect transistor P3 is connected with the drain electrode of the fourth N-type field effect transistor N4 and used as a first output end Out1, the grid electrode of the first N-type field effect transistor N1 is connected with the post-synaptic neuron membrane potential Vpost, the source electrode of the first N-type field effect transistor N1 is connected with the source electrode of the second N-type field effect transistor P2, the drain electrode of the third N-type field effect transistor N3 is connected with the grid electrode of the third P-type field effect transistor P3, the grid electrode of the third P-type field effect transistor P3 is connected with the fourth N-type field effect transistor P4,
the source electrode of the fourth P-type field effect transistor P4 is connected with the source electrode of the fifth P-type field effect transistor P5, the source electrode of the sixth P-type field effect transistor P6 and a power supply VCC, the grid electrode of the fourth P-type field effect transistor P4 is connected with the drain electrode of the fourth P-type field effect transistor P4, the grid electrode of the fifth P-type field effect transistor P5 and the drain electrode of the fifth N-type field effect transistor N5, the drain electrode of the fifth P-type field effect transistor P5 is connected with the drain electrode of the sixth N-type field effect transistor N6, the grid electrode of the sixth P-type field effect transistor P6 is connected with the drain electrode of the eighth N-type field effect transistor N8 and used as a second output end Out2, the grid electrode of the fifth N-type field effect transistor N5 is connected with the post-synaptic neuron calcium ion concentration Capost, the source electrode of the fifth N-type field effect transistor N5 is connected with the source electrode of the sixth N-type field effect transistor N6, the drain electrode of the seventh N-type field effect transistor N7 is connected with the grid electrode of the seventh N-type field effect transistor P8, the grid electrode of the seventh N-type field effect transistor P8 is connected with the fifth N-type field effect transistor P8,
the source electrode of the seventh P-type field effect transistor P7 is connected with the source electrode of the eighth P-type field effect transistor P8, the source electrode of the ninth P-type field effect transistor P9 and a power supply VCC, the grid electrode of the seventh P-type field effect transistor P7 is connected with the drain electrode of the seventh P-type field effect transistor P7, the grid electrode of the eighth P-type field effect transistor P8 and the drain electrode of the ninth N-type field effect transistor N9, the drain electrode of the eighth P-type field effect transistor P8 is connected with the drain electrode of the tenth N-type field effect transistor N10, the grid electrode of the ninth P-type field effect transistor P9 is connected with the drain electrode of the twelfth N-type field effect transistor N12 and used as a third output end Out3, the grid electrode of the ninth N-type field effect transistor N9 is connected with the post-synaptic neuron calcium ion concentration Capost, the source electrode of the ninth N-type field effect transistor N9 is connected with the source electrode of the tenth N-type field effect transistor N10, the drain electrode of the eleventh N-type field effect transistor N11, the grid electrode of the tenth N-type field effect transistor N10 is connected with the gate electrode of the eleventh N-type field effect transistor N12, the drain electrode of the eleventh N-type field effect transistor N11 is connected with the drain electrode of the twelfth N-type field effect transistor P12,
the drain electrode of the thirteenth N-type field effect transistor N13 is connected with the front neuron stimulation Pre, the grid electrode of the thirteenth N-type field effect transistor N13 is connected with the first output end Out1, the source electrode of the thirteenth N-type field effect transistor N13 is connected with the drain electrode of the fourteenth N-type field effect transistor N14, the grid electrode of the fourteenth N-type field effect transistor N14 is connected with the second output end Out2, the source electrode of the fourteenth N-type field effect transistor N14 is connected with the source electrode of the tenth P-type field effect transistor P10, the grid electrode of the tenth P-type field effect transistor P10 is connected with the third output end Out3, the drain electrode of the tenth P-type field effect transistor P10 is connected with the grid electrode of the fifteenth N-type field effect transistor N15, the source electrode of the fifteenth N-type field effect transistor N15 is connected with one end of the first resistor R1, one end of the first capacitor C1 and the output enhancement signal Out_P are connected, the other end of the first resistor R1 is connected with the other end of the first capacitor C1 and is grounded,
the source electrode of the eleventh P-type field effect transistor P11 is connected with the source electrode of the twelfth P-type field effect transistor P12, the source electrode of the thirteenth P-type field effect transistor P13 and the power supply VCC, the grid electrode of the eleventh P-type field effect transistor P11 is connected with the drain electrode of the eleventh P-type field effect transistor P11, the grid electrode of the twelfth P-type field effect transistor P12 and the drain electrode of the sixteenth N-type field effect transistor N16, the drain electrode of the twelfth P-type field effect transistor P12 is connected with the drain electrode of the seventeenth N-type field effect transistor N17, the grid electrode of the thirteenth P-type field effect transistor P13 is connected with the drain electrode of the nineteenth N-type field effect transistor N19 and serves as a fourth output end Out4, the grid electrode of the sixteenth N-type field effect transistor N16 is connected with the post-synaptic neuron calcium ion concentration cap, the source electrode of the sixteenth N-type field effect transistor N16 is connected with the source electrode of the seventeenth N-type field effect transistor N17, the drain electrode of the sixteenth N-type field effect transistor N18 is connected with the gate electrode of the nineteenth N-type field effect transistor N19, the eighteenth N-type field effect transistor N18 is connected with the nineteenth source electrode of the nineteenth N-type field effect transistor N19,
the source electrode of the fourteenth P-type field effect transistor P14 is connected with the source electrode of the fifteenth P-type field effect transistor P15, the source electrode of the sixteenth P-type field effect transistor P16 and a power supply VCC, the grid electrode of the fourteenth P-type field effect transistor P14 is connected with the drain electrode of the fourteenth P-type field effect transistor P14, the grid electrode of the fifteenth P-type field effect transistor P15 and the drain electrode of the twenty-second N-type field effect transistor N20, the drain electrode of the fifteenth P-type field effect transistor P15 is connected with the drain electrode of the twenty-first N-type field effect transistor N21, the grid electrode of the sixteenth P-type field effect transistor P16 is connected with the drain electrode of the twenty-first N-type field effect transistor N23 and serves as a fifth output end Out5, the grid electrode of the twenty-first N-type field effect transistor N20 is connected with the post-synaptic calcium ion concentration cap, the source electrode of the twenty-first N-second N-type field effect transistor N20 is connected with the source electrode of the twenty-second N-type field effect transistor N21, the drain electrode of the twenty-second N-type field effect transistor N22 is connected with the twenty-second N-type field effect transistor N22, the twenty-second N-type field effect transistor N23 is connected with the drain electrode of the twenty-second N-second P-type field effect transistor N22,
the source electrode of the seventeenth P-type field effect transistor P17 is connected with the front neuron stimulus Pre, the grid electrode of the seventeenth P-type field effect transistor P17 is connected with the first output end Out1, the drain electrode of the seventeenth P-type field effect transistor P17 is connected with the drain electrode of the twenty-fourth N-type field effect transistor N24, the grid electrode of the twenty-fourth N-type field effect transistor N24 is connected with the fourth output end Out4, the source electrode of the twenty-fourth N-type field effect transistor N24 is connected with the source electrode of the eighteenth P-type field effect transistor P18, the grid electrode of the eighteenth P-type field effect transistor P18 is connected with the fifth output end Out5, the drain electrode of the eighteenth P-type field effect transistor P18 is connected with the grid electrode of the twenty-fifth N-type field effect transistor N25, the drain electrode of the twenty-fifth N-type field effect transistor N25 is connected with the power supply VCC, the source electrode of the twenty-fifth N-type field effect transistor N25 is connected with one end of the second resistor R2, one end of the second capacitor C2 and the output inhibition signal Out_D are connected with the other end of the second resistor R2 and grounded.
3. The SDSP and WTA algorithm based neural network device of claim 1, wherein: the winner takes the WTA algorithm circuit as follows: sixteenth N-type field effect transistor N26, third resistor R3, third capacitor C3, seventeenth N-type field effect transistor N27, fourth resistor R4, fourth capacitor C4, twenty-eighth N-type field effect transistor N28, fifth resistor R5, fifth capacitor C5, first three input OR gate OR;
the gate of the twenty-first N-type field effect transistor N26 is connected to the gate of the twenty-first N-type field effect transistor N27, the gate of the twenty-first N-type field effect transistor N28, the output of the first third input OR gate OR, the drain of the twenty-first N-type field effect transistor N26 is connected to the first input signal In1 of the rear neuron, one end of the third resistor R3, one end of the third capacitor C3, the first input of the first third input OR gate OR, the source of the twenty-first N-type field effect transistor N26 is connected to the other end of the third resistor R3, the other end of the third capacitor C3 and the ground, the drain of the twenty-first N-type field effect transistor N27 is connected to the second input signal In2 of the rear neuron, one end of the fourth resistor R4, one end of the fourth capacitor C4, the second input of the first third input OR gate OR, the source of the second seventeenth N-type field effect transistor N27 is connected to the other end of the fourth resistor R4, the other end of the fourth capacitor C4 and the other end of the fifth capacitor C5 is connected to the ground, and the drain of the second N-type field effect transistor N28 is connected to the fifth input signal In3 of the rear neuron, the fifth input of the fifth input OR gate OR the fifth input of the fifth resistor R5.
4. A hall bar synapse characterized by: for implementing any one of claims 1 to 3 comprising a hall bar and a signal transmission unit;
the Hall strip consists of four top electrodes from top to bottom, a metal isolation layer, a ferromagnetic layer, a heavy metal layer, a metal isolation layer, a ferromagnetic layer, an oxide isolation layer and a metal isolation layer;
the metal isolation layer of the Hall strip is tantalum Ta, and the thickness of the metal isolation layer is between 0.2nm and 3nm;
the ferromagnetic layer of the Hall strip refers to one of cobalt iron boron CoFeB, cobalt Co and platinum Pt, and the thickness of the ferromagnetic layer is between 0.3nm and 1.2 nm;
the heavy metal layer of the Hall strip is platinum Pt, and the thickness of the heavy metal layer is 0.3nm;
the oxide isolation layer of the Hall strip is magnesium oxide MgO, and the thickness of the oxide isolation layer is 3nm;
the signal transmission unit is used for representing the connection strength between the front neuron and the rear neuron according to the weight value of the Hall strip, applying pulse current signals of the front neuron to two ends of the Hall strip, and carrying out differential amplification on voltage signals of the other two ends of the Hall strip after the pulse current signals are regulated to transmit the voltage signals to the rear neuron.
5. A hall bar synapse as set forth in claim 4 wherein: the top electrode is one of platinum Pt, gold Au, copper Cu and aluminum Al, and specifically comprises the following components: gold Au of 20nm thickness was grown on titanium Ti of 5nm thickness.
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| JP2000215264A (en) * | 1999-01-25 | 2000-08-04 | Fuji Xerox Co Ltd | Signal processing unit and circuit therefor |
| CN112270409A (en) * | 2020-10-19 | 2021-01-26 | 杭州电子科技大学 | Unsupervised learning synapse unit circuit based on Hall strip |
| CN112738325A (en) * | 2020-12-25 | 2021-04-30 | 浙江工业大学 | Intelligent LED identification method based on Android mobile phone |
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| JP2000215264A (en) * | 1999-01-25 | 2000-08-04 | Fuji Xerox Co Ltd | Signal processing unit and circuit therefor |
| CN112270409A (en) * | 2020-10-19 | 2021-01-26 | 杭州电子科技大学 | Unsupervised learning synapse unit circuit based on Hall strip |
| CN112738325A (en) * | 2020-12-25 | 2021-04-30 | 浙江工业大学 | Intelligent LED identification method based on Android mobile phone |
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