CN113552970A

CN113552970A - Display substrate and display device

Info

Publication number: CN113552970A
Application number: CN202110888129.0A
Authority: CN
Inventors: 张顺; 张元其; 何帆
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-08-03
Filing date: 2021-08-03
Publication date: 2021-10-26
Anticipated expiration: 2041-08-03
Also published as: CN113552970B; WO2023011284A1

Abstract

The embodiment of the disclosure provides a display substrate and a display device. The display substrate includes: a substrate base plate, the substrate base plate comprising: the display device comprises a display area, a bending area connected with one side of the display area, and an extension area connected with one side of the bending area far away from the display area; the touch routing group is positioned in the extension area and comprises a plurality of touch routing lines which extend along a first direction and are sequentially arranged along a second direction; the first floating wire group is located on at least one side of the touch control wire group and comprises at least one first floating wire extending along the first direction, the first direction is a direction pointing to the bending area and the extending area from the display area, and the at least one first floating wire is electrically insulated from the touch control wire.

Description

Display substrate and display device

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a display substrate and a display device.

Background

With the development of Active-matrix organic light-emitting diode (AMOLED) towards the direction of light and thin, the On cell technology will gradually replace the existing Touch Screen (TSP) external hanging mode, the On cell technology is an integrated technology of Touch Screen, and the Touch Screen electrodes and the routing are formed On the packaging layer by using the photolithography process.

Disclosure of Invention

The embodiment of the present disclosure provides a display substrate, which includes:

a substrate base plate, the substrate base plate comprising: the display device comprises a display area, a bending area connected with one side of the display area, and an extension area connected with one side of the bending area far away from the display area;

the touch routing group is positioned in the extension area and comprises a plurality of touch routing lines which extend along a first direction and are sequentially arranged along a second direction;

the first floating wire group is located on at least one side of the touch control wire group and comprises at least one first floating wire extending along the first direction, the first direction is a direction pointing to the bending area and the extending area from the display area, and the at least one first floating wire is electrically insulated from the touch control wire.

In a possible implementation manner, the first floating routing groups are disposed on two sides of the touch routing group, and the number of the first floating routing lines in different first floating routing groups is the same.

In one possible implementation, the display substrate includes a first power line, the first power line being located in the extension region; at least part of the orthographic projection of the first floating wire on the substrate is positioned in the orthographic projection of the first power line on the substrate.

In one possible implementation, the first floating trace includes a first sub-floating trace and a second sub-floating trace which are stacked;

the orthographic projection of the first sub-floating wire on the substrate base plate is at least partially overlapped with the orthographic projection of the second sub-floating wire on the substrate base plate.

In one possible implementation, the touch traces include a first sub-touch trace and a second sub-touch trace which are stacked;

the first sub-floating wire and the first sub-touch wire are made of the same material on the same layer, and the second sub-floating wire and the second sub-touch wire are made of the same material on the same layer.

In a possible embodiment, the bending region includes a first edge near the display region, a second edge near the extension portion disposed opposite to the first edge, and a connecting edge connecting the first edge and the second edge;

the display substrate comprises signal wires positioned in the bending area, and a second floating wire group surrounding the connecting edge is arranged in an area between the signal wires and the connecting edge; the second floating wire group comprises at least one second floating wire, and the second floating wire is electrically insulated from the signal wire.

In one possible implementation, the second floating trace includes a third sub-floating trace and a fourth sub-floating trace which are stacked; the orthographic projection of the third sub-floating wire on the substrate base plate is at least partially overlapped with the orthographic projection of the fourth sub-floating wire on the substrate base plate.

In one possible implementation, the display substrate further includes a third floating line group located on a side of the second floating line group away from the connection edge; the third floating wire group comprises at least one third floating wire extending along the second direction.

In one possible implementation, the third floating trace includes a fifth sub-floating trace and a sixth sub-floating trace which are stacked; the orthographic projection of the fifth sub-floating wire on the substrate base plate is at least partially overlapped with the orthographic projection of the sixth sub-floating wire on the substrate base plate.

In a possible implementation manner, in a direction perpendicular to the second edge, the minimum distance between the third floating routing group and the signal routing is smaller than the distance between the third floating routing group and the second edge.

In one possible implementation, the display area includes a touch area having touch electrodes, and a lead area surrounding the touch area and having touch leads;

the lead area has a first compensation capacitance at least one corner position in electrical connection with the touch lead.

In one possible implementation, the touch electrode includes a plurality of first touch electrodes extending along the first direction, and a plurality of second touch electrodes extending along the second direction and insulated from the first touch electrodes; the touch control leads comprise first touch control leads which are electrically connected with the first touch control electrodes in a one-to-one corresponding mode, and second touch control leads which are electrically connected with the second touch control electrodes in a one-to-one corresponding mode; the first touch lead and the second touch lead are both provided with double-layer sub-leads;

at the corner position having the first touch lead and the second touch lead, the display substrate forms the first compensation capacitor by mutual extension of the sub-leads of different layers of the first touch lead and the second touch lead.

In one possible implementation, the first touch lead includes a first sub-touch lead and a second sub-touch lead which are stacked, the second touch lead includes a third sub-touch lead and a fourth sub-touch lead which are stacked, the first sub-touch lead and the third sub-touch lead are made of the same material on the same layer, and the second sub-touch lead and the fourth sub-touch lead are made of the same material on the same layer;

at the corner location having both the first and second touch leads, the first touch lead nearest the touch area has a first lead extension extending from the first sub-touch lead, the second touch lead nearest the touch area has a fourth lead extension extending along the fourth sub-touch lead, an orthographic projection of the first lead extension on the substrate base overlaps an orthographic projection of the fourth lead extension on the substrate base to form the first compensation capacitance;

alternatively, at the corner position having the first and second touch leads, the first touch lead nearest to the touch area has a second lead extension extending from the second sub-touch lead, the second touch lead nearest to the touch area has a third lead extension extending along the third sub-touch lead, and an orthogonal projection of the second lead extension on the substrate base overlaps an orthogonal projection of the third lead extension on the substrate base to form the first compensation capacitance.

In one possible implementation, at the corner location having only the second touch lead, the display substrate further includes, at the lead area, a first touch electrode extension extending from the first touch electrode nearest to the touch area;

the display substrate forms the first compensation capacitor through the first touch electrode extension part and the second touch lead.

In one possible implementation, the first touch electrode extension and the fourth sub-touch lead are in the same layer;

at the corner position with only the second touch lead, there is a partial overlap between the orthographic projection of the first touch electrode extension part on the substrate base plate and the orthographic projection of the third sub-touch lead on the substrate base plate to form the first compensation capacitor.

In one possible implementation, at the corner location having only the first touch lead, the display substrate further includes a second touch electrode extension at the lead area that extends from the second touch electrode nearest to the touch area;

the display substrate forms the first compensation capacitor through the second touch electrode extension part and the first touch lead.

In one possible implementation, the second touch electrode extension is on the same layer as the second sub-touch lead;

at the corner position with only the first touch lead, there is a partial overlap between the orthographic projection of the second touch electrode extension part on the substrate base plate and the orthographic projection of the first sub-touch lead on the substrate base plate to form the first compensation capacitor.

In a possible implementation manner, the display substrate further includes a through hole located in the display area, the display substrate includes a first compensation portion located on a side of the first touch electrode facing the through hole, connected to the first touch electrode, and surrounding the through hole, and includes a second compensation portion located on a side of the second touch electrode facing the through hole, connected to the second touch electrode, and surrounding the through hole; the first compensation part and the second compensation part are mutually insulated;

the display substrate is provided with a second compensation capacitor at the position of the through hole through the first compensation part and the second compensation part.

In a possible implementation manner, the display substrate includes a first extension portion located at a different layer from the first compensation portion and connected to an end of the first compensation portion by a hole, and an overlapping region exists between an orthographic projection of the first extension portion on the substrate and an orthographic projection of the second compensation portion on the substrate to form the second compensation capacitor.

The embodiment of the present disclosure further provides a display device, which includes the display substrate provided in the embodiment of the present disclosure.

Drawings

Fig. 1A is a schematic top view of a display substrate according to an embodiment of the disclosure;

FIG. 1B is an enlarged schematic view of FIG. 1A at dashed line block D2;

fig. 1C is a schematic diagram of the first scan signal line layer Gate1 and the second scan signal line layer Gate2 in fig. 1B;

FIG. 1D is a schematic diagram of the layers of FIG. 1C after the data line layers are stacked;

FIG. 2A is an enlarged schematic view of FIG. 1A at dashed line coil D1;

fig. 2B is a schematic view of a stack including the first power line 4 and the first touch metal layer TMA;

FIG. 2C is a schematic view of the laminated interlayer dielectric layer 11 of FIG. 2B;

FIG. 3 is a schematic cross-sectional view of FIG. 2A at dashed line E-E1;

FIG. 4A is an enlarged schematic view showing the connection edge B3 on the left side of the substrate;

FIG. 4B is an enlarged schematic view of FIG. 4A at the dashed line box;

fig. 4C is a schematic diagram of the film layer in fig. 4A including the first scan signal line layer Gate 1;

FIG. 4D is a schematic diagram of the second scan signal line layer Gate2 in FIG. 4C;

FIG. 4E is a schematic diagram of the layers of FIG. 4A including a data line layer;

FIG. 4F is a schematic view of the film layer including the first touch metal layer TMA in FIG. 4A;

fig. 4G is a film layer diagram including the second touch metal layer TMB in fig. 4A;

FIG. 4H is a schematic cross-sectional view taken at dashed line E-E7 in FIG. 4A;

FIG. 5A is an enlarged view of the right side of the substrate at the connection edge B3;

FIG. 5B is an enlarged schematic view of FIG. 5A at the dashed line box;

fig. 6 is a second schematic top view of a display substrate according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a complete touch unit shown in FIG. 6;

FIG. 8 is an enlarged schematic view of the upper left corner position T1 of FIG. 6;

FIG. 9 is one of the schematic cross-sectional views of FIG. 8 taken along dashed line E-E2;

FIG. 10 is a second schematic cross-sectional view taken along dashed line E-E2 of FIG. 8;

FIG. 11 is an enlarged schematic view of the lower left corner position T4 of FIG. 6;

FIG. 12 is a schematic cross-sectional view of FIG. 11 at the dashed line coil;

FIG. 13 is an enlarged schematic view of the upper right corner position T2 of FIG. 6;

FIG. 14 is a schematic cross-sectional view of FIG. 13 at the dashed line coil;

FIG. 15 is an enlarged schematic view of the lower right corner position T2 of FIG. 6;

FIG. 16 is a schematic cross-sectional view of FIG. 15 at the dashed line coil;

FIG. 17 is an enlarged view of the upper left corner of the through hole K;

FIG. 18 is an enlarged schematic view of the dashed coil of FIG. 17;

fig. 19 is a schematic cross-sectional view of fig. 18 at dashed line coil E6.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of known functions and known components have been omitted from the present disclosure.

At present, an On Cell technology mainly includes two types, namely a Flexible Multi-Layer On Cell (FMLOC) technology and a Flexible Single-Layer On Cell (FSLOC) technology, the FMLOC technology is based On a working principle of mutual capacitance detection, two layers of metal are generally adopted to form an emitter (TX) electrode and a Receiver (RX) electrode, an IC detects mutual capacitance between the TX and the RX to realize touch action, the FSLOC technology is based On a working principle of self-capacitance (or voltage) detection, a Single-Layer metal is generally adopted to form an electrode, and the IC detects the self-capacitance (or voltage) of the electrode to realize touch action.

However, in the current FMLOC structure, the problem of non-uniform touch trace under the bending region causes the problem of final touch performance.

In view of the above, referring to fig. 1A and fig. 2A, fig. 2A is an enlarged schematic structural diagram of a circle at a dashed line D1 in fig. 1A, and the outer drawing in fig. 2A is an enlarged schematic diagram of a middle drawing at a position of a different dashed line frame, an embodiment of the present invention provides a display substrate, including:

a base substrate 1, the base substrate 1 comprising: the display device comprises a display area A, a bending area B connected with one side of the display area A, and an extension area C connected with one side of the bending area B far away from the display area A;

the touch routing group 2 is located in the extension area C, and the touch routing group 2 includes a plurality of touch routing lines 20 extending along a first direction G1 and arranged along a second direction G2;

the first floating wire group 3, the first floating wire group 3 being located on at least one side of the touch wire group 2, includes at least one first floating wire 30 extending along a first direction G1, the first direction G1 is a direction pointing from the display area a to the bending region B and the extending region C, and the at least one first floating wire 30 is electrically insulated from the touch wire 20.

In the embodiment of the disclosure, at least one side of the touch wire set 2 is provided with a first floating wire set 3, the first floating wire set 3 includes at least one first floating wire 30, thus, the plurality of first floating traces 30 are disposed on the periphery of the touch trace group 2, so as to prevent the occurrence of a situation that the touch screen panel is damaged when the first floating trace group 3 is not disposed, when the touch trace 20 is formed by patterning, the amount of the etching solution accumulated on the periphery is large, which easily causes over-etching of the peripheral touch trace 20, causes uneven line width between the peripheral touch trace 20 and the inner touch trace 20, and affects the touch performance, in the embodiment of the present disclosure, a plurality of first floating traces 30 are further disposed on the periphery of the touch trace 20, when the amount of the peripheral etching liquid is large, the peripheral first floating trace 30 can be etched, so that the inner touch trace 20 can be protected, and the problem that the touch performance is affected due to uneven line width of the touch trace 20 is solved.

Specifically, as shown in the upper or lower drawing of fig. 2A, the touch trace 20 may be electrically connected to other signal lines or components (e.g., ICs) in the extending direction thereof to provide electrical signals for the touch trace 20, and the first floating trace 30 of the first floating trace group 3 may not be electrically connected to other signal lines in the extending direction thereof, and only serves as a protection trace during the etching process.

In one possible implementation, as shown in fig. 2A, the first floating routing groups 3 are disposed on two sides of the touch routing group 2, and the number of the first floating routing lines 30 in different first floating routing groups 3 is the same. Specifically, for example, in fig. 2A, a left first floating routing group 31 is disposed on the left side of the touch routing group 2, and a right first floating routing group 32 is disposed on the right side of the touch routing group 2. In this way, the touch traces 20 on both edge sides of the touch trace group 2 can be protected.

In one possible embodiment, as shown in the enlarged schematic view of the upper side of fig. 2A, the display substrate includes a first power line 4, the first power line 4 is located in the extension region C; the orthographic projection of the first floating trace 30 on the substrate base plate 1 is at least partially positioned in the orthographic projection of the first power line 4 on the substrate base plate 1. Specifically, the orthographic projection of the first floating trace 30 on the substrate 1 may also be partially located in the orthographic projection of the first power line 4 on the substrate 1, and partially not located in the orthographic projection of the first power line 4 on the substrate 1; it is also possible that the orthographic projection of the first floating trace 30 on the substrate base 1 is entirely located within the orthographic projection of the first power line 4 on the substrate base 1, that is, as shown in the enlarged schematic diagram of the upper side of fig. 2A, in the extension region C, the extension length of the orthographic projection of the first floating trace 30 on the substrate base 1 along the first direction G1 is smaller than the length of the orthographic projection of the first power line 4 on the substrate base 1 along the first direction G1; as for the touch trace 20, the extending length of the touch trace 20 in the first direction G1 of the orthographic projection of the substrate base 1 may be greater than the length of the first power line 4 in the first direction G1 of the orthographic projection of the substrate base 1, so as to be electrically connected to other signal lines.

Specifically, the first power line 4 may be a VSS signal line. Specifically, under the bending region B (i.e. the extension region C), in the direction perpendicular to the substrate 1, the first floating trace 30 and the touch trace 20 may be located on one side of the VSS signal line away from the substrate 1, and the display signals of other signal lines of the display substrate may be shielded by using the constant voltage signal of the VSS signal line, so as to prevent the touch signal and the backplane display signals (GOA signal, Data signal) from affecting each other.

Specifically, the display substrate comprises a first touch metal layer located on one side of the substrate 1, and a second touch metal layer TMB located on one side of the first touch metal layer TMA away from the substrate 1; specifically, referring to fig. 1B, fig. 1C and fig. 1D, wherein fig. 1B is an enlarged schematic view of a dotted line coil D2 in fig. 1A, fig. 1C is a schematic view of film layers of a first scanning signal line layer Gate1 and a second scanning signal line layer Gate2 in fig. 1B, fig. 1D is a schematic view of the film layer after a data line layer (SD layer) is superimposed in fig. 1C, and fig. 1B is a schematic view of the film layer after a first touch metal layer TMA and a second touch metal layer TMB are superimposed in fig. 1D; the Touch Trace 2 (Trace) is generally located above the first power line 4(VSS signal Trace), specifically, below the Bending region B (Bending region), the Touch Trace 2 (Trace) is located on the VSS Trace formed by the SD layer, above the Bending region B (Bending region), the Touch Trace 2 (Trace) is located on the first power line 4(VSS signal Trace) formed by the Data line layer (SD layer), or above the anode metal layer connected to the Data line layer (SD layer), or above the cathode connected to the anode metal layer, the VSS constant voltage signal is used to shield the Backplane (BP) display signal, and the Touch signal and the BP signal (GOA signal, Data signal) are prevented from affecting each other. In the film layer structure below the Bending region B (Bending region), the GOA signal lines and the Data signal lines are usually formed by Gate1 and Gate2 layers, as shown in fig. 1C, the VSS signal lines are formed by SD layers, as shown in fig. 1D, the touch Trace 2 (Trace) is located right above the VSS signal lines and formed by TMA and TMB double-layer metals, and the double-layer metals are connected together through via holes of the interlayer dielectric layer 11 (TLD).

In specific implementation, the touch trace 20 may be a single-layer trace, or may be a single-layer trace at a part of the position, or a single-layer and double-layer alternate trace at a part of the position, or may be a single-layer trace at a part of the position, and then the layer is changed by the jumper. In one possible implementation, referring to fig. 2A, fig. 2B, fig. 2C and fig. 3, wherein fig. 2B is a schematic diagram of a stack including the first power line 4 and the first touch metal layer TMA, fig. 2C is a schematic diagram of fig. 2B after stacking the interlayer dielectric layer 11, fig. 2A is a schematic diagram of fig. 2B after stacking the interlayer dielectric layer 11 and the second touch metal layer TMB, and fig. 3 is a schematic diagram of a cross section of fig. 2A at a dotted line E-E1; the touch trace 20 includes a first sub-touch trace 201 and a second sub-touch trace 202 which are stacked; the first floating trace 30 includes a first sub-floating trace 301 and a second sub-floating trace 302 that are stacked; the orthographic projection of the first sub-floating trace 301 on the substrate base plate 1 is at least partially overlapped with the orthographic projection of the second sub-floating trace 302 on the substrate base plate 1. The first sub-touch trace 201 and the second sub-touch trace 202 are electrically connected in a partial area through an interlayer dielectric layer via hole K1 penetrating through the interlayer dielectric layer 11; the first sub-floating trace 301 and the second sub-floating trace 302 can be isolated and insulated by the interlayer dielectric layer 11 and are not connected with each other. Specifically, the orthographic projection of the first sub-floating trace 301 on the substrate 1 may be partially overlapped with the orthographic projection of the second sub-floating trace 302 on the substrate 1, and partially not overlapped with the orthographic projection of the second sub-floating trace 302 on the substrate 1; the orthographic projection of the first sub-floating trace 301 on the substrate 1 may be completely overlapped with the orthographic projection of the second sub-floating trace 302 on the substrate 1, so that different layers of sub-traces of the touch trace 20 can be protected in the patterning etching process.

Specifically, as shown in fig. 3, a data line 15, a passivation layer 14, and a barrier layer 13 may be sequentially disposed between the substrate 1 and the first sub-touch trace 201; an interlayer dielectric layer 11 may be disposed between the first sub-touch trace 201 and the second sub-touch trace 202; one side of the second touch trace 202 away from the interlayer dielectric layer is provided with a protective layer 12.

In one possible implementation, the first sub-floating trace and the first sub-touch trace 201 are made of the same material in the same layer, and the second sub-floating trace and the second sub-touch trace 202 are made of the same material in the same layer.

Specifically, the first sub-touch trace 201 of the touch trace 20 and the first sub-floating trace of the first floating trace 30 may be both located on the first touch metal layer, and the second sub-touch trace 202 and the second sub-floating trace may be both located on the second touch metal layer.

In one possible embodiment, shown in conjunction with fig. 1A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 5A, and 5B, wherein fig. 4A is an enlarged schematic view showing the connection edge at B3 on the left side of the substrate and fig. 5A is an enlarged schematic view showing the connection edge at B3 on the right side of the substrate; fig. 4B is an enlarged schematic view of the dotted line frame of fig. 5A, fig. 4C is a schematic view of a film layer including a first scan signal line layer Gate1 in fig. 4A, fig. 4D is a schematic view of a film layer including a second scan signal line layer Gate2 in fig. 4C, fig. 4E is a schematic view of a film layer including a data line layer (SD) layer in fig. 4A, fig. 4F is a schematic view of a film layer including a first touch metal layer TMA in fig. 4A, fig. 4G is a schematic view of a film layer including a second touch metal layer TMB in fig. 4A, and fig. 4H is a schematic cross-sectional view of the dotted line E-E7 in fig. 4A; the bending region B comprises a first edge B1 near the display region a, a second edge B2 arranged opposite to the first edge B1 near the extension C, and a connecting edge B3 connecting the first edge B1 and the second edge B2; the display substrate includes a signal trace 5 located in the bending region B, and the signal trace 5 may be specifically understood as a signal line group closest to the connection edge having B3, and specifically may include: the system comprises a panel periphery detection line PCD-FMLOC for detecting whether the periphery of the panel is cracked, a bending area detection line BT for detecting whether the wiring of a bending area is cracked, a constant-level high-voltage signal line VGH, a pixel circuit initialization signal line Vinit, a constant-level low-voltage signal line VGL and a gate drive circuit initialization signal line ESTV; the region between the signal trace 5 and the connection edge B3 has a second floating trace group 6 surrounding the connection edge B3; the second floating wiring group 6 includes at least one second floating wiring 60, and the second floating wiring 60 is electrically insulated from the signal wiring 5. Therefore, the signal wire 5 can be shielded electrostatically, and the problem that the signal wire 5 is damaged due to electrostatic shock easily occurring at a position close to the connection edge B3 (such as a position of a dashed box in fig. 4A and 5A) is solved.

In one possible implementation, as shown in conjunction with fig. 4H, the second floating trace 60 includes a third sub-floating trace 601 and a fourth sub-floating trace 602 which are stacked; the orthographic projection of the third sub-floating trace 601 on the substrate base 1 is at least partially overlapped with the orthographic projection of the fourth sub-floating trace 602 on the substrate base 1. Specifically, the orthographic projection of the third sub-floating trace 601 on the substrate 1 may be partially overlapped with the orthographic projection of the fourth sub-floating trace 602 on the substrate 1, and partially not overlapped with the orthographic projection of the fourth sub-floating trace 602 on the substrate 1; the orthographic projection of the third sub floating trace 601 on the substrate 1 may be completely overlapped with the orthographic projection of the fourth sub floating trace 602 on the substrate 1. Specifically, the third sub-floating trace 601 may be made of the same material as the first sub-floating trace 301 in the same layer, and the fourth sub-floating trace 602 may be made of the same material as the second sub-floating trace 302 in the same layer.

In one possible implementation, as shown in fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 5A and 5B in combination, the display substrate further includes a third floating route group 7 located on a side of the second floating route group 6 away from the connection edge B3; the third floating wiring group 7 includes at least one third floating wiring 70 extending in the second direction G2. Therefore, the signal wire 5 can be better electrostatically shielded, and the problem that the signal wire 5 or a circuit unit connected with the signal wire 5 is damaged due to the fact that the signal wire 5 is easily subjected to electrostatic damage at a position close to the connection edge B3 is solved.

In one possible implementation, the third floating trace 70 includes a fifth sub-floating trace and a sixth sub-floating trace that are stacked; the orthographic projection of the fifth sub-floating wire on the substrate base plate 1 is at least partially overlapped with the orthographic projection of the sixth sub-floating wire on the substrate base plate 1. Specifically, the orthographic projection of the fifth sub-floating trace on the substrate 1 may be partially overlapped with the orthographic projection of the sixth sub-floating trace on the substrate 1, and partially not overlapped with the orthographic projection of the sixth sub-floating trace on the substrate 1; the orthographic projection of the fifth sub floating trace on the substrate 1 may be completely overlapped with the orthographic projection of the sixth sub floating trace on the substrate 1. Specifically, the fifth sub-floating trace may be made of the same material as the first sub-floating trace in the same layer, and the sixth sub-floating trace may be made of the same material as the second sub-floating trace in the same layer.

In one possible embodiment, referring to fig. 4A and 5A, the minimum distance h1 between the third floating line group 7 and the signal trace 5 in the direction perpendicular to the second edge B2 is smaller than the distance h2 between the third floating line group 7 and the second edge B2, i.e., in the direction perpendicular to the second edge B2 as shown in fig. 4A or 5A, the third floating line group 7 is located at an upper position, so that the position of the third floating line group 7 is relatively large and there is more wiring space, and the third floating trace 70 can extend for a longer length to achieve better electrostatic shielding effect.

In one possible implementation, referring to fig. 1A, fig. 6 and fig. 7, wherein fig. 6 includes enlarged schematic views of different corner positions of the display substrate, fig. 7 is a schematic view of a complete touch unit S, the display area a includes a touch area a1 having touch electrodes, and a lead area a2 surrounding the touch area a1 and having touch leads 8; the touch electrodes include a plurality of first touch electrodes S1 extending along the first direction G1, and a plurality of second touch electrodes S2 extending along the second direction G2 and insulated from the first touch electrodes S1; the first touch electrodes S1 intersect the second touch electrodes S2 to form a plurality of touch units S, and the touch leads 8 include first touch leads 81 electrically connected to the first touch electrodes S1 in a one-to-one correspondence (the position of the reference numeral 81 in fig. 1 may specifically include a plurality of first touch leads 81), and second touch leads 82 electrically connected to the second touch electrodes S2 in a one-to-one correspondence (the position of the reference numeral 82 in fig. 1A may specifically include a plurality of second touch leads 82); the first touch lead 81 and the second touch lead 82 are both provided with double-layer sub-leads; at the corner position T, as shown in fig. 6 and 7, since the integrity of the touch unit S (Sensor) is worse than that of the normal region, the mutual capacitance between the first touch electrode S1 (specifically, the transmitting electrode Tx) and the second touch electrode S2 (specifically, the receiving electrode Rx) is smaller than that of the normal region, and when the mutual capacitance is too small, the phenomenon of weak noise immunity of the Sensor is likely to occur, which is represented as large noise volume at the fillet and hole positions; in the embodiment of the disclosure, the lead area a2 has the first compensation capacitor C1 electrically connected to the touch lead 8 at least one corner position T, so that the mutual capacitance compensation at the corner position T can be realized, and the problems that the mutual capacitance of the display substrate at the corner position T is too small, the Sensor noise immunity is weak, and the noise volume is large are solved.

In one possible implementation, referring to fig. 8 and 9, the first touch lead 81 includes a first sub-touch lead 811 and a second sub-touch lead 812 stacked in layers, the second touch lead 82 includes a third sub-touch lead 821 and a fourth sub-touch lead 822 stacked in layers, the first sub-touch lead 811 and the third sub-touch lead 821 are the same material in the same layer, and the second sub-touch lead 812 and the fourth sub-touch lead 822 are the same material in the same layer; at a corner position T having both the first touch lead 81 and the second touch lead 82 (e.g., at a top left corner position T1 of the display substrate as shown in fig. 6), the display substrate forms a first compensation capacitor C1 by the mutual extension of the sub-leads of different layers of the first touch lead 81 and the second touch lead 82. Therefore, the mutual capacitance value compensation of the upper left corner position T1 is realized, and the problems that the mutual capacitance value of the display substrate at the corner position T is too small, the anti-noise capability of a touch unit (Sensor) is weak, and the noise volume is large are solved.

Specifically, referring to fig. 8, 9 and 10, wherein fig. 8 is an enlarged schematic view of the upper left corner position T1 in fig. 1A, fig. 9 and 10 are schematic sectional views taken along a broken line E-E2 in fig. 8, the upper and lower views on the left side of fig. 8 are enlarged schematic views of the lower right view of fig. 8 at different positions, the upper right drawing of figure 8 mainly shows the first lead extension 813 extended from the first sub-touch lead 811, wherein the enlarged view at E2 shows the double-layer punched connection of the first touch lead 81 at the position E21, and from this position, the first touch lead 81 is indexed to the single-layer trace (first lead extension 813) of the first touch metal layer TMA, the enlarged view at E shows the double-layer punched connection of the second touch lead 82 at the position E22, starting from the position, the second touch lead 82 is transposed to the single-layer trace of the second touch metal layer TMB; at a corner position T having both the first touch lead 81 and the second touch lead 82 (i.e., at the upper left corner position T1), the first touch lead 81 nearest to the touch area a1 has a first lead extension 813 extending from the first sub-touch lead 811, the second touch lead 82 nearest to the touch area a1 has a fourth lead extension 823 extending along the fourth sub-touch lead 822, and an orthogonal projection of the first lead extension 813 on the substrate base 1 overlaps an orthogonal projection of the fourth lead extension 823 on the substrate base 1 to form a first compensation capacitance C1; alternatively, as shown in fig. 10, at a corner position T having the first touch lead 81 and the second touch lead 82 (i.e., at an upper left corner position T1), the first touch lead 81 nearest to the touch area a1 has a second lead extension 814 extending from the second sub-touch lead extension 812, the second touch lead 82 nearest to the touch area a1 has a third lead extension 824 extending along the third sub-touch lead 821, and a forward projection of the second lead extension 814 on the substrate base 1 overlaps a forward projection of the third lead extension 824 on the substrate base to form a first compensation capacitor C1.

Specifically, the first touch electrode S1, the first sub-touch lead 811, and the third touch lead 821 may be all located on the first touch metal layer, and the second touch electrode S2, the second sub-touch lead 812, and the fourth sub-touch lead 822 may be all located on the second touch metal layer. The touch lead 8 of the display area a may be electrically connected to the touch trace of the extension area C in a one-to-one correspondence.

In one possible embodiment, see fig. 11 and 12, where fig. 12 is a schematic cross-sectional view of fig. 11 at dashed line E3, the top and bottom views on the right side of fig. 11 are enlarged views of the bottom left view of fig. 11 at different positions, the top left view on fig. 11 mainly shows the first touch electrode extension S11 extending from the first touch electrode S1 nearest to the touch area a1, where the enlarged view at E31 shows the two-layer punch connection of the second touch lead 82 at E31, and the enlarged view at E32 shows the two-layer punch connection of the second touch lead 82 at E32; at the corner position T having only the second touch lead 82 (i.e., at the lower left corner position T4), the display substrate further includes, at the lead area a2, a first touch electrode extension S11 extending from the first touch electrode S1 nearest to the touch area a 1; the display substrate forms a first compensation capacitor through the first touch electrode extension S11 and the second touch lead 82. Therefore, the mutual capacitance value compensation at the lower left corner position T4 is realized, and the problems that the mutual capacitance value of the display substrate at the lower left corner position T4 is too small, the noise resistance of a touch unit (Sensor) is weak, and the noise volume is large are solved.

Specifically, referring to fig. 11 and 12, the first touch electrode extension portion S11 and the fourth sub touch lead 822 are in the same layer, that is, the first touch electrode extension portion S11 and the first touch electrode S1 are in the same layer and are located on the second touch metal layer; at the corner position T having only the second touch lead 82 (i.e., at the lower left corner position T4), there is a partial overlap between the orthographic projection of the first touch electrode extension portion S12 on the substrate base 1 and the orthographic projection of the third sub-touch lead 821 on the substrate base 1 to form a first compensation capacitor C1. In this way, the first touch electrode extension portion S11 is formed by extending the first touch electrode S1, so that the orthographic projection of the first touch electrode extension portion S11 on the substrate 1 overlaps the orthographic projection of the sub-trace third sub-touch lead 821 under the second touch lead S11, thereby forming the first compensation capacitor C1.

In one possible embodiment, referring to fig. 13, 14, 15 and 16, where fig. 13 is an enlarged view of the upper right corner position T2 in fig. 1A, fig. 15 is an enlarged view of the lower right corner position T3 in fig. 1A, fig. 14 is a schematic cross-sectional view of the dashed line coil E4 in fig. 13, fig. 16 is a schematic cross-sectional view of the dashed line coil E5 in fig. 15, the upper and lower views on the right side of fig. 13 are enlarged views of the lower left side of fig. 13 at positions E41 and E42, the upper left side of fig. 13 mainly shows the second touch electrode extension S21 extending from the second touch electrode S2 nearest to the touch area a1, where the enlarged view of the upper left side of E41 shows the double-layer punch connection of the first touch lead 81 at the position E43, the enlarged view of the upper left side of E42 shows the double-layer punch connection of the first touch lead 81 at the position E42, the upper left side of fig. 15 mainly shows the second touch electrode extension S21 extending from the second touch area a1 nearest to the touch area a2, wherein the enlarged view at E51 shows the double-layer punched connection of the first touch lead 81 at the E53 position, and the enlarged view at E52 shows the double-layer punched connection of the first touch lead 81 at the E52 position; at a corner position having only the first touch lead 81 (i.e., the upper right corner position T2 or the lower right corner position T3 in fig. 1A), the display substrate further includes, at the lead region a2, a second touch electrode extension S21 extending from the second touch electrode S2 nearest to the touch region a 1; the display substrate forms a first compensation capacitor C1 through the second touch electrode extension S21 and the first touch lead 81. Therefore, the mutual capacitance value compensation of the upper right corner position T2 or the lower right corner position T3 is realized, and the problems that the mutual capacitance value of the display substrate at the upper right corner position T2 or the lower right corner position T3 is too small, the noise resistance of a touch unit (Sensor) is weak, and the noise volume is large are solved.

Specifically, as shown in fig. 13, 14, 15 and 16, the second touch electrode extension S21 is on the same layer as the second sub-touch lead 812; at a corner position having only the first touch lead 81 (i.e., the upper right corner position T2 or the lower right corner position T3), there is a partial overlap between the orthographic projection of the second touch electrode extension portion S21 on the substrate base 1 and the orthographic projection of the first sub-touch lead 811 on the substrate base 1 to form a first compensation capacitance C1. Specifically, as shown in fig. 13, the second touch electrode extension S21 can also be disposed at a Finger2 position or a Finger3 position.

In one possible embodiment, see fig. 17, 18, 19, wherein, fig. 17 is an enlarged view at the through hole, fig. 18 is an enlarged view at one of the dotted coils (e.g. the dotted coil at the upper left corner) in fig. 17, the drawing on the left side of fig. 18 mainly shows the first extension S31 connected to the end punch of the first compensation portion S3 (e.g. via T in fig. 18), FIG. 18 is an enlarged view of the lower left dotted line coil E6 in the right drawing, FIG. 19 is a cross-sectional view of the dotted line coil E6 in FIG. 18, the display substrate further includes a via hole K in the display area A, the display substrate includes a first compensation portion S3 connected to the first touch electrode S1 and surrounding the via hole K and located on the side of the first touch electrode S1 facing the via hole K, the second compensation part S4 is positioned on one side of the second touch electrode S2 facing the through hole K, is connected with the second touch electrode S2 and surrounds the through hole K; the first compensation part S3 and the second compensation part S4 are insulated from each other; the display substrate is formed with a second compensation capacitance C2 at the position of the through hole K through the first and second compensation parts S3 and S4. Therefore, mutual capacitance value compensation of the peripheral position of the through hole K is achieved, and the problems that the mutual capacitance value of the display substrate at the peripheral position of the through hole K is too small, the noise resisting capacity of a touch unit (Sensor) is weak, and the noise volume is large are solved.

Specifically, as shown in fig. 17, 18 and 19, the display substrate includes a first extension portion S31 located at a different layer from the first compensation portion S3 and connected to an end of the first compensation portion S3 through a hole (e.g., a via T in fig. 19), and an overlapping region exists between an orthogonal projection of the first extension portion S31 on the substrate 1 and an orthogonal projection of the second compensation portion S4 on the substrate 1 to form a second compensation capacitor C2.

Specifically, the display substrate may include two curved first compensation portions S3 located on the left side and the right side of the through hole K, for example, in fig. 17, the upper left side and the lower left side of the through hole K are integrally connected to form one curved first compensation portion S3, and the upper right side and the lower right side of the through hole K are integrally connected to form another curved first compensation portion S3; the display substrate may include two arc-shaped second compensation portions S4 located on the upper side and the lower side of the through hole K, in which the arc-shaped portions on the upper left side and the upper right side of the through hole K are integrally connected to form one of the arc-shaped second compensation portions S4, and the arc-shaped portions on the lower left side and the lower right side of the through hole K are integrally connected to form the other of the arc-shaped second compensation portions S4 in fig. 16. The first compensation part S3 and the second compensation part S4 are in the same layer, are both located on the second touch metal layer, and are disconnected from each other at the circular dotted line coil.

Specifically, in order to more clearly understand the film structure of the display substrate provided by the embodiment of the present disclosure, the following description is made with reference to fig. 3, fig. 4H, fig. 9, fig. 12, fig. 14, fig. 16, and fig. 19 to manufacture the display substrate provided by the embodiment of the present disclosure as follows:

1. after the packaging process, firstly depositing a Barrier layer 13(Barrier), wherein the material can be SiNx; specifically, before forming the encapsulation layer, the data line 15(SD layer) and the passivation layer 14 may be sequentially formed on the base substrate 1; of course, in the manufacturing process of the display substrate, other signal line layers may also be formed, which is not limited in the embodiments of the present disclosure;

2. forming a first touch metal layer (TMA) pattern by a Photo Mask (Photo Mask) process, wherein the material can be a metal Ti-Al-Ti structure and is used for forming a bridge region lower layer channel (bridge part) and touch wires, a first floating wire, a second floating wire and a third floating wire of an extension region C, and sub-layer patterns of touch wires of a lead region A2 on the first touch metal layer;

3. forming a TLD (interlayer dielectric layer 11) pattern by a photoetching (Photo Mask) process, wherein the material can be SiNx and plays an insulating role; the subsequently formed upper layer second touch metal layer (TMB metal layer) and the lower layer TMA metal can be conducted through the via hole design;

4. forming a second touch metal layer (TMB) pattern by a Photo-etching (Photo Mask) process, wherein the material can be a metal Ti-Al-Ti structure, and is used for forming a bridge area upper channel, a metal network (metal mesh) outside the bridge area, which is used for forming a first touch electrode S1 and a second touch electrode S2, and peripheral signal traces, the metal network comprises a touch trace, a first floating trace, a second floating trace and a third floating trace of an extension area C, and a sub-layer pattern of a touch lead of a lead area a2 on the first touch metal layer, the peripheral signal traces are TMA/TMB double-layer metal structures and are connected through TLD via holes;

5. a protection layer 12(TOC) pattern is formed by a Photo Mask (Photo Mask) process, and the material may be PI, which plays an insulation protection role covering the metal mesh and the peripheral trace.

Specifically, the On Cell structure comprises a Touch unit (Sensor) and a peripheral line (Trace), and the Trace connects a signal port of the Touch IC with the Sensor to complete signal transmission. The Trace line is usually located above the VSS signal line, specifically, below (i.e., extending region C) the Bending region b (bonding) region, the Trace line is located on the VSS line formed by the SD layer, and above the bonding, the Trace line is located on the VSS line formed by the SD layer or above the anode metal layer connected to the SD layer or above the cathode connected to the anode metal layer, and the BP display signal is shielded by a VSS constant voltage signal, so as to prevent the Touch signal and the BP signal (GOA signal, Data signal) from affecting each other. In the film layer structure below bonding, a GOA signal line and a Data signal line are usually formed by adopting a Gate1 layer and a Gate2 layer, a VSS signal line is formed by an SD layer, an FMLOC Trace line is positioned right above the VSS signal line and is formed by adopting TMA and TMB double-layer metals, and the double-layer metals are connected together through TLD through holes.

Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, wherein the display device includes the display substrate provided by the embodiment of the present disclosure.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A display substrate, comprising:

2. The display substrate according to claim 1, wherein the first floating routing groups are disposed on two sides of the touch routing group, and the first floating routing groups of different first floating routing groups have the same number.

3. The display substrate of claim 1, wherein the display substrate comprises a first power line at the extension region; the orthographic projection of the first floating wire on the substrate base plate is at least partially positioned in the orthographic projection of the first power line on the substrate base plate.

4. The display substrate of claim 3, wherein the first floating trace comprises a first sub-floating trace and a second sub-floating trace which are stacked;

5. The display substrate according to claim 4, wherein the touch trace comprises a first sub-touch trace and a second sub-touch trace which are stacked;

6. The display substrate of claim 1, wherein the bending region comprises a first edge near the display region, a second edge near the extension region disposed opposite to the first edge, and a connecting edge connecting the first edge and the second edge;

7. The display substrate according to claim 6, wherein the second floating trace comprises a third sub-floating trace and a fourth sub-floating trace which are stacked; the orthographic projection of the third sub-floating wire on the substrate base plate is at least partially overlapped with the orthographic projection of the fourth sub-floating wire on the substrate base plate.

8. The display substrate of claim 6, wherein the display substrate further comprises a third floating line group located on a side of the second floating line group away from the connection edge; the third floating wire group comprises at least one third floating wire extending along the second direction.

9. The display substrate according to claim 8, wherein the third floating trace comprises a fifth sub-floating trace and a sixth sub-floating trace which are stacked; the orthographic projection of the fifth sub-floating wire on the substrate base plate is at least partially overlapped with the orthographic projection of the sixth sub-floating wire on the substrate base plate.

10. The display substrate of claim 9, wherein a minimum distance between the third floating line group and the signal line is smaller than a distance between the third floating line group and the second edge in a direction perpendicular to the second edge.

11. The display substrate of any one of claims 1-10, wherein the display area comprises a touch area having touch electrodes, and a lead area surrounding the touch area and having touch leads;

12. The display substrate according to claim 10, wherein the touch electrode comprises a plurality of first touch electrodes extending in the first direction, and a plurality of second touch electrodes extending in the second direction and insulated from the first touch electrodes; the touch control leads comprise first touch control leads which are electrically connected with the first touch control electrodes in a one-to-one corresponding mode, and second touch control leads which are electrically connected with the second touch control electrodes in a one-to-one corresponding mode; the first touch lead and the second touch lead are both provided with double-layer sub-leads;

13. The display substrate according to claim 12, wherein the first touch lead comprises a first sub-touch lead and a second sub-touch lead which are stacked, the second touch lead comprises a third sub-touch lead and a fourth sub-touch lead which are stacked, the first sub-touch lead and the third sub-touch lead are made of the same material in the same layer, and the second sub-touch lead and the fourth sub-touch lead are made of the same material in the same layer;

14. The display substrate of claim 13, wherein at the corner location having only the second touch lead, the display substrate further comprises a first touch electrode extension at the lead area that extends from the first touch electrode nearest to the touch area;

15. The display substrate of claim 14, wherein the first touch electrode extension and the fourth sub-touch lead are on the same layer;

16. The display substrate of claim 13, wherein at the corner location having only the first touch lead, the display substrate further comprises a second touch electrode extension at the lead area that extends from the second touch electrode nearest to the touch area;

17. The display substrate of claim 16, wherein the second touch electrode extension is in the same layer as the second sub-touch lead;

18. The display substrate according to claim 12, wherein the display substrate further comprises a through hole in the display area, the display substrate comprises a first compensation portion located on a side of the first touch electrode facing the through hole, connected to the first touch electrode, and surrounding the through hole, and a second compensation portion located on a side of the second touch electrode facing the through hole, connected to the second touch electrode, and surrounding the through hole; the first compensation part and the second compensation part are mutually insulated;

19. The display substrate of claim 18, wherein the display substrate comprises a first extension portion located at a different layer from the first compensation portion and connected to an end of the first compensation portion through a hole, and an overlapping region exists between an orthographic projection of the first extension portion on the substrate and an orthographic projection of the second compensation portion on the substrate to form the second compensation capacitor.

20. A display device comprising the display substrate according to any one of claims 1 to 19.