CN113541775A - Optical fiber bus fault reconstruction system - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/03—Arrangements for fault recovery
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/03—Arrangements for fault recovery
- H04B10/032—Arrangements for fault recovery using working and protection systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/03—Arrangements for fault recovery
- H04B10/038—Arrangements for fault recovery using bypasses
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
Abstract
The application relates to a fiber bus fault reconstruction system. The system comprises a bus controller, a first terminal node and a second terminal node which are respectively connected with the bus controller, wherein a standby application processing unit for executing the task of the first terminal node when the first terminal node is abnormal is arranged in the second terminal node; and when the bus controller identifies that the first terminal node is abnormal, the bus controller controls the standby application processing unit of the second terminal node to carry out fault reconstruction. When the first terminal node is abnormal, the system does not need to process data or control the system through complete backup equipment when the equipment fails, and can complete fault reconstruction only through the standby application processing unit of the second terminal node, thereby reducing the time overhead of fault switching and improving the fault processing efficiency.
Description
Technical Field
The application relates to the technical field of optical fiber networks, in particular to a fault reconstruction system of an optical fiber bus.
Background
The FC-AE-1553 bus consists of a bus controller and a bus terminal, and a command response type communication protocol is adopted between the bus controller and the bus terminal, namely, all communication processes on the bus can only be initiated and scheduled by the bus controller. In practical application, according to different requirements of application scenes such as physical positions of actual layout, improvement of bus transmission reliability, bus isomerism and the like, multiple FC-AE-1553 data buses are required to be adopted to complete transmission.
However, the manner in which data interaction is accomplished using multiple FC-AE-1553 data buses may result in an increased rate of device failure.
At present, a backup mode is usually adopted to deal with equipment failure, and the failure processing efficiency is low.
Disclosure of Invention
In view of the above, it is necessary to provide a fiber bus fault reconfiguration system capable of improving the fault processing efficiency.
A fiber bus fault reconstruction system comprises a bus controller, a first terminal node and a second terminal node which are respectively connected with the bus controller, wherein a standby application processing unit for executing a task of the first terminal node when the first terminal node is abnormal is arranged in the second terminal node;
and when the bus controller identifies that the first terminal node is abnormal, the bus controller controls the standby application processing unit of the second terminal node to carry out fault reconstruction.
In one embodiment, a first terminal node is provided with a first bus interface module and a first device processing module; the bus controller is used for determining that the first terminal node is abnormal when the working state parameter of the first terminal node is received and exceeds the time limit; the bus controller is also used for determining that the first terminal node is abnormal when receiving a first terminal node timeout message fed back by the second terminal node, wherein the first terminal node timeout message is generated when the second terminal node receives the application data of the first terminal node and times out; the bus controller is further configured to determine that the first terminal node is abnormal when receiving a handshake timeout message sent by the first terminal node, where the handshake timeout message is generated when the first bus interface module detects handshake timeout of the first device processing module.
In one embodiment, the bus controller is further configured to schedule the standby application processing unit to perform control instruction transmission and data acquisition when the first terminal node is detected to be abnormal.
In one embodiment, a central bus interface module is arranged in the bus controller; and the standby application processing unit calculates according to the control operation of the first terminal node sent by the central bus interface module to obtain a control instruction, and transmits the control instruction to the first terminal node.
In one embodiment, the second terminal node is further provided with a second bus interface module; the standby application processing unit transmits the control instruction to the second bus interface module; and the first bus interface module reads the control instruction from the second bus interface module and outputs the control instruction.
In one embodiment, the bus controller is further provided with a central equipment data processing module and a central external interface module; the central bus interface module receives input control operation and transmits the input control operation to the central equipment data processing module; the central equipment data processing module identifies input control operation and sends an identification result to the central external interface module, and the central external interface module sends the control operation of the first terminal node in the identification result to the standby application processing unit.
In one embodiment, the first terminal node is further provided with a first external interface module; the first external interface module receives the input parameters, processes the input parameters and sends the processed parameters to the first bus interface module; the bus controller sends the processed parameters to the standby application processing unit from the first bus interface module; the standby application processing unit obtains a state parameter after finishing data processing according to the processed parameter, and sends the state parameter to the second bus interface module; the bus controller collects the state parameters from the second bus interface module and outputs the state parameters through the central external interface module.
In one embodiment, the central bus interface module, the first bus interface module and the second bus interface module all adopt a dual redundancy structure to realize data backup.
In one embodiment, the first end node and the second end node send their operating state parameters to the bus controller at a fixed frequency.
In one embodiment, the system further comprises a forwarding node, through which the bus controller is connected to the first end node and the second end node.
The optical fiber bus fault reconstruction system comprises a bus controller, a first terminal node and a second terminal node which are respectively connected with the bus controller, wherein the second terminal node is internally provided with a standby application processing unit which executes a task of the first terminal node when the first terminal node is abnormal; and when the bus controller identifies that the first terminal node is abnormal, the bus controller controls the standby application processing unit of the second terminal node to carry out fault reconstruction. When the first terminal node is abnormal, the system does not need to process data or control the system through complete backup equipment when the equipment fails, and can complete fault reconstruction only through the standby application processing unit of the second terminal node, thereby reducing the time overhead of fault switching and improving the fault processing efficiency.
Drawings
FIG. 1 is a system diagram of a fiber optic bus fault reconstruction system in one embodiment;
FIG. 2 is a diagram illustrating the transmission of control commands according to one embodiment;
FIG. 3 is a schematic transmission diagram of data acquisition in one embodiment;
FIG. 4 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The FC-AE-1553 bus consists of a bus controller and a bus terminal, and a command response type communication protocol is adopted between the bus controller and the bus terminal, namely, all communication processes on the bus can only be initiated and scheduled by the bus controller. The FC-AE-1553 bus physical layer adopts a shared passive optical network, and the bus controller scheduling communication process adopts a time division multiplexing mode, namely after the first communication process scheduled by the bus controller is finished in communication on the passive optical network, the second communication process can be scheduled. In practical application, in application scenarios of limited physical positions of actual layout, improvement of bus transmission reliability, bus isomerism and the like, transmission needs to be completed by adopting a plurality of FC-AE-1553 data buses, and the data interaction efficiency is influenced by a data interaction mode among the plurality of FC-AE-1553 data buses.
The FC-AE-1553 bus is taken as a typical command response type bus protocol and is suitable for a closed-loop control system with higher communication reliability requirement. In the initialization process of each device, a system allocates a fixed address, each device allocates a unique address, the devices cannot be overlapped and multiplexed, and when the devices communicate with each other, routing is completed according to the addresses. When a single device encounters a fault, system reconfiguration cannot be achieved.
Generally, in order to improve the robustness of the FC-AE-1553 bus system and overcome the influence of a single machine fault on the system, a single machine backup or unit backup mode is usually adopted, that is, a dual-mode redundancy or triple-mode redundancy scheme is adopted for equipment with lower reliability in the system.
The current scheme can overcome the influence of single machine equipment failure on the system, when the equipment fails, the backup equipment is started to replace the master equipment to complete corresponding algorithm and control, but other influences are brought to the system, specifically:
(1) the energy consumption of the system is increased. For the scenario of using the battery to complete the system power supply, under the condition that the total amount of available energy is fixed, the magnitude of the system power supply current is related to the time of the system continuously working, and the working time of the system is shorter when the current is larger. Therefore, the solution of dual or triple modular redundancy comes at the cost of the time that the system can work continuously.
(2) The time overhead for completing failover between the primary and backup devices is large. When the master device completes data processing or system control according to a specific algorithm, a certain time delay is generally provided, that is, a certain time difference exists between data input and data output of each device. In the scheme of performing fault reconstruction by using the primary equipment and the backup equipment, when the primary equipment is switched to the backup equipment to work, data sent to the primary equipment cannot be recovered, the output of the backup equipment is temporarily in an invalid state, and a system is in an out-of-control state for a period of time.
Aiming at solving the problem of single machine equipment fault reconstruction in the system by sacrificing the sustainable working time of the system and the overall reliability of the system in the current solution, a novel optical fiber bus fault reconstruction system is provided.
The system diagram of the fiber bus fault reconstruction system provided by the application is shown in fig. 1. The optical fiber bus fault reconstruction system comprises a bus controller, a first terminal node, a second terminal node and a forwarding node, wherein the bus controller, the first terminal node, the second terminal node and the forwarding node are connected through an optical fiber bus and communicate by adopting a corresponding command protocol. The bus controller, the first terminal node, the second terminal node, and the forwarding node may be, but are not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices.
In one embodiment, a fiber bus fault reconstruction system is provided, which includes a bus controller, and a first terminal node and a second terminal node connected to the bus controller, respectively, where the second terminal node is provided with a standby application processing unit for executing a task of the first terminal node when the first terminal node is abnormal;
and when the bus controller identifies that the first terminal node is abnormal, the bus controller controls the standby application processing unit of the second terminal node to carry out fault reconstruction.
The optical fiber bus can be an FC-AE-1533 bus.
Specifically, the bus controller, the first end node, and the second end node are all connected to the FC-AE-1533 passive optical network, and communications on the optical fiber bus are initiated and scheduled by the bus controller. And when the bus controller identifies that the first terminal node is abnormal, the bus controller controls the standby application processing unit of the second terminal node to execute the task of the first terminal node, so as to realize fault reconstruction.
In the optical fiber bus fault reconstruction system, a bus controller, a first terminal node and a second terminal node which are respectively connected with the bus controller are arranged, and a standby application processing unit for executing a task of the first terminal node when the first terminal node is abnormal is arranged in the second terminal node; and when the bus controller identifies that the first terminal node is abnormal, the bus controller controls the standby application processing unit of the second terminal node to carry out fault reconstruction. When the first terminal node is abnormal, the system does not need to process data or control the system through complete backup equipment when the equipment fails, and can complete fault reconstruction only through the standby application processing unit of the second terminal node, thereby reducing the time overhead of fault switching and improving the fault processing efficiency.
In an optional embodiment, a first bus interface module and a first device processing module are arranged in the first terminal node; the bus controller is used for determining that the first terminal node is abnormal when the working state parameter of the first terminal node is received and exceeds the time limit; the bus controller is also used for determining that the first terminal node is abnormal when receiving a first terminal node timeout message fed back by the second terminal node, wherein the first terminal node timeout message is generated when the second terminal node receives the application data of the first terminal node and times out; the bus controller is further configured to determine that the first terminal node is abnormal when receiving a handshake timeout message sent by the first terminal node, where the handshake timeout message is generated when the first bus interface module detects handshake timeout of the first device processing module.
As shown in fig. 1, a bus controller (NC), a first terminal node (NT 1), and a second terminal node (NT 2) are split into modules according to the functional characteristics of a single device, and the bus controller includes a central bus interface module (i.e., an optical fiber protocol chip), a central device data processing module (i.e., an external control or memory control module), and a central external interface module (FPGA: interface control module). The first terminal node comprises a first bus interface module (namely an optical fiber protocol chip), a first equipment data processing module (namely an external control or storage control module) and a first external interface module (FPGA: an interface control module). The second terminal node has a structure consistent with that of the first terminal node, and comprises a second bus interface module (namely an optical fiber protocol chip), a second equipment data processing module (namely an external control or memory control module) and a second external interface module (FPGA: interface control module). The bus controller, the first terminal node and the second terminal node are realized by adopting an ONU type photoelectric conversion module.
The second device data Processing module of the second terminal node includes an application Processing unit (DSP (Digital Signal Processing, chip for implementing Digital Signal Processing technology)) application 1 and a standby application Processing unit (DSP application 2). The first device data processing module of the first terminal node also comprises an application processing unit and a standby application processing unit, and the standby application processing unit of the first terminal node is used for completing the task of the second terminal node when the second terminal node is abnormal. And the standby application processing unit of the second terminal node is used for completing the task of the first terminal node when the first terminal node is abnormal.
Specifically, when the bus controller receives the working state parameter timeout of the first terminal node, it is determined that the first terminal node is abnormal, that is, the DSP of the bus controller is overtime through the working state parameter collection fed back by the first terminal node, and it is recognized that the DSP of the first terminal node is abnormal.
The bus controller is further configured to determine that the first terminal node is abnormal when receiving a first terminal node timeout message fed back by the second terminal node, where the first terminal node timeout message is generated when the second terminal node receives application data of the first terminal node and times out, that is, the DSP application 1 of the second terminal node sends the first terminal node timeout message to the bus controller when receiving the application data of the first terminal node and times out, and the bus controller determines that the first terminal node DSP is abnormal according to the first terminal node timeout message.
The bus controller is further used for determining that the first terminal node is abnormal when receiving the handshake timeout message sent by the first terminal node, the handshake timeout message is generated when the first bus interface module detects handshake timeout of the first device processing module, namely when the FPGA of the first terminal node recognizes that the DSP of the first terminal node is abnormal through handshake timeout with the DSP of the first terminal node, the handshake timeout message is sent to the bus controller, and the bus controller judges that the DSP of the first terminal node is abnormal according to the handshake timeout message.
In this embodiment, a module design idea is proposed, to solve the problem of reliability indexes of different modules in the optical fiber bus system, the single-chip device is split into different functional modules, reliability of a specific functional unit is strengthened, a working condition of the first terminal node is detected in multiple ways, an abnormal condition can be found in time, the bus controller is used for scheduling, and a task of the first terminal node is scheduled to the standby application processing unit of the second terminal node, so that reliability and fault processing rate of the system are improved.
In an optional embodiment, the bus controller is further configured to schedule the standby application processing unit to perform control instruction transmission and data acquisition when the first terminal node is detected to be abnormal.
Specifically, when the DSP chip (i.e., the first device data processing module) of the first terminal node is abnormal and loses the application data processing capability of the first terminal node, the DSP processing function of the first terminal node is assumed by the DSP application program 2 of the second terminal node, and the bus controller schedules the DSP application program 2 of the second terminal node to perform control instruction transmission and data acquisition. When the second terminal node receives the control instruction transmission and the data acquisition task of the first terminal node sent by the bus controller, the DSP application program 1 of the second terminal node sends a semaphore to the application program 2 so as to start the DSP application program 2 to complete the application data processing of the first terminal node.
In this embodiment, when the DSP chip (i.e., the second device data processing module) of the second terminal node is abnormal and loses the application data processing capability of the second terminal node, the DSP processing function of the second terminal node is assumed by the DSP application program 2 of the first terminal node, and the bus controller schedules the DSP application program 2 of the first terminal node to perform control instruction transmission and data acquisition.
In this embodiment, the advantage of the transmission rate of the FC-AE-1553 bus is utilized, the scheduling function of the bus controller is added to the system, the processing function of the single machine equipment with a fault is transferred to other single machines, the data processing or control sequence is completed, and the system function reconfiguration is completed.
In an optional embodiment, the bus controller is further provided with a central device data processing module and a central external interface module; the central bus interface module receives input control operation and transmits the input control operation to the central equipment data processing module; the central equipment data processing module identifies input control operation and sends an identification result to the central external interface module, and the central external interface module sends the control operation of the first terminal node in the identification result to the standby application processing unit.
Specifically, as shown in fig. 2, it is a control instruction transmission process when the first terminal node is abnormal. The central bus interface module receives control operations input by other equipment (input interface of FPGA) except the FC-AE-1553 network, such as control instructions input by a ground test system, a bus health management system and the like.
And the DSP of the bus controller identifies the control operation, the identification result is that the control instruction belongs to the first terminal node or the second terminal node, and the identification result is updated to a protocol chip of the bus controller. When the protocol chip of the bus controller recognizes that the control instruction belongs to the control instruction of the second terminal node, the protocol chip of the bus controller arranges NC2NT message to send the control instruction of the second terminal node to the second terminal DSP application 1. When the protocol chip of the bus controller recognizes that the control instruction belongs to the control instruction of the first terminal node, the protocol chip of the bus controller arranges NC2NT message to send the control instruction of the first terminal node to the second terminal DSP application 2.
In an optional embodiment, a central bus interface module is arranged in the bus controller; and the standby application processing unit calculates according to the control operation of the first terminal node sent by the central bus interface module to obtain a control instruction, and transmits the control instruction to the first terminal node.
Specifically, the protocol chip configuration NC2NT message of the bus controller sends the control instruction of the first terminal node to the second terminal DSP application 2, the second terminal DSP application 2 performs data processing according to the control instruction, updates the control instruction obtained after the data processing to the second bus interface module (i.e., the protocol chip of the second terminal node), and then transmits the control instruction obtained after the data processing to the first terminal node by the bus controller.
In an optional embodiment, the second terminal node is further provided with a second bus interface module; the standby application processing unit transmits the control instruction to the second bus interface module; and the first bus interface module reads the control instruction from the second bus interface module and outputs the control instruction.
Specifically, after the protocol chip of the bus controller detects that the protocol chip of the second terminal node is updated, the protocol chip of the bus controller arranges NT2NT message to send a control instruction obtained after data processing of the second terminal node to the protocol chip of the first terminal node. And the first terminal node FPGA reads the control instruction from the protocol chip and outputs the control instruction. For example, when the DSP of the first terminal node fails, the calculation capability of the control parameter is reconfigured to the application 2 of the DSP of the second terminal node, and after the calculation is completed, the control parameter is scheduled to the optical fiber bus protocol chip of the first terminal node through the bus controller of the FC-AE-1553 bus, and is read by the FPGA of the first terminal node through the dotted path in fig. 1, so that the FPGA can complete the control of the external device, such as the power-off relay.
In an optional embodiment, the first terminal node is further provided with a first external interface module; the first external interface module receives the input parameters, processes the input parameters and sends the processed parameters to the first bus interface module; the bus controller sends the processed parameters to the standby application processing unit from the first bus interface module; the standby application processing unit obtains a state parameter after finishing data processing according to the processed parameter, and sends the state parameter to the second bus interface module; the bus controller collects the state parameters from the second bus interface module and outputs the state parameters through the central external interface module.
Specifically, as shown in fig. 3, in the data acquisition and transmission process when the first terminal node is abnormal, the FPGA input interface of the first terminal node receives the input parameter, processes the input parameter, and updates the processed parameter to the memory of the protocol chip of the first terminal node. After waiting for the time slice, the bus controller arranges NT2NT messages to send the parameters processed by the first terminal node from the protocol chip memory of the first terminal node to the second terminal node, and the DSP application 2 of the second terminal node completes data processing according to the processed parameters to obtain state parameters, and updates the state parameters to the protocol chip memory of the second terminal node. After waiting for the time slice, the bus controller arranges NT2NC message to send the status parameter from the protocol chip memory of the second terminal node to the DSP of the bus controller, and outputs it through the FPGA interface of the bus controller.
In an alternative embodiment, the central bus interface module, the first bus interface module, and the second bus interface module all implement data backup by using a dual redundancy structure.
The double redundancy structure is used for transmitting the same data by adopting a redundancy channel A \ B to realize the data backup function. For example, if the channel a has an error, the data may be adjusted to the channel B to receive the data of the channel B while determining that the data is in error. The switching time is almost 0 compared to the conventional method of detecting an a channel data error and then requesting a B channel to retransmit the data.
Specifically, the central bus interface module, the first bus interface module and the second bus interface module all adopt a dual redundancy structure, the switching time among different bus interfaces is eliminated, the influence of single-machine bus interface faults on the system is eliminated, and the reliability of the system is improved.
In an alternative embodiment, the first terminal node and the second terminal node send their operating state parameters to the bus controller at a fixed frequency.
Specifically, after the first terminal node and the second terminal node complete the task sent by the system, the working state parameters of the first terminal node and the second terminal node are sent to the bus controller at a fixed frequency, so that the bus controller can judge whether the first terminal node is abnormal or not according to the first terminal node in real time, and the bus controller can judge whether the second terminal node is abnormal or not according to the working state of the second terminal node in real time.
In this embodiment, the first terminal node and the second terminal node feed back the system operating state to the bus controller at a fixed frequency, so as to ensure that the bus controller senses the operating state of the device data processing unit in time under the requirement of system reliability, thereby improving the efficiency of implementing system fault detection.
In an optional embodiment, the system further comprises a forwarding node, and the bus controller is connected with the first terminal node and the second terminal node through the forwarding node.
The forwarding node is realized by adopting an OLT type photoelectric conversion module.
Specifically, the system further comprises a forwarding Node (NR), the optical fiber signal transmission has directivity, and the bus controller realizes information transmission between the first terminal node and the second terminal node through the forwarding node. For example, when the bus controller sends a control instruction to the first terminal node, the control instruction is first transmitted to the forwarding node by the central bus interface module (i.e., the optical fiber protocol chip of the bus controller), and then the forwarding node forwards the control instruction to the first terminal node.
It should be understood that although the various steps in the flowcharts of fig. 2-3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-3 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps or stages.
In one embodiment, a computer device is provided, which may be a bus controller, a first terminal node, or a second terminal node, and its internal structure diagram may be as shown in fig. 4. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a fiber optic bus fault reconstruction system. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 4 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An optical fiber bus fault reconstruction system is characterized by comprising a bus controller, a first terminal node and a second terminal node, wherein the first terminal node and the second terminal node are respectively connected with the bus controller;
and when the bus controller identifies that the first terminal node is abnormal, the bus controller controls a standby application processing unit of the second terminal node to carry out fault reconstruction.
2. The system of claim 1, wherein a first bus interface module and a first device processing module are disposed in the first terminal node;
the bus controller is used for determining that the first terminal node is abnormal when the working state parameter of the first terminal node is received to be overtime;
the bus controller is further configured to determine that the first terminal node is abnormal when receiving a first terminal node timeout message fed back by the second terminal node, where the first terminal node timeout message is generated when the second terminal node receives application data of the first terminal node and times out;
the bus controller is further configured to determine that the first terminal node is abnormal when receiving a handshake timeout message sent by the first terminal node, where the handshake timeout message is generated when the first bus interface module detects handshake timeout of the first device processing module.
3. The system of claim 2, wherein the bus controller is further configured to schedule the standby application processing unit for control instruction transmission and data acquisition when the first end node is detected to be abnormal.
4. The system of claim 3, wherein a central bus interface module is disposed in the bus controller;
and the standby application processing unit calculates according to the control operation of the first terminal node sent by the central bus interface module to obtain a control instruction, and transmits the control instruction to the first terminal node.
5. The system of claim 4, wherein a second bus interface module is further disposed in the second end node;
the standby application processing unit transmits the control instruction to the second bus interface module;
and the first bus interface module reads the control instruction from the second bus interface module and outputs the control instruction.
6. The system of claim 4, wherein the bus controller is further provided with a central device data processing module and a central external interface module;
the central bus interface module receives input control operation and transmits the input control operation to the central equipment data processing module; the central equipment data processing module identifies the input control operation and sends an identification result to the central external interface module, and the central external interface module sends the control operation of the first terminal node in the identification result to the standby application processing unit.
7. The system of claim 6, wherein the first terminal node is further provided with a first external interface module;
the first external interface module receives input parameters, processes the input parameters and sends the processed parameters to the first bus interface module; the bus controller sends the processed parameters to a standby application processing unit from the first bus interface module; the standby application processing unit obtains a state parameter after finishing data processing according to the processed parameter, and sends the state parameter to the second bus interface module; the bus controller collects the state parameters from the second bus interface module and outputs the state parameters through the central external interface module.
8. The system of claim 7, wherein the central bus interface module, the first bus interface module, and the second bus interface module implement data backup using a dual redundancy architecture.
9. The system of claim 1, wherein the first end node and the second end node send their operating state parameters to the bus controller at a fixed frequency.
10. The system of claim 1, further comprising a forwarding node through which the bus controller is connected to the first end node and the second end node.
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