CN113541632A - Impedance adjustable circuit - Google Patents
Impedance adjustable circuit Download PDFInfo
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- CN113541632A CN113541632A CN202110730472.2A CN202110730472A CN113541632A CN 113541632 A CN113541632 A CN 113541632A CN 202110730472 A CN202110730472 A CN 202110730472A CN 113541632 A CN113541632 A CN 113541632A
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/38—Impedance-matching networks
Abstract
The present application relates to the field of electrical circuits. The application provides an impedance adjustable circuit, includes: a first impedance tuner including a first clock signal transmission line, a first data signal transmission line, and an impedance variable device; in response to the acquired first clock signal of the first clock signal transmission line and the acquired first data signal of the first data signal transmission line, the first impedance tuner adjusts the impedance value of the impedance variable device to a first impedance value, which is an impedance value corresponding to the first clock signal and the first data signal; and the first impedance value is used for carrying out radio frequency debugging on the impedance adjustable circuit so as to obtain a radio frequency index. By modifying the clock signal of the first clock signal transmission line and the data signal of the first data signal transmission line, the corresponding impedance value is selected, so that the manual replacement of an impedance element in the matching circuit for radio frequency debugging is avoided, the debugging time is saved, and the efficiency is improved.
Description
Technical Field
The application relates to the field of circuits, in particular to an impedance adjustable circuit.
Background
The matching circuit is used as a part of the radio frequency circuit and bears an input/output bridge, and in order to ensure that effective transmission of signals or energy from a signal source to a load can be realized, the matching circuit is required to be used for debugging the impedance matching circuit so as to achieve the optimal radio frequency performance.
The rapid development of wireless communication nowadays, 5G is more and more widely applied, the requirements of SUB6G and subsequent millimeter wave ultrahigh frequency products on radio frequency circuits are higher and higher, and the impedance value of the radio frequency circuit is different in order of magnitude by extremely small capacitance resistance deviation for the capacitance resistance sensor of the ultrahigh frequency products. Because the resistance-capacitance parameters of the same batch of resistance-capacitance sensing devices are consistent, and each independent resistance-capacitance sensing device has a small resistance-capacitance sensing difference, if the impedance value of the matching circuit of the ultrahigh frequency product is set only according to the resistance-capacitance parameters during radio frequency debugging, the obtained radio frequency debugging result may be greatly different from the expected result, so that the impedance value in the matching circuit needs to be changed for many times, and the radio frequency debugging is performed by referring to the obtained radio frequency index. In the traditional radio frequency debugging, the impedance element in the matching circuit needs to be replaced to change the impedance value of the matching circuit to realize the radio frequency debugging, and the radio frequency debugging mode of manual material replacement is low in efficiency.
Therefore, how to provide a matching circuit and a corresponding impedance adjusting method is to be solved for improving the efficiency of radio frequency debugging.
Disclosure of Invention
In view of the foregoing, it is desirable to provide an impedance tunable circuit to improve efficiency of rf debugging.
In a first aspect, the present application provides an impedance tunable circuit, comprising: a first impedance tuner including a first clock signal transmission line, a first data signal transmission line, and an impedance variable device; in response to the acquired first clock signal of the first clock signal transmission line and the acquired first data signal of the first data signal transmission line, the first impedance tuner adjusts the impedance value of the impedance variable device to a first impedance value, which is an impedance value corresponding to the first clock signal and the first data signal; and the first impedance value is used for carrying out radio frequency debugging on the impedance adjustable circuit so as to obtain a radio frequency index.
By implementing the circuit provided by the first aspect, the corresponding impedance value can be selected by modifying the clock signal of the first clock signal transmission line and the data signal of the first data signal transmission line, so that the condition that the impedance element in the matching circuit is manually replaced to perform radio frequency debugging is avoided, the debugging time is saved, and the efficiency is improved. It can be understood that although the clock signal of the first clock signal transmission line and the data signal of the first data signal transmission line are modified manually in the embodiment of the present application, the objects of modification are not consistent, the manual replacement of the impedance element may be to replace an entire impedance element or the impedance element is an adjustable microstrip line, the manner of replacing an entire impedance element is time and labor consuming when the target impedance element is found manually and the process is replaced, and the manual steps involved in the process are too many and error prone; and to adjustable microstrip line, the manual work is adjusted the microstrip line to fixed position, needs debugging personnel to know very to the microstrip line structure to and accomplish work enough meticulous when adjusting the width and the area of microstrip line, the operation requires height. However, the present solution adjusts the impedance value indirectly through the clock signal and the data signal, only the input of the clock signal and the data signal may involve manual adjustment, and the adjustment of the impedance value of the first impedance tuner to the target impedance value is automatically adjusted by the impedance variable device. Illustratively, the impedance variable device comprises a plurality of impedance elements, and the impedance variable device is controlled by a clock signal and a data signal to replace the impedance elements with corresponding impedance values; alternatively, the impedance variable device includes a microstrip line, and the width and area of the microstrip line in the impedance variable device are controlled by a clock signal and a data signal.
With reference to the first aspect, in some embodiments, the first clock signal transmission line is configured to receive a plurality of clock signals, the first data signal transmission line is configured to receive a plurality of data signals, and the impedance variable device is specifically configured to obtain a plurality of impedance values according to different combinations of any one of the plurality of clock signals and any one of the plurality of data signals; the impedance values are used for carrying out radio frequency debugging to obtain a plurality of radio frequency indexes; determining a first impedance value corresponding to an optimal radio frequency index in the plurality of radio frequency indexes; and taking a clock signal corresponding to the first impedance value as the first clock signal, and taking a data signal corresponding to the first impedance value as the first data signal.
Optionally, different combinations of the clock signal traversing the first clock signal transmission line and the data signal traversing the first data signal transmission line may be input one by a debugger, or a traversal code may be set, so that the first impedance tuner performs traversal by itself.
In the embodiment of the present application, a plurality of impedance values are obtained by traversing different combinations of the clock signal of the first clock signal transmission line and the data signal of the first data signal transmission line. On one hand, the radio frequency debugging can be avoided by manually replacing the impedance element in the matching circuit, so that the debugging time is saved and the efficiency is improved; on the other hand, the plurality of impedance values are used for carrying out radio frequency debugging on each ultrahigh frequency product, so that the optimal radio frequency index of each ultrahigh frequency product can be obtained, and the problem of poor product performance consistency caused by the individual difference of the resistance-capacitance inductance of the ultrahigh frequency products can be avoided.
With reference to the first aspect, in some embodiments, the first impedance tuner is specifically configured to tune a capacitance value of the first impedance variable device to a capacitance value corresponding to the first clock signal and the first data signal; and obtaining the impedance value of the first impedance tuner according to the capacitance value.
It will be appreciated that impedance is a resistance acting on a current in a circuit having a resistance, an inductance and a capacitance, and that changing the impedance value may be achieved by changing one or more of the resistance, the capacitance or the inductance. In the embodiment of the application, a control variable method is adopted, and only one variable of the capacitive reactance value is changed by fixing the two variables of the resistance value and the inductive reactance value unchanged, so that the multivariable problem is simplified into a single-variable problem, and the input of the single variable is rapidly adjusted according to the change of an observation dependent variable (the impedance value of a circuit is changed due to the sending change of the capacitive reactance value of the circuit, namely the sending change of the radio frequency index of the circuit is shown, and the dependent variable is the radio frequency index of the circuit).
In combination with the first aspect, in some embodiments, the circuit further comprises: an input port of the first device and an output port of the second device; a first end of the first impedance tuner is connected with the output port of the second device, and a second end of the first impedance tuner is connected with the input port of the first device; the first impedance value is used for enabling a radio frequency circuit comprising the first device, the second device and the first impedance tuner to obtain an optimal radio frequency index.
In combination with the first aspect, in some embodiments, the circuit further comprises: an input port of a third device and an output port of the third device, a first end of the first impedance tuner is connected with the input port of the third device, and a second end of the first impedance tuner is connected with the output port of the third device; the first impedance value is used to enable a radio frequency circuit comprising the third device and the first impedance tuner to obtain an optimal radio frequency specification.
Optionally, for a first device or a second device comprising two ports (including an input port and an output port), the impedance tuner may be connected in series with the first device and the second device in the radio frequency circuit; for a third device comprising four ports (comprising two input ports and two output ports), the impedance tuner and the third device can be selected to be connected in series in a radio frequency circuit, or the impedance tuner and the third device can be selected to be connected in parallel in the radio frequency circuit, and the adaptability is strong.
With reference to the first aspect, in some embodiments, the first clock signal and the first data signal comprise two-bit binary digital signals, and the first clock signal and the first data signal are combined from the two-bit binary digital signals; the first clock signal is 000, 001, 010, 011, 100, 101, 110, or 111, and the first data signal is 00, 01, 10, or 11.
With reference to the first aspect, in some embodiments, the first clock signal includes a three-bit binary digital signal, the first data signal includes a two-bit binary digital signal, the first clock signal is obtained by combining the three-bit binary digital signals, and the first data signal is obtained by combining the two-bit binary digital signals; the first clock signal is 00, 01, 10 or 11, and the first data signal is 00, 01, 10 or 11.
In the embodiment of the application, the association relationship between the digital signals of the first clock signal and the second clock signal and the impedance value is established, so that different impedance values are obtained by changing different combinations among the digital signals.
With reference to the first aspect, in some embodiments, the first device includes a power amplifier and the second device includes a duplexer.
With reference to the first aspect, in some embodiments, the third device comprises a power amplifier or a duplexer.
In the embodiment of the application, the impedance adjustable circuit is applied to key positions affecting radio frequency performance, such as the front and the back of a duplexer, so that the impedance value is changed for radio frequency debugging, the relatively accurate optimal radio frequency index is obtained, and the impedance value of the impedance adjustable circuit is stabilized at the impedance value corresponding to the optimal radio frequency index according to the optimal radio frequency index.
With reference to the first aspect, in some embodiments, the radio frequency indicator includes a receive sensitivity, an adjacent channel leakage ratio, and a transmit power; and obtaining the optimal radio frequency index under the conditions that the sensitivity reaches a first threshold value, the adjacent channel leakage ratio reaches a second threshold value, and the transmission power reaches a third threshold value.
Specifically, the step of detecting that the sensitivity reaches the first threshold includes: the sensitivity meets the 3rd Generation Partnership Project (3 GPP) protocol and is consistent with the budgeting result of the sensitivity, which is the calculation result of the sensitivity in the link budget of the circuit. The link budget includes: by evaluating various influencing factors (including sensitivity) in the signal propagation path of the circuit, the maximum propagation loss allowed by the circuit under a certain communication quality is obtained. The above-mentioned adjacent channel leakage ratio reaching the second threshold value includes: the 3GPP protocol is satisfied, and the margin of the adjacent channel leakage ratio is greater than or equal to 6 decibels. The above-mentioned transmit power reaching the third threshold includes: the transmit power satisfies 3GPP protocols. In the embodiment of the application, the radio frequency index refers to a plurality of radio frequency influence factors, and the obtained optimal radio frequency index has accuracy.
With reference to the first aspect, in some embodiments, the circuit further comprises: an output port of the fourth device, a second impedance tuner, an input port of the fifth device; a first end of the second impedance tuner is connected with an output port of the fifth device, and a second end of the second impedance tuner is connected with an input port of the fourth device; the second impedance tuner comprises a second clock signal transmission line, a second data signal transmission line and a second impedance variable device;
in response to the acquired second clock signal of the second clock signal transmission line and the acquired second data signal of the second data signal transmission line, the second impedance tuner adjusts the impedance value of the second impedance variable device to a second impedance value, which is an impedance value corresponding to the second clock signal and the second data signal.
Optionally, the fourth device and the second device are the same device, a first end of the first impedance tuner is connected to the input port of the first device, and a second end of the first impedance tuner is connected to the output port of the second device; a first end of the second impedance tuner is connected to the input port of the second device, and a second end of the second impedance tuner is connected to the output port of the fifth device.
Drawings
In order to more clearly illustrate the technical solution in the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below.
Fig. 1A is a schematic diagram of an impedance tunable circuit according to an embodiment of the present disclosure;
fig. 1B is a schematic diagram of a corresponding relationship between a data signal and a capacitance value of a variable device according to an embodiment of the present disclosure;
fig. 1C is a schematic diagram of another corresponding relationship between a data signal and a capacitance value of a variable device according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of another impedance tunable circuit provided in an embodiment of the present application;
fig. 3 is a schematic diagram of another impedance tunable circuit provided in an embodiment of the present application;
fig. 4 is a schematic diagram of another impedance tunable circuit provided in an embodiment of the present application.
Detailed Description
The present application is described in further detail below with reference to the attached figures.
The terminology used in the following embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the specification of the present application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In this application, "at least one" means one or more, "a plurality" means two or more, "at least two" means two or three and three or more, "and/or" for describing an association relationship of associated objects, which means that there may be three relationships, for example, "a and/or B" may mean: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one item(s) below" or similar expressions refer to any combination of these items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b," a and c, "" b and c, "or" a and b and c.
The following describes an impedance tunable circuit provided in the following embodiments of the present application.
In some embodiments, the present application provides an impedance tunable circuit as shown in fig. 1A, the impedance tunable circuit comprising: a first impedance tuner 100, the first impedance tuner 100 including a first clock signal transmission line 101, a first data signal transmission line 102, and an impedance variable device 103; in response to the acquired first clock signal of the first clock signal transmission line and the acquired first data signal of the first data signal transmission line, the first impedance tuner adjusts the impedance value of the impedance variable device to a first impedance value, which is an impedance value corresponding to the first clock signal and the first data signal; and the first impedance value is used for carrying out radio frequency debugging on the impedance adjustable circuit so as to obtain a radio frequency index.
Specifically, the first clock signal 101 transmission line is used for receiving a clock signal from the clock signal input interface 1101, and the second data signal transmission line is used for receiving a data signal from the data signal input interface 1201. Understandably, the clock signal input interface is used for providing a function of controlling the clock signal of the clock signal transmission line for users, and the data signal input interface is used for providing a function of controlling the data signal of the data signal transmission line for users. Optionally, the clock signal input interface or the data signal input interface may be an entity button, or may also be a software interface input box. Illustratively, the clock signal comprises a two-bit binary digital signal, the digital signal comprising a two-bit binary digital signal. The clock signal input interface or the data signal input interface is an entity button, and the entity button can have two options, wherein one option is used for representing that a binary bit is 0, and the other option is used for representing that the binary bit is 1; alternatively, the clock signal input interface or the data signal input interface includes two physical buttons, wherein one physical button is used for representing that the binary bit is 0, and the other physical button is used for representing that the binary bit is 1.
In an embodiment of the present application, the first impedance tuner is specifically configured to tune a capacitance value of the first impedance variable device to a capacitance value corresponding to the first clock signal and the first data signal; and obtaining the impedance value of the first impedance tuner according to the capacitance value.
It will be understood that the impedance values include the capacitance of the capacitor and the inductance of the inductor, and the impedance value Z is calculated as Z ═ R + j (X)l-Xc) Wherein R is a resistance value, j is an imaginary symbol, XlIs an inductance value, XcIn the embodiment of the present application, the impedance value is changed by changing the capacitive reactance value.
In the embodiment of the present application, the first impedance tuner adjusts the impedance value of the first impedance variable device 103 to a first impedance value in response to acquiring the first clock signal and the first data signal.
In some embodiments, the first clock signal and the first data signal comprise two-bit binary digital signals; the first clock signal is 00, 01, 10 or 11, and the first data signal is 00, 01, 10 or 11. A combination of one of the first clock signals and one of the first data signals corresponds to an impedance value.
Understandably, the first impedance tuner adjusts the capacitance value of the first impedance variable device to a capacitance value corresponding to the first clock signal and the awkward first data signal by changing the adjustable width and the adjustable area of the first impedance variable device.
In this embodiment of the present application, the first clock signal transmission line is configured to receive a plurality of clock signals, the first data signal transmission line is configured to receive a plurality of data signals, and the first impedance variable device is specifically configured to obtain a plurality of impedance values according to different combinations of any one of the plurality of clock signals and any one of the plurality of data signals; the impedance values are used for carrying out radio frequency debugging to obtain a plurality of radio frequency indexes; determining a first impedance value corresponding to an optimal radio frequency index in the plurality of radio frequency indexes; and taking a clock signal corresponding to the first impedance value as the first clock signal, and taking a data signal corresponding to the first impedance value as the first data signal.
In some embodiments, the clock signal is 00, 01, 10, or 11 and the data signal is 00, 01, 10, or 11. The combination of one clock signal and one data signal corresponds to one impedance value. Illustratively, the clock signal is combined with the data signal to obtain a four-bit binary number, one four-bit binary number corresponding to one impedance value. Specifically, as shown in fig. 1B, if the clock signal and the data signal are both 00 and the combined four-bit binary number is 0000, the first impedance tuner will adjust the capacitance of the impedance variable device to 0.4pF, and the impedance value corresponding to 0.4pF is the impedance value corresponding to the clock signal and the data signal. If the clock signal is 00 and the data signal is 01, the combined four-bit binary digit is 0001, and the corresponding capacitance value is 0.64 pF. If the clock signal is 10 and the data signal is 01, the combined four-bit binary digit is 1001, and the corresponding capacitance value is 2.56 pF.
Specifically, the first impedance tuner traverses different combinations of the clock signal and the data signal to obtain different impedance values, the impedance values are used for performing radio frequency debugging on the impedance-adjustable circuit to obtain a plurality of radio frequency indexes, and then the optimal radio frequency index is determined according to the plurality of radio frequency indexes. And acquiring a first impedance value corresponding to the optimal radio frequency index, taking a clock signal corresponding to the first impedance value as the first clock signal, and taking a data signal corresponding to the first impedance value as the first data signal. The first clock signal of the first signal transmission line of the impedance variable circuit is adjusted and held at the first clock signal, and the first data signal is adjusted and held at the first data signal.
For example, referring to fig. 1B, if the first impedance value corresponding to the optimal rf indicator is 2.56pF, the clock signal corresponding to the first impedance value is 10, and the data signal corresponding to the first impedance value is 01. Then, the first clock signal of the impedance adjustable circuit is adjusted and stabilized at the 10 signal, and the first data signal is adjusted and stabilized at the 01 signal.
In some other embodiments, the clock signal comprises a three-bit binary digital signal, and the data signal comprises a two-bit binary digital signal; the clock signal is 000, 001, 010, 011, 100, 101, 110, or 111 and the data signal is 00, 01, 10, or 11. The combination of one clock signal and one data signal corresponds to one impedance value.
Illustratively, the clock signal is combined with the data signal to obtain five-bit binary digits, one corresponding to one impedance value. Specifically, as shown in fig. 1C, if the clock signal is 000, the data signal is 00, and the combined five-bit binary number is 00000, the first impedance tuner adjusts the capacitance of the impedance variable device to 0.4pF, and the impedance value corresponding to 0.4pF is the impedance value corresponding to the clock signal and the data signal. If the clock signal is 010 and the data signal is 01, the combined five-bit binary digit is 01001, and the corresponding capacitance value is 2.61 pF.
In some other embodiments, in addition to the first impedance tuner shown in fig. 1A, the present application provides an impedance tunable circuit as shown in fig. 2, further comprising: an input port of the first device and an output port of the second device; a first end of the first impedance tuner is connected with the output port of the second device, and a second end of the first impedance tuner is connected with the input port of the first device; the first impedance value is used for enabling a radio frequency circuit comprising the first device, the second device and the first impedance tuner to obtain an optimal radio frequency index.
Specifically, in addition to the first impedance tuner shown in fig. 1A, the impedance tunable circuit further includes: the device comprises a first device, an input port of the first device, a second device and an output port of the second device. Wherein a first end of the first impedance tuner is connected to the output port of the second device, and a second end of the first impedance tuner is connected to the input port of the first device. That is, the first impedance tuner is connected in series with the first device and the second device in a circuit.
Understandably, the first impedance value is used for enabling a radio frequency circuit comprising the first device, the second device and the first impedance tuner to obtain an optimal radio frequency index. For example, a user may adjust a combination of the clock signal and the data signal according to the radio frequency indicator corresponding to the first impedance value, so that the radio frequency circuit obtains an optimal radio frequency indicator. Illustratively, the first impedance value is an impedance value corresponding to the optimal rf indicator (please refer to the above related description for how to obtain the impedance value corresponding to the optimal rf indicator by traversing the clock signal and the data signal).
In some other embodiments, in addition to the first impedance tuner shown in fig. 1A, the present application provides an impedance tunable circuit as shown in fig. 3, further comprising: an input port of a third device and an output port of the third device, a first end of the first impedance tuner is connected with the input port of the third device, and a second end of the first impedance tuner is connected with the output port of the third device; the first impedance value is used to enable a radio frequency circuit comprising the third device and the first impedance tuner to obtain an optimal radio frequency specification.
Specifically, the impedance tunable circuit includes, in addition to the first impedance tuner shown in fig. 1A: a third device, an input port of the third device, and an output port of the third device. A first end of the first impedance tuner is connected with an input port of the third device, and a second end of the first impedance tuner is connected with an output port of the third device; that is, the first impedance tuner is connected in parallel with the third device in a circuit.
Understandably, the first impedance value is used for enabling a radio frequency circuit comprising the third device and the first impedance tuner to obtain an optimal radio frequency index. Illustratively, the user adjusts the combination of the clock signal and the data signal according to the radio frequency index corresponding to the first impedance value, so that the radio frequency circuit obtains the optimal radio frequency index. Illustratively, the first impedance value is an impedance value corresponding to the optimal rf indicator (please refer to the above related description for how to obtain the impedance value corresponding to the optimal rf indicator by traversing the clock signal and the data signal).
In some other embodiments, in addition to the first impedance tuner, the first device, the input port of the first device, the second device, and the output port of the second device shown in fig. 1B, the impedance-tunable circuit provided by the present application as shown in fig. 4 further includes: a second impedance tuner, a fourth device, an input port of the fourth device, a fifth device, and an output port of the fifth device. Wherein a first end of the second impedance tuner is connected to an output port of the fifth device, and a second end of the second impedance tuner is connected to an input port of the fourth device. The second impedance tuner comprises a second clock signal transmission line, a second data signal transmission line and a second impedance variable device; in response to the acquired second clock signal of the second clock signal transmission line and the acquired second data signal of the second data signal transmission line, the second impedance tuner adjusts the impedance value of the second impedance variable device to a second impedance value, which is an impedance value corresponding to the second clock signal and the second data signal.
Optionally, the fourth device and the second device may be different devices or may be the same device. Illustratively, the fourth device and the second device are different devices, and the fourth device and the second device are connected through a transmission line, specifically, an output port of the fourth device is connected to an input port of the second device. Illustratively, the fourth device and the second device are the same device, the first end of the first impedance tuner is connected to the input port of the first device, and the second end of the first impedance tuner is connected to the output port of the second device; a first end of the second impedance tuner is connected to the input port of the second device, and a second end of the second impedance tuner is connected to the output port of the fifth device.
Understandably, the first impedance value and the second impedance value are used for enabling a radio frequency circuit comprising the first impedance tuner, the second impedance tuner, the first device, the second device, the fourth device and the fifth device to obtain an optimal radio frequency index. Illustratively, the user adjusts the combination of the clock signal and the data signal of the first impedance coordinator and the combination of the clock signal and the data signal of the second impedance coordinator according to the radio frequency indexes corresponding to the first impedance value and the second impedance value, so that the radio frequency circuit obtains the optimal radio frequency index. Illustratively, traversing the clock signal and the data signal of the first impedance tuner and traversing the clock signal and the data signal of the second impedance tuner results in different combinations of first impedance values and second impedance values. And using the combination of the different first impedance values and the second impedance values for radio frequency debugging to obtain a plurality of radio frequency indexes, and determining the optimal radio frequency index according to the radio frequency indexes.
In some embodiments, the first device is a power amplifier, the second device is a duplexer, and the third device is a power amplifier or a duplexer.
In the embodiment of the present application, the radio frequency index includes a receiving sensitivity, an adjacent channel leakage ratio, and a transmission power; and obtaining the optimal radio frequency index under the conditions that the sensitivity reaches a first threshold value, the adjacent channel leakage ratio reaches a second threshold value, and the transmission power reaches a third threshold value.
Specifically, the step of detecting that the sensitivity reaches the first threshold includes: the sensitivity meets the 3rd Generation Partnership Project (3 GPP) protocol and is consistent with the budgeting result of the sensitivity, which is the calculation result of the sensitivity in the link budget of the circuit. The link budget includes: by evaluating various influencing factors (including sensitivity) in the signal propagation path of the circuit, the maximum propagation loss allowed by the circuit under a certain communication quality is obtained. The above-mentioned adjacent channel leakage ratio reaching the second threshold value includes: the 3GPP protocol is satisfied, and the margin of the adjacent channel leakage ratio is greater than or equal to 6 decibels. The above-mentioned transmit power reaching the third threshold includes: the transmit power satisfies 3GPP protocols.
By implementing the circuit provided by the embodiment of the application, the corresponding impedance value can be selected by modifying the clock signal of the first clock signal transmission line and the data signal of the first data signal transmission line, so that the condition that the impedance element in the matching circuit is manually replaced to carry out radio frequency debugging is avoided, the debugging time is saved, and the efficiency is improved.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. An impedance tunable circuit, comprising:
a first impedance tuner including a first clock signal transmission line, a first data signal transmission line, and an impedance variable device;
in response to the acquired first clock signal of the first clock signal transmission line and the acquired first data signal of the first data signal transmission line, the first impedance tuner adjusts the impedance value of the impedance variable device to a first impedance value, which is an impedance value corresponding to the first clock signal and the first data signal; and the first impedance value is used for carrying out radio frequency debugging on the impedance adjustable circuit so as to obtain a radio frequency index.
2. The circuit of claim 1, wherein the first clock signal transmission line is to receive a plurality of clock signals, the first data signal transmission line is to receive a plurality of data signals,
the impedance variable device is specifically configured to obtain a plurality of impedance values according to different combinations of any one of the plurality of clock signals and any one of the plurality of data signals; the impedance values are used for carrying out radio frequency debugging to obtain a plurality of radio frequency indexes;
determining a first impedance value corresponding to an optimal radio frequency index in the plurality of radio frequency indexes;
and taking a clock signal corresponding to the first impedance value as the first clock signal, and taking a data signal corresponding to the first impedance value as the first data signal.
3. The circuit of claim 1 or 2,
the first impedance tuner is specifically configured to tune a capacitance value of the first impedance variable device to a capacitance value corresponding to the first clock signal and the first data signal;
and obtaining the impedance value of the first impedance variable device according to the capacitance value.
4. The circuit of claim 1 or 2, wherein the circuit further comprises:
an input port of the first device and an output port of the second device;
a first end of the first impedance tuner is connected with the output port of the second device, and a second end of the first impedance tuner is connected with the input port of the first device;
the first impedance value is used for enabling a radio frequency circuit comprising the first device, the second device and the first impedance tuner to obtain an optimal radio frequency index.
5. The circuit of claim 1 or 2, wherein the circuit further comprises:
an input port of a third device and an output port of the third device, a first end of the first impedance tuner is connected with the input port of the third device, and a second end of the first impedance tuner is connected with the output port of the third device;
the first impedance value is used to enable a radio frequency circuit comprising the third device and the first impedance tuner to obtain an optimal radio frequency specification.
6. The circuit of claim 1 or 2, wherein the first clock signal and the first data signal comprise two-bit binary digital signals; the first clock signal is 00, 01, 10 or 11, and the first data signal is 00, 01, 10 or 11.
7. The circuit of claim 2, wherein a combination of one of said clock signals and one of said data signals corresponds to an impedance value.
8. The circuit of claim 4, wherein the first device comprises a power amplifier and the second device comprises a duplexer.
9. The circuit of claim 5, wherein the third device comprises a power amplifier or a duplexer.
10. The circuit of claim 2, wherein the radio frequency indicators include receive sensitivity, adjacent channel leakage ratio, and transmit power; and obtaining the optimal radio frequency index under the conditions that the sensitivity reaches a first threshold value, the adjacent channel leakage ratio reaches a second threshold value, and the transmission power reaches a third threshold value.
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| CN202110730472.2A CN113541632A (en) | 2021-06-29 | 2021-06-29 | Impedance adjustable circuit |
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