CN113541466A

CN113541466A - Circuit and method for prolonging power-down retention time

Info

Publication number: CN113541466A
Application number: CN202110604885.6A
Authority: CN
Inventors: 不公告发明人
Original assignee: Mornsun Guangzhou Science and Technology Ltd
Current assignee: Mornsun Guangzhou Science and Technology Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2021-10-22

Abstract

The invention provides a circuit and a method for prolonging power-down holding time. The PFC circuit, the time extension circuit and the DC-DC circuit are sequentially connected in series, and the first output end of the control circuit is connected with the PFC circuit. The time prolonging circuit comprises a switch S2 and a capacitor C2. The switch S2 is connected in series with the capacitor C2 and is connected between the positive output terminal and the negative output terminal of the PFC circuit. The control end of the switch S2 is connected with the second output end of the control circuit, and the connection point of the switch S2 and the capacitor C2 is connected with the first input end of the control circuit. When the control method provided by the invention is applied to the circuit, the power-down holding time of the follow-up PFC under low-voltage input can be obviously prolonged under the condition that the size and the cost of a switching power supply are hardly increased.

Description

Circuit and method for prolonging power-down retention time

Technical Field

The invention relates to the field of power factor correction, in particular to a circuit and a method for prolonging power-down retention time.

Background

With the rapid development of modern industry, the nonlinear load of the power system is increasing. Harmonic currents generated by these nonlinear loads are injected into the grid, so that the voltage waveform of the utility grid is distorted, the environment of the grid is seriously polluted, and Power Factor Correction (PFC) is performed to reduce and eliminate the harmonic waves, so that the input current close to a sine wave and the power factor close to 1 are obtained.

The output voltage Vo of the PFC circuit is generally a stable output voltage value (regulator PFC), and the output of the PFC circuit is usually connected to a DC-DC converter. The voltage-stabilizing PFC circuit is simple in design and mature in technical scheme. However, the core volume required by the PFC circuit is usually large, and the loss during the switching process is large, so as to make up for the above defects, a PFC circuit (follow-up PFC) with a variable output voltage is proposed in the industry, and the output voltage of the PFC circuit changes with the change of the input voltage. For example, in a PFC controller L6563 of the ST company, the TBO pin of the PFC controller is externally connected with a resistor, so that the output voltage can change along with the input voltage, and the change trend is shown in fig. 1. At the time of the lowest input voltage Vin _ min, the output voltage thereof is Vo _ min, and at the time of the highest input voltage Vin _ max, the output voltage thereof is Vo _ max. Compared with a follow-up PFC and a voltage-stabilizing PFC, the size of a magnetic core of the follow-up PFC can be reduced by about 40%, and the low-voltage efficiency of the follow-up PFC is improved by about 1.2%. However, the output voltage of the follow-up PFC is lower under low voltage, the energy stored by the capacitor is reduced, and the power-down holding time of the follow-up PFC is obviously reduced compared with the voltage-stabilizing PFC.

In the case of a sudden power failure, many electronic devices, instruments, etc. have no time to react, resulting in loss of data or interruption of service. Therefore, more and more electronic devices and instruments are required to provide a long power-down retention function.

To maintain a long power-down retention time, it is common practice to: 1, adding a large-capacity energy storage capacitor or super capacitor at the PFC output end; 2. an additional circuit, such as that disclosed in application No. 201320603095.7, is added to the circuit for prolonging the power-down retention time, which is shown in fig. 2.

The increase of the energy storage capacitor or super capacitor with large capacity usually requires more cost and volume, and has no economic applicability. The 201320603095.7 patent application in a follow-up PFC circuit has the following problems:

1. the output ripple voltage of the PFC circuit is small, usually about 10V, the effect of the PFC circuit is basically equivalent to the effect of direct parallel connection of a capacitor C1 and a capacitor C2, and therefore a large energy storage capacitor is needed, and economic applicability is not achieved;

2. the device usually has leakage current, the voltage of the capacitor C2 is released to be equal to the voltage of the capacitor C1 after long-term operation, the effect is the same as that of the capacitor C2 directly connected in parallel with the output end, a large energy storage capacitor is also needed, and the device does not have economic applicability;

3. when the current conducting device is turned on, the capacitor C2 and the capacitor C1 are prone to generate large impact current, and the device is prone to be damaged.

Therefore, the existing technology for prolonging the power-down retention time is obviously insufficient when applied to the follow-up PFC circuit, and the problem of short power-down retention time of the follow-up PFC circuit under low-voltage input cannot be economically and efficiently solved.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a circuit and a method for prolonging power-down holding time. The invention can obviously prolong the power-down holding time under the low-voltage input of the follow-up PFC without increasing the volume and the cost of the switching power supply.

The invention provides a circuit for prolonging power-down holding time, which comprises a PFC circuit, a time prolonging circuit, a DC-DC circuit and a control circuit. The PFC circuit, the time extension circuit and the DC-DC circuit are sequentially connected in series, and the first output end of the control circuit is connected with the PFC circuit. The time extension circuit includes a switch S2 and a capacitor C2. One end of the switch S2 is electrically coupled with one end of the capacitor C2, and the switch S2 and the capacitor C2 are connected between the positive output terminal and the negative output terminal of the PFC circuit. The control end of the switch S2 is connected with the second output end of the control circuit, and one end of the capacitor C2 is also connected with the first input end of the control circuit.

Preferably, the power-down retention time prolonging circuit further comprises a resistor R1, one end of the switch S2 is electrically connected with one end of the capacitor C2 through a resistor R1, and the resistor R1 is used for limiting current.

Preferably, the power-down retention time prolonging circuit further comprises a diode D1, the switch S2 is connected in parallel with the diode D1, and one end of the capacitor C2 is further connected with the cathode of the diode D1.

On the basis that the power-down retention time prolonging circuit comprises a diode D1, the power-down retention time prolonging circuit preferably further comprises a resistor R1, one end of a switch S2 is electrically connected with one end of a capacitor C2 through a resistor R1, and a resistor R1 is used for limiting current.

Preferably, the switch S2 is a MOSFET or an IGBT or a thyristor or a relay.

A control method for prolonging the power-down retention time is suitable for the circuit for prolonging the power-down retention time without a diode D1, and comprises the following steps:

step one, starting a power supply to ensure that input voltage is normal, starting a control circuit to work, and executing step two;

step two, closing a switch S2, setting the output voltage Vo of the PFC circuit to be Vo _ p through a control circuit, then judging whether the voltage Vc2 reaches Vo _ p, if not, performing step two, and if so, performing step three;

step three: turning off a switch S2, setting the output voltage Vo of the PFC circuit to be the rated voltage Vo _ nom through a control circuit, rapidly reducing the output voltage Vo from Vo _ p to Vo _ nom, judging whether the voltage Vc2 is reduced to Vo _ th, if so, returning to execute the second step, and if not, executing the fourth step;

step four: judging whether the power failure holding state is entered, if not, executing a third step, and if so, executing a fifth step;

step five: the control circuit controls the switch S2 to conduct soft turn-on, and gradually increases the conducting time of the switch S2 every period.

The invention also provides a control method for prolonging the power-down retention time, which is suitable for the power-down retention time prolonging circuit comprising the diode D1 and comprises the following steps:

step two, setting the output voltage Vo of the PFC circuit to be Vo _ p through the control circuit, then judging whether the voltage Vc2 reaches Vo _ p, if not, performing step two, and if so, performing step three;

step three: setting the output voltage Vo of the PFC circuit as the rated voltage Vo _ nom through the control circuit, rapidly reducing the output voltage Vo from Vo _ p to Vo _ nom, judging whether the voltage Vc2 is reduced to Vo _ th, if so, returning to execute the step two, and if not, executing the step four;

Interpretation of related terms:

electrically coupling: including direct or indirect connections, and also connections such as inductive couplings.

The invention only uses the switch and the capacitor to construct the time prolonging circuit, and has the following technical effects:

1. voltage following is realized under the condition that the size and the cost of the switching power supply are hardly increased;

2. the circuit of the invention can obviously prolong the power-down retention time only by adding a capacitor with smaller capacity;

3. in addition, the impulse current is reduced in the process of turning on the device;

4. compared with the traditional solution, the method has the advantages of smaller volume, lower cost and higher reliability.

Drawings

FIG. 1 is a graph showing the variation trend of the output voltage and the input voltage of a follower-type PFC;

FIG. 2 is a schematic diagram of a prior art circuit for extending power down retention time;

FIG. 3 is a schematic circuit diagram according to an embodiment of the present invention;

FIG. 4 is a graph of voltage waveforms at key nodes at various stages of the circuit of the present invention;

FIG. 5 is a flowchart of a control method according to a first embodiment of the present invention;

FIG. 6 is a schematic circuit diagram according to a second embodiment of the present invention;

FIG. 7 is a schematic circuit diagram of a third embodiment of the present invention;

FIG. 8 is a flowchart of a control method according to a third embodiment of the present invention;

fig. 9 is a schematic circuit diagram of a fourth embodiment of the present invention.

Detailed Description

First embodiment

As shown in fig. 3, which is a schematic circuit diagram of a first embodiment of the present invention, a circuit for prolonging a power-down retention time includes a PFC circuit, a time prolonging circuit, a DC-DC circuit, and a control circuit. The PFC circuit, the time extension circuit and the DC-DC circuit are sequentially connected in series, and the first output end of the control circuit is connected with the PFC circuit. The PFC circuit includes a rectifier bridge DB1, an inductor L1, a switch S1, a diode D1, and a capacitor C1. A first input end and a second input end of the rectifier bridge DB1 are respectively connected with the L end and the N end of the alternating voltage, and a first output end of the rectifier bridge DB1 is connected with one end of the inductor L1; the other end of the inductor L1 is connected to one end of the switch S1 and the anode of the diode D1, the cathode of the diode D1 is connected to one end of the capacitor C1, and the connection point serves as the output positive terminal of the PFC circuit; the other end of the capacitor C1 is connected with the other end of the switch S1 and a second output end of the rectifier bridge DB1, and the connection point is used as an output negative terminal of the PFC circuit; the control terminal of the switch S1 is connected to a first output terminal of the control circuit, and the control circuit controls the switch S1 to be turned on and off by outputting a first output signal Q1. The time extension circuit includes a switch S2 and a capacitor C2. The switch S2 is connected in series with the capacitor C2 and is connected between the positive output terminal and the negative output terminal of the PFC circuit. The switch S2 is connected to the positive output terminal and the capacitor C2 is connected to the negative output terminal. The control end of the switch S2 is connected to the second output end of the control circuit, a second output signal Q2 of the control circuit is used to control the switch S2 to be turned on and off, the connection point of the switch S2 and the capacitor C2 is connected to the first input end of the control circuit, and the control circuit detects the voltage amplitude Vc2 of the capacitor C2 through the first input end. The switch S2 may be a MOSFET, an IGBT, a thyristor, a relay, or the like. The waveforms of the output voltage Vo of the PFC circuit and the voltage Vc2 of the capacitor C2 are shown in fig. 4.

As shown in fig. 5, the specific working steps and sequence of the first embodiment are as follows:

step two, closing a switch S2, setting the output voltage Vo of the PFC circuit to be Vo _ p through a control circuit, normally setting the voltage value of Vo _ p to be larger than or equal to the maximum output voltage value Vo _ max of the PFC circuit, wherein the step is a starting step, the output voltage Vo of the PFC circuit is Vo _ p at the step, gradually increasing the voltage Vc2 of a capacitor C2, and judging whether the voltage Vc2 reaches Vo _ p, if not, performing step two, and if so, performing step three;

step three: turning off a switch S2, setting the output voltage Vo of the PFC circuit to be the rated voltage Vo _ nom through a control circuit, rapidly reducing the output voltage Vo from Vo _ p to Vo _ nom, basically keeping the voltage Vc2 of a capacitor C2 to be Vo _ p, reducing the voltage Vc2 at an extremely slow slope due to some leakage current of the device at the stage, judging whether the voltage Vc2 is reduced to Vo _ th, normally setting the voltage value of Vo _ th to be less than Vo _ p, if yes, returning to the step two, and if not, executing the step four;

step four: judging whether to enter a power-down holding state, wherein the circuit is generally regarded as entering the power-down holding state under the conditions of input voltage shutoff, PFC circuit protection or failure, if not, executing a third step, and if so, executing a fifth step;

step five: the control circuit controls the switch S2 to conduct soft turn-on, the conducting time of the switch S2 is gradually increased every period, the current stress born by the device is reduced, and the risk of device damage is reduced.

The circuit of this embodiment stores more energy in the capacitor C2 through the start-up phase or the normal operation phase according to the formula

Thold＝0.5*C*(Vo_p²-V1²) The ratio of the ratio to the ratio of,

thold is power-down holding time, C is the capacitance value of the capacitor C2, Vo _ P is the voltage value of the capacitor C2 at the power-down starting moment, V1 is the voltage value of the capacitor C2 at the power-down ending moment, and P is output power.

The value of V1 is the lowest operating voltage of the DC-DC circuit, and when the voltage Vo _ p is higher, the capacitance is smaller, which can significantly increase the power-down retention time of the circuit.

Second embodiment

As shown in fig. 6, which is a schematic diagram of a second embodiment of the present invention, compared with the first embodiment, the difference is that: the time extension circuit further comprises a resistor R1, and the switch S2 and the capacitor C2 are connected in series with the resistor R1 and connected between the positive output terminal and the negative output terminal of the PFC circuit. The control end of the switch S2 is connected with the second output end of the control circuit, and the connection point of the resistor R1 and the capacitor C2 is connected with the first input end of the control circuit.

The resistor R1 is used for limiting current, so that the current stress of the device in the switching-on process of the switch S2 is reduced to a greater extent, and the selection of the device with lower specification is facilitated.

The control method and the circuit operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.

Third embodiment

As shown in fig. 7, which is a diagram of the three principles of the embodiment of the present invention, compared with the first embodiment, the differences are: the time extension circuit of the embodiment further includes a diode D2, the switch S2 is connected in parallel with the diode D2, the anode of the diode D2 is connected to the positive output terminal, the cathode of the diode is connected to one end of the capacitor C2, and the connection point of the switch S2, the diode D2 and the capacitor C2 is connected to the first input terminal of the control circuit.

As shown in fig. 8, the specific working steps and sequence of this embodiment are different from those of the first embodiment in that: when step two is executed, the switch S2 is not closed; in step three, there is no operation of the off switch S2.

Fourth embodiment

As shown in fig. 9, a four-principle diagram of the embodiment of the present invention is different from the three-principle diagram of the embodiment in that: the time extension circuit of the embodiment further includes a resistor R1, the switch S2, the resistor R1 and the capacitor C2 are sequentially connected in series and connected between the positive output terminal and the negative output terminal of the PFC circuit, the switch S2 is connected in parallel with the diode D2, the anode of the diode D2 is connected to the positive output terminal, the cathode of the diode D2 is connected to one end of the resistor R1, the connection point between the other end of the resistor R1 and the capacitor C2 is connected to the first input terminal of the control circuit, and the function of the resistor R1 is the same as that of the resistor R1 mentioned in the second embodiment.

The control method and the circuit of the present embodiment have the same working principle as the embodiments, and are not described herein again.

The above disclosure is only a preferred embodiment of the present invention, but the present invention is not limited thereto, and those skilled in the art should make modifications to the present invention without departing from the core idea of the present invention, and fall within the protection scope of the claims of the present invention.

Claims

1. The utility model provides a time circuit is kept in extension power failure, includes PFC circuit, time extension circuit, DC-DC circuit and control circuit, PFC circuit, time extension circuit, DC-DC circuit series connection in proper order, and control circuit is connected its characterized in that with PFC circuit, time extension circuit respectively:

the time extension circuit comprises a switch S2 and a capacitor C2, one end of the switch S2 is electrically connected with one end of the capacitor C2, the switch S2 and the capacitor C2 are connected between the output positive end and the output negative end of the PFC circuit, the control end of the switch S2 is connected with the second output end of the control circuit, and one end of the capacitor C2 is further connected with the first input end of the control circuit.

2. The circuit of claim 1, wherein: the circuit also comprises a resistor R1, one end of a switch S2 is electrically connected with one end of a capacitor C2 through a resistor R1, and the resistor R1 is used for limiting current.

3. The circuit of claim 1, wherein: the LED driving circuit further comprises a diode D1, the switch S2 is connected with the diode D1 in parallel, and one end of the capacitor C2 is further connected with the cathode of the diode D1.

4. The circuit of claim 3, wherein: the circuit also comprises a resistor R1, one end of a switch S2 is electrically connected with one end of a capacitor C2 through a resistor R1, and the resistor R1 is used for limiting current.

5. The circuit of any of claims 1 to 4, wherein: the switch S2 is a MOSFET or IGBT or thyristor or relay.

6. A control method for prolonging power-down retention time, which is applied to the circuit of claim 1 or 2, and is characterized by comprising the following steps:

7. A control method for prolonging power-down retention time, which is applicable to the circuit of claim 3 or 4, and is characterized by comprising the following steps: