CN113541098A - Power supply protection circuit and antenna device - Google Patents

Power supply protection circuit and antenna device Download PDF

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Publication number
CN113541098A
CN113541098A CN202111076557.XA CN202111076557A CN113541098A CN 113541098 A CN113541098 A CN 113541098A CN 202111076557 A CN202111076557 A CN 202111076557A CN 113541098 A CN113541098 A CN 113541098A
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China
Prior art keywords
resistor
transistor
pin
protection circuit
power supply
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Pending
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CN202111076557.XA
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Chinese (zh)
Inventor
来杰
高佳
黄晓峰
宋磊
贾惠柱
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Hangzhou Boya Hongtu Video Technology Co ltd
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Hangzhou Boya Hongtu Video Technology Co ltd
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Priority to CN202111076557.XA priority Critical patent/CN113541098A/en
Publication of CN113541098A publication Critical patent/CN113541098A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H02H3/10—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current additionally responsive to some other abnormal electrical conditions
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1203—Circuits independent of the type of conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses power protection circuit and antenna equipment. The power supply protection circuit comprises a first transistor, a first resistor, a second resistor, a third resistor, a PMOS (P-channel metal oxide semiconductor) tube and a capacitor; the second pin of the first transistor is connected with the first end of the first resistor; the first end of the second resistor is connected with the second end of the first resistor; the second end of the second resistor and the first end of the third resistor are respectively connected with the first pin of the first transistor; the second end of the third resistor is grounded; the source electrode of the PMOS tube is connected with the second end of the first resistor; the grid electrode of the PMOS tube is connected with the collector electrode of the first transistor; the drain electrode of the PMOS tube is connected with the first end of the capacitor; the second terminal of the capacitor is grounded. The power supply protection circuit is simple in structure and low in cost, can quickly and effectively protect a power supply when a load is short-circuited, provides overcurrent protection for the power supply, and can well meet the requirements of practical application.

Description

Power supply protection circuit and antenna device
Technical Field
The application relates to the technical field of circuits, in particular to a power supply protection circuit and antenna equipment.
Background
In the field of circuit technology, a short circuit of a load can cause damage to a power supply and even cause accidents such as fire or explosion. How to realize a protection circuit which has a simple structure and can quickly and effectively protect a power supply when a load is in short circuit so as to avoid the power supply from being damaged by the short circuit of the load is a technical problem which is continuously solved by technical personnel in the field.
Disclosure of Invention
The application aims to provide a power supply protection circuit and an antenna device. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of an embodiment of the present application, there is provided a power protection circuit, including a first transistor, a first resistor, a second resistor, a third resistor, a PMOS transistor, and a capacitor; the second pin of the first transistor is connected with the first end of the first resistor; the first end of the second resistor is connected with the second end of the first resistor; a second end of the second resistor and a first end of the third resistor are respectively connected with a first pin of the first transistor; the second end of the third resistor is grounded; the source electrode of the PMOS tube is connected with the second end of the first resistor; the grid electrode of the PMOS tube is connected with the collector electrode of the first transistor; the drain electrode of the PMOS tube is connected with the first end of the capacitor; the second end of the capacitor is grounded.
In some embodiments of the present application, the power protection circuit further includes a bidirectional protection diode, a first end of the bidirectional protection diode is connected to the drain of the PMOS transistor, and a second end of the bidirectional protection diode is grounded.
In some embodiments of the present application, the power protection circuit further includes a processor, a second transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; the first end of the fourth resistor is connected with the grid electrode of the PMOS tube; a third pin of the second transistor is connected with a second end of the fourth resistor; a second pin of the second transistor is grounded; a first end of the fifth resistor is connected with a first pin of the second transistor; the second end of the fifth resistor is respectively connected with the processor and the first end of the sixth resistor; a second end of the sixth resistor is grounded; the first end of the seventh resistor is connected with the drain electrode of the PMOS tube; the second end of the seventh resistor is respectively connected with the first end of the eighth resistor and the processor; and the second end of the eighth resistor is grounded.
In some embodiments of the present application, the first transistor is a PMOS transistor or a PNP transistor; the first pin of the first transistor is the grid electrode of the PMOS tube or the base electrode of the PNP type triode, the second pin of the first transistor is the source electrode of the PMOS tube or the emitting electrode of the PNP type triode, and the third pin of the first transistor is the drain electrode of the PMOS tube or the collecting electrode of the PNP type triode.
In some embodiments of the present application, the second transistor is an NMOS transistor or an NPN transistor; the first pin of the second transistor is a gate of the NMOS transistor or a base of the NPN-type triode, the second pin of the second transistor is a source of the NMOS transistor or an emitter of the NPN-type triode, and the third pin of the second transistor is a drain of the NMOS transistor or a collector of the NPN-type triode.
In some embodiments of the present application, the processor is a single chip or an ARM chip.
In some embodiments of the present application, the first resistance is 2.7 Ω, the second resistance is 1000 Ω, the third resistance is 10000 Ω, the capacitance is 0.1 μ F, and the power supply is 5V.
According to another aspect of the embodiments of the present application, there is provided an antenna apparatus including an antenna and the power protection circuit of any one of the above, wherein the antenna is connected to the drain of the PMOS transistor.
The technical scheme provided by one aspect of the embodiment of the application can have the following beneficial effects:
the power supply protection circuit provided by the embodiment of the application has the advantages of simple structure and low cost, can quickly and effectively protect a power supply when a load is short-circuited, provides overcurrent protection for the power supply, and can well meet the requirements of practical application.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a circuit diagram of a first embodiment of the present application;
fig. 2 shows a circuit diagram of a second embodiment of the present application;
fig. 3 shows a circuit diagram of a third embodiment of the present application;
fig. 4 shows a circuit diagram of embodiment four of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Example one
As shown in fig. 1, the present embodiment provides a power protection circuit, which includes a P-channel MOS transistor Q13, a PNP transistor Q15, a capacitor C207, a resistor R320, a resistor R321, and a resistor R322.
Q13 is a P-channel MOS transistor with pin 1 as gate G, pin 2 as source S, pin 3 as drain D, source S connected to input, drain D connected to output. When the voltage V between the gate G and the source SGSWhen the threshold is less than the threshold, the drain D and the source S are conducted.
Q15 is a PNP triode with pin 1 as base B, pin 2 as emitter E, and pin 3 as collector C. When the voltage V between the base and the emitterBEIs negative and the voltage V between the base and the collectorBCWhen the current is positive, the PNP type triode Q15 is conducted.
The first end of the resistor R322 is connected with pin 2 of Q15, and pin 2 of Q15 is connected with a power supply V; the first end of R320 is connected with the second end of R322, and the second end of R320 is connected with pin 1 of Q15; the first end of the R321 is connected with the second end of the R320, and the second end of the R321 is grounded; pin 2 of Q13 is connected to the second end of R322; the first ends of the pin 1 of the Q13 and the pin 3 of the R323 are respectively connected with the pin 3 of the Q15; the first terminal of C207 is connected to pin 3 of Q13 and the second terminal of C207 is connected to ground. Pin 3 of Q13 is connected to the load connection ANT _ T. The load connection terminal ANT _ T is used for connecting a load. The load may be, for example, an antenna or the like.
When the load is short-circuited, the current passing through the R322 is suddenly increased, the voltage on the R322 is suddenly increased, the voltage between the source and the drain of the Q13 is instantly reduced to be less than the conducting voltage, and the source and the drain of the Q13 are not conducted any more, so that the power supply V is prevented from being damaged due to the short-circuit of the load.
The power supply protection circuit provided by the embodiment has the advantages of simple structure and low cost, can quickly and effectively protect a power supply when a load is in a short circuit, provides overcurrent protection for the power supply, and can well meet the requirements of practical application.
Example two
As shown in fig. 2, the power protection circuit of the second embodiment includes the structure of the first embodiment, and further includes a bidirectional protection diode D28. The first terminal of D28 is connected to pin 3 of Q13, and the second terminal of D28 is connected to ground. D28 is a bidirectional protection diode, and when the ANT _ T voltage is too high due to an accident (for example, when the load is an antenna and the antenna is struck by lightning), the power supply V can be prevented from being damaged by the too high voltage, so as to perform an isolation protection function, that is, an overvoltage protection function.
The power supply protection circuit provided by the embodiment can not only quickly and effectively protect a power supply when a load is in a short circuit, and provide overcurrent protection for the power supply, but also provide overvoltage protection, so that the power supply is prevented from being damaged due to the fact that the load inputs overlarge voltage.
EXAMPLE III
As shown in fig. 3, the present embodiment provides a power protection circuit, which includes a processor, a P-channel MOS transistor Q13, an NPN type triode Q14, a PNP type triode Q15, a capacitor C207, a bidirectional protection diode D28, a resistor R320, a resistor R321, a resistor R322, a resistor R323, a resistor R324, a resistor R325, a resistor R326, and a resistor R327.
Q13 is a P-channel MOS transistor with pin 1 as gate G and pin 2 as source SPin 3 is a drain D, whose source S is connected to the input terminal and drain D is connected to the output terminal. When the voltage V between the gate G and the source SGSWhen the threshold is less than the threshold, the drain D and the source S are conducted.
Q14 is an NPN type triode with pin 1 as base B, pin 2 as emitter E, and pin 3 as collector C. When V isBEIs positive, VBCWhen the voltage is negative, the NPN type triode can be conducted.
Q15 is a PNP triode with pin 1 as base B, pin 2 as emitter E, and pin 3 as collector C. When the voltage V between the base and the emitterBEIs negative and the voltage V between the base and the collectorBCWhen the current is positive, the PNP type triode Q15 is conducted.
The first end of the resistor R322 is connected with pin 2 of Q15, and pin 2 of Q15 is connected with a power supply; the first end of R320 is connected with the second end of R322, and the second end of R320 is connected with pin 1 of Q15; the first end of the R321 is connected with the second end of the R320, and the second end of the R321 is grounded; pin 2 of Q13 is connected to the second end of R322; the first ends of the pin 1 of the Q13 and the pin 3 of the R323 are respectively connected with the pin 3 of the Q15; the second end of R323 is connected to pin 3 of Q14; pin 2 of Q14 is grounded; the first end of the C207 and the first end of the R326 are respectively connected with a pin 3 of the Q13, and the second end of the C207 is grounded; the first end of the D28 is connected with the pin 3 of the Q13, and the second end of the D28 is grounded; the second end of R326 is connected with the first end of R327, and the second end of R327 is grounded; a second end of the R326 is connected with the processor; pin 1 of Q14 connects to a first end of R324; a first end of R325 is connected to a second end of R324; the second end of R325 is grounded; a second end of R324 is coupled to the processor.
The processor can be a microprocessor, for example, an ARM chip or a single chip microcomputer. The power supply V is used to supply voltage to the load connection.
When the processor controls the ANT _ CTRL output value to be low, the base of Q14 is also low, i.e., there is no conducting voltage between pin 1 and pin 2 of Q14, the PN junction is not conducting, and the 2 and 3 stages of Q14 are also not conducting through the triode characteristic. Pin 3 of Q15 is no return path and is non-conductive. And further V of Q13GSThe reverse voltage difference is not conducted, so that the drain D and the source S of the Q13 are also not conducted, and the ANT _ T is not conductedAnd (6) outputting the voltage.
When the processor controls the ANT _ CTRL output value to be at a high level, the base of Q14 is also at a high level, i.e., there is a conduction voltage between pin 1 and pin 2 of Q14, the PN junction is turned on, and conduction is performed between pin 2 and pin 3 of the transistor Q14. Pin 2 and pin 3 of Q15 are connected, and through the R323 voltage divider circuit, pin 1 of Q13 gets a high voltage, and a voltage difference is generated between the gate and source of Q13, and the drain D and source S of Q13 are connected, and ANT _ T has a voltage output.
When the antenna connected with the load connection end ANT _ T is in short circuit, the voltage drop on the resistor R322 can be increased, the voltage value affecting an ANT _ OVERLOAD point is further reduced to be lower than a normal threshold value in a linkage mode, the ANT _ CTRL output value is immediately controlled to be changed into a low level after the processor detects that the voltage value is reduced to be lower than the normal threshold value, at the moment, Q13 is not conducted, the power output of the ANT _ T is cut off, the 5V power supply is guaranteed to be always kept in a normal range under the condition that the short circuit occurs, the influence of the ANT _ T short circuit is avoided, and the overcurrent protection effect is achieved.
D28 is a bidirectional protection diode, when the ANT _ T voltage is too large due to accident, the power supply V can be prevented from being damaged by the too large voltage, and the processor can be prevented from being damaged by the too large voltage, so that the isolation protection effect, namely the overvoltage protection effect, can be realized.
In one embodiment of this embodiment, the power supply V is 5V, R322 is 2.7 Ω, R320 is 1k Ω, R321 is 10k Ω, C207 is 0.1 μ F, R323 is 1.5k Ω, R324 is 2k Ω, R325 is 10k Ω, R326 is 10k Ω, and R327 is 10k Ω, and the parameter values in this embodiment may have a floating variation of ± 10%. The parameters of the above components may also adopt other values according to the needs of practical application, and may be specifically set according to the needs of practical application.
Example four
As shown in fig. 4, the present embodiment provides a power protection circuit, which includes a processor, a P-channel MOS transistor Q13, an NMOS transistor M14, a PMOS transistor M15, a capacitor C207, a bidirectional protection diode D28, a resistor R320, a resistor R321, a resistor R322, a resistor R323, a resistor R324, a resistor R325, a resistor R326, and a resistor R327.
Q13The MOS transistor is a P-channel MOS transistor, wherein a pin 1 is a grid G, a pin 2 is a source S, a pin 3 is a drain D, the source S is connected with an input end, and the drain D is connected with an output end. When the voltage V between the gate G and the source SGSWhen the threshold is less than the threshold, the drain D and the source S are conducted.
M14 is an NMOS transistor with pin 1 as gate B, pin 2 as source E, and pin 3 as drain C. When V isBEIs positive, VBCWhen the voltage is negative, the NMOS tube can be conducted.
M15 is a PMOS transistor with pin 1 as gate B, pin 2 as source E, and pin 3 as drain C. When the voltage between the gate and the source is VBEIs negative and the voltage between the gate and the drain is VBCWhen the voltage is positive, the PMOS transistor M15 is turned on.
The first end of the resistor R322 is connected with pin 2 of M15, and pin 2 of M15 is connected with a power supply; the first end of R320 is connected with the second end of R322, and the second end of R320 is connected with pin 1 of M15; the first end of the R321 is connected with the second end of the R320, and the second end of the R321 is grounded; pin 2 of Q13 is connected to the second end of R322; the first ends of the pin 1 of the Q13 and the pin 3 of the R323 are respectively connected with the M15; the second end of R323 is connected with pin 3 of M14; pin 2 of M14 is grounded; the first end of the C207 and the first end of the R326 are respectively connected with a pin 3 of the Q13, and the second end of the C207 is grounded; the first end of the D28 is connected with the pin 3 of the Q13, and the second end of the D28 is grounded; the second end of R326 is connected with the first end of R327, and the second end of R327 is grounded; a second end of the R326 is connected with the processor; pin 1 of M14 connects to a first end of R324; a first end of R325 is connected to a second end of R324; the second end of R325 is grounded; a second end of R324 is coupled to the processor.
When the processor controls the ANT _ CTRL output value to be low, the gate of M14 is also low, i.e., there is no conduction voltage between pin 1 and pin 2 of M14, the PN junction is not conductive, and there is no conduction between pin 2 and pin 3 of M14. Pin 3 of M15 is no loop and is non-conductive. And further V of Q13GSThe reverse voltage difference is not conducted, so that the drain D and the source S of Q13 are also not conducted, and ANT _ T has no voltage output.
When the processor controls the ANT _ CTRL output value to be at a high level, the gate of M14 is also at a high level, that is, there is a conduction voltage between pin 1 and pin 2 of M14, the PN junction is turned on, and conduction is performed between pin 2 and pin 3 through M14. Pin 2 and pin 3 of M15 are connected, and through the R323 voltage divider circuit, pin 1 of Q13 gets a high voltage, and a voltage difference is generated between the gate and source of Q13, and the drain D and source S of Q13 are connected, and ANT _ T has a voltage output.
When the antenna connected with the load connection end ANT _ T is in short circuit, the voltage drop on the resistor R322 can be increased, the voltage value affecting an ANT _ OVERLOAD point is further reduced to be lower than a normal threshold value in a linkage mode, the ANT _ CTRL output value is immediately controlled to be changed into a low level after the processor detects that the voltage value is reduced to be lower than the normal threshold value, at the moment, Q13 is not conducted, the power output of the ANT _ T is cut off, the 5V power supply is guaranteed to be always kept in a normal range under the condition that the short circuit occurs, the influence of the ANT _ T short circuit is avoided, and the overcurrent protection effect is achieved.
D28 is a bidirectional protection diode, when the ANT _ T voltage is too large due to accident, the power supply V can be prevented from being damaged by the too large voltage, and the processor can be prevented from being damaged by the too large voltage, so that the isolation protection effect, namely the overvoltage protection effect, can be realized.
EXAMPLE five
The embodiment provides a power protection circuit, which comprises a first transistor, a first resistor, a second resistor, a third resistor, a PMOS (P-channel metal oxide semiconductor) tube and a capacitor; the second pin of the first transistor is connected with the first end of the first resistor; the first end of the second resistor is connected with the second end of the first resistor; the second end of the second resistor and the first end of the third resistor are respectively connected with the first pin of the first transistor; the second end of the third resistor is grounded; the source electrode of the PMOS tube is connected with the second end of the first resistor; the grid electrode of the PMOS tube is connected with the collector electrode of the first transistor; the drain electrode of the PMOS tube is connected with the first end of the capacitor; the second terminal of the capacitor is grounded.
In some embodiments, the power protection circuit of this embodiment further includes a bidirectional protection diode, a first end of the bidirectional protection diode is connected to the drain of the PMOS transistor, and a second end of the bidirectional protection diode is grounded.
In some embodiments, the power protection circuit of the present embodiment further includes a processor, a second transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; the first end of the fourth resistor is connected with the grid electrode of the PMOS tube; a third pin of the second transistor is connected with a second end of the fourth resistor; a second pin of the second transistor is grounded; the first end of the fifth resistor is connected with the first pin of the second transistor; the second end of the fifth resistor is respectively connected with the processor and the first end of the sixth resistor; the second end of the sixth resistor is grounded; the first end of the seventh resistor is connected with the drain electrode of the PMOS tube; the second end of the seventh resistor is connected with the first end of the eighth resistor and the processor respectively; the second end of the eighth resistor is grounded.
EXAMPLE six
The present embodiment provides an antenna device, including an antenna and the power protection circuit described in any one of the first to fifth embodiments, where the antenna is connected to a drain of a PMOS transistor. In this embodiment, the antenna serves as a load, and the power supply V supplies an operating voltage to the antenna.
It should be noted that:
the above-mentioned embodiments only express the embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims (8)

1. A power supply protection circuit is characterized by comprising a first transistor, a first resistor, a second resistor, a third resistor, a PMOS (P-channel metal oxide semiconductor) tube and a capacitor; the second pin of the first transistor is connected with the first end of the first resistor; the first end of the second resistor is connected with the second end of the first resistor; a second end of the second resistor and a first end of the third resistor are respectively connected with a first pin of the first transistor; the second end of the third resistor is grounded; the source electrode of the PMOS tube is connected with the second end of the first resistor; the grid electrode of the PMOS tube is connected with the collector electrode of the first transistor; the drain electrode of the PMOS tube is connected with the first end of the capacitor; the second end of the capacitor is grounded.
2. The power protection circuit according to claim 1, further comprising a bidirectional protection diode, wherein a first end of the bidirectional protection diode is connected to the drain of the PMOS transistor, and a second end of the bidirectional protection diode is grounded.
3. The power protection circuit according to claim 1, wherein the power protection circuit further comprises a processor, a second transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; the first end of the fourth resistor is connected with the grid electrode of the PMOS tube; a third pin of the second transistor is connected with a second end of the fourth resistor; a second pin of the second transistor is grounded; a first end of the fifth resistor is connected with a first pin of the second transistor; the second end of the fifth resistor is respectively connected with the processor and the first end of the sixth resistor; a second end of the sixth resistor is grounded; the first end of the seventh resistor is connected with the drain electrode of the PMOS tube; the second end of the seventh resistor is respectively connected with the first end of the eighth resistor and the processor; and the second end of the eighth resistor is grounded.
4. The power protection circuit according to any one of claims 1 to 3, wherein the first transistor is a PMOS transistor or a PNP type triode; the first pin of the first transistor is the grid electrode of the PMOS tube or the base electrode of the PNP type triode, the second pin of the first transistor is the source electrode of the PMOS tube or the emitting electrode of the PNP type triode, and the third pin of the first transistor is the drain electrode of the PMOS tube or the collecting electrode of the PNP type triode.
5. The power protection circuit according to any one of claim 3, wherein the second transistor is an NMOS transistor or an NPN transistor; the first pin of the second transistor is a gate of the NMOS transistor or a base of the NPN-type triode, the second pin of the second transistor is a source of the NMOS transistor or an emitter of the NPN-type triode, and the third pin of the second transistor is a drain of the NMOS transistor or a collector of the NPN-type triode.
6. The power protection circuit of any one of claim 3, wherein the processor is a single chip or an ARM chip.
7. A power protection circuit according to any one of claims 1-3, wherein the first resistance is 2.7 Ω, the second resistance is 1000 Ω, the third resistance is 10000 Ω, the capacitance is 0.1 μ F, and the power supply is 5V.
8. An antenna device comprising an antenna and the power protection circuit of any one of claims 1 to 7, wherein the antenna is connected to the drain of the PMOS transistor.
CN202111076557.XA 2021-09-14 2021-09-14 Power supply protection circuit and antenna device Pending CN113541098A (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
CN202111076557.XA CN113541098A (en) 2021-09-14 2021-09-14 Power supply protection circuit and antenna device

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201490685U (en) * 2009-07-24 2010-05-26 深圳市中兴移动通信有限公司 Multifunction power protection circuit
CN112019003A (en) * 2020-08-18 2020-12-01 重庆智行者信息科技有限公司 Load driving circuit with full diagnosis function built by discrete components

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201490685U (en) * 2009-07-24 2010-05-26 深圳市中兴移动通信有限公司 Multifunction power protection circuit
CN112019003A (en) * 2020-08-18 2020-12-01 重庆智行者信息科技有限公司 Load driving circuit with full diagnosis function built by discrete components

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Application publication date: 20211022