CN113540105B - Semiconductor device and forming method - Google Patents
Semiconductor device and forming method Download PDFInfo
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- CN113540105B CN113540105B CN202010291020.4A CN202010291020A CN113540105B CN 113540105 B CN113540105 B CN 113540105B CN 202010291020 A CN202010291020 A CN 202010291020A CN 113540105 B CN113540105 B CN 113540105B
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The embodiment of the invention provides a semiconductor device and a forming method. In the embodiment of the invention, a first groove is formed between active areas of a storage unit area by removing part of shallow groove isolation structures between first control gate structures and part of shallow groove isolation structures in areas below the first control gate structures, and then a dielectric layer with gaps is formed on the first stacked gate structures and the semiconductor substrate. Because the dielectric constants of the gap and the first groove are low, the average dielectric constants between the active areas of the memory cell areas and between the first stacked gate structures are reduced, so that the capacitance between the active areas of the memory cell areas and between the first stacked gate structures can be reduced, programming crosstalk is avoided, and the circularity of the semiconductor device is improved. Therefore, the method for forming the semiconductor device can improve the performance of the semiconductor device.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method of forming the same.
Background
With the continuous development of semiconductor manufacturing process, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a semiconductor device and a forming method thereof, so as to improve the performance of the semiconductor device.
The embodiment of the invention provides a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises active areas and shallow trench isolation structures, the active areas are arranged at intervals along a first direction, the shallow trench isolation structures are used for isolating the active areas, the semiconductor substrate comprises a storage unit area, a plurality of first stacked gate structures are formed on each active area of the storage unit area, the first stacked gate structures are arranged at intervals along a second direction, the first stacked gate structures comprise first control gate structures, the first control gate structures also extend onto the shallow trench isolation structures of the storage unit area along the first direction, and the first direction is perpendicular to the second direction; forming first grooves in part of the shallow trench isolation structures between the first control gate structures and part of the shallow trench isolation structures in the area below the first control gate structures; and forming a dielectric layer on the first control gate structure and the semiconductor substrate, and forming a gap in the dielectric layer in the process of forming the dielectric layer, wherein the gap is positioned on the active region and the shallow trench isolation structure between adjacent first control gate structures and is communicated with the first groove.
Optionally, the method further comprises: forming a first protection layer covering the side wall of the first stacked gate structure before forming the first groove; etching part of the shallow trench isolation structure between the first control gate structures and part of the shallow trench isolation structure in the area below the first control gate structures by using the first protection layer and the first stacked gate structures as masks through an isotropic etching process to form the first grooves; after the first groove is formed and before the dielectric layer is formed, the first protection layer is removed.
Optionally, the isotropic etching process etching comprises a wet etching process.
Optionally, the material of the first protective layer includes silicon nitride; the thickness of the first protective layer is 30-50 angstroms.
Optionally, the depth of the first groove is 100-5000 angstroms.
Optionally, a plasma enhanced chemical vapor deposition process is used to form the dielectric layer.
Optionally, the semiconductor substrate further includes a peripheral region, and a plurality of second stacked gate structures are formed on each active region of the peripheral region, and are arranged at intervals along a second direction, wherein the second stacked gate structures include second control gate structures, and the second control gate structures further extend onto the shallow trench isolation structures of the peripheral region along the first direction; before the dielectric layer is formed, second grooves are formed between the second stacked gate structures and the first stacked gate structures and between adjacent second stacked gate structures, and first grooves are formed between adjacent first stacked gate structures; the method for forming the semiconductor device further comprises the following steps: forming a second groove in part of the shallow trench isolation structure at the bottom of the second groove in the process of forming the first groove; the second grooves and the first grooves are separated from each other, and the second grooves on two sides of the second stacked gate structure are separated from each other; the dielectric layer is also formed on the second stacked gate structure and in a top region of the second trench.
Optionally, after forming the first groove and the second groove and before forming the dielectric layer, the method further includes: forming a second initial protection layer on the side wall of the first stacked gate structure, the side wall of the second stacked gate structure, the inner wall of the first groove and the inner wall of the second groove; forming a second initial protection layer, and then forming a sacrificial layer in the first groove and the first groove, wherein the sacrificial layer exposes the second groove and the second groove, and the top surface of the sacrificial layer is lower than the top surface of the first stacked gate structure; after the sacrificial layer is formed, forming a side wall and a filling medium layer, wherein the side wall is positioned on the side wall of the second groove, the filling medium layer is positioned in the second groove and covers the side wall of the side wall, and the top surfaces of the filling medium layer and the side wall are lower than the top surface of the second stacked gate structure; removing the second initial protection layer covering the top area of the first stacked gate structure and the top area of the second stacked gate structure in the process of forming the filling dielectric layer and the side wall, so that the second initial protection layer forms a second protection layer; after forming a filling dielectric layer, a side wall and a second protective layer, removing the sacrificial layer; after the sacrificial layer is removed and before the dielectric layer is formed, metal silicidation is carried out on the top area of the first stacked gate structure and the top area of the second stacked gate structure; the dielectric layer is also formed on the second protective layer, the side wall and the filling dielectric layer.
Optionally, the method for forming the filling dielectric layer and the side wall includes: after the sacrificial layer is formed, forming an initial side wall on the side wall of the second groove, and forming an additional side wall on the sacrificial layer in the top area of the first groove in the process of forming the initial side wall; after forming the initial side wall, forming an initial filling medium layer filling the second groove and the second groove; and etching the initial filling dielectric layer and the initial side wall back to form the side wall by the initial side wall, forming the filling dielectric layer by the initial filling dielectric layer, and etching the additional side wall and the second initial protective layer back to remove the additional side wall and form the second protective layer by the second initial protective layer in the process of etching the initial filling dielectric layer and the initial side wall back.
Optionally, the method further comprises: and before forming the initial filling dielectric layer, forming a second source drain region in the active region of the peripheral region at two sides of the second stacked gate structure by taking the initial side wall and the second stacked gate structure as masks.
Optionally, before forming the initial filling dielectric layer, the method further includes: forming a stop layer on the surface of the side wall, the top of the first stacked gate structure and the top of the second stacked gate structure and the surface of the side wall; and in the process of etching back the initial filling medium layer and the initial side wall, etching back the stop layer to remove the stop layer above the storage unit area and the stop layer at the top of the second stacked gate structure, and enabling the top surface of the stop layer covering the side wall to be lower than that of the second stacked gate structure.
Optionally, the material of the sacrificial layer is a carbon-containing organic polymer material or amorphous carbon; the material of the second protective layer includes silicon oxide.
The embodiment of the invention also provides a semiconductor device, which comprises: a semiconductor substrate including active regions arranged at intervals along a first direction and shallow trench isolation structures for isolating the active regions, the semiconductor substrate including a memory cell region; the first stacked gate structures are arranged on each active area of the memory cell area at intervals along a second direction, the first stacked gate structures comprise first control gate structures, the first control gate structures also extend onto shallow trench isolation structures of the memory cell area along the first direction, and the first direction is perpendicular to the second direction; a first groove which is positioned in part of the shallow trench isolation structures between the first control gate structures and part of the shallow trench isolation structures in the area below the first control gate structures; and the dielectric layer is positioned on the first control gate structures and the semiconductor substrate, a gap is formed in the dielectric layer, the gap is positioned on the active region and the shallow trench isolation structure between the adjacent first control gate structures, and the gap is communicated with the first groove.
Optionally, the depth of the first groove is 100-5000 angstroms.
Optionally, the semiconductor substrate further includes a peripheral region; a first groove is arranged between the adjacent first stacked gate structures; a plurality of second stacked gate structures arranged at intervals along a second direction on each active region of the peripheral region, wherein the second stacked gate structures comprise second control gate structures which also extend onto shallow trench isolation structures of the peripheral region along the first direction, and second trenches are arranged between the second stacked gate structures and the first stacked gate structures and between adjacent second stacked gate structures; the second grooves are positioned at the bottom of the second groove and are separated from the first grooves, and the second grooves at two sides of the second stacked gate structure are separated from each other; the dielectric layer is also located on the second stacked gate structure and in a top region of the second trench.
Optionally, the semiconductor device further includes: the second protection layer is positioned on part of the side wall of the first stacked gate structure and part of the side wall of the second stacked gate structure, and the top surface of the second protection layer is lower than the top surface of the first stacked gate structure and the top surface of the second stacked gate structure; the side wall covers the side wall of the second groove, and the top surface of the side wall is lower than the top surface of the second stacked gate structure; the filling medium layer is positioned in the second groove and the second groove, and the top surface of the filling medium layer is lower than the top surface of the second stacked gate structure; a first metal silicide region located in a top region of the first stacked gate structure; and the second metal silicide region is positioned at the top area of the second stacked gate structure.
Optionally, the method further comprises: the second source-drain regions are positioned in the peripheral region active regions at the two sides of the side wall and the second stacked gate structure; the filling medium layer also covers the second source drain region.
Optionally, the first control gate structure includes a first floating gate, a first control gate dielectric layer and a first control gate stacked in sequence from bottom to top; the first control gate structure is divided into a storage gate structure and a selection gate structure; in the storage grid structure, a first floating gate and a first control gate are isolated by a first control gate dielectric layer; in the selection grid structure, a first control grid penetrates through a first control grid dielectric layer and is connected with a first floating gate.
Optionally, the second stacked gate structure includes a second floating gate, a second control gate dielectric layer and a second control gate stacked in sequence from bottom to top, where the second control gate penetrates through the second control gate dielectric layer and is connected with the second floating gate.
Optionally, the material of the second protective layer includes silicon oxide; the material of the side wall comprises silicon oxide.
In the embodiment of the invention, the first grooves are formed between the active areas of the storage unit areas by removing part of the shallow groove isolation structures between the first control gate structures and part of the shallow groove isolation structures in the area below the first control gate structures, and then the dielectric layers with gaps are formed on the first stacked gate structures and the semiconductor substrate, wherein the dielectric layers are not filled in the first grooves or are very little filled. The gap is positioned on the active area and the shallow trench isolation structure between the adjacent first control gate structures and is communicated with the first groove, so that the total space of the first groove and the gap is larger. Because the dielectric constants of the gap and the first groove are low, the average dielectric constants between the active areas of the memory cell areas and between the first stacked gate structures are reduced, so that the capacitance between the active areas of the memory cell areas and between the first stacked gate structures can be reduced, programming crosstalk is avoided, and the circularity of the semiconductor device is improved. Therefore, the method for forming the semiconductor device can improve the performance of the semiconductor device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a circuit schematic of a NAND memory;
fig. 2 to 5 are photomicrographs of structures formed at respective steps of a method for forming a semiconductor device of comparative example;
fig. 6 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 7 to 23 are schematic views of structures formed at respective steps of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 24 to 25 are sectional views of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
The conventional semiconductor device includes a Flash Memory (FM). Flash memory is the most basic device in semiconductor fabrication and is widely used in various integrated circuits, so improving the performance of flash memory is of great importance to the development of integrated circuits.
Flash memories are classified into a NOR Flash Memory (NOR) and a NAND Flash Memory (NAND Flash Memory, NAND) according to the difference of structures. Nand flash memory can provide a high cell density and can achieve a high memory density as compared to nor flash memory.
However, the existing nand flash memory has poor electrical performance.
Fig. 1 is a circuit schematic of a NAND memory. As shown in fig. 1, in the NAND architecture, memory cells are organized in series every 64 memory transistors. The gate structures of the plurality of memory transistors are connected to Word Lines (WL). In each string of memory cells (32 or 64), control transistors are provided at both ends of the memory cells to be connected to Source Lines (SL) and Bit lines (Bit lines, BL). Each NAND memory cell string has a bit line for connecting with other strings.
A dielectric layer is typically filled (region a) between adjacent gate structures and voids are formed in the dielectric layer between adjacent gate structures. Because the dielectric constant of the void is lower than that of the dielectric layer material, forming the void can reduce the average dielectric constant of the material between adjacent gate structures, and can reduce the capacitance between adjacent gate structures, thereby reducing the probability of program crosstalk between adjacent gate structures.
Fig. 2 to 5 are photomicrographs of structures formed at respective steps of the method for forming a semiconductor device of the comparative example. As shown in fig. 2, in step S1, a semiconductor substrate is provided. The semiconductor substrate comprises a discrete gate structure 1. The gate structure 1 includes a floating gate 11, an interlayer insulating layer 12, and a control gate 13 stacked in this order.
As shown in fig. 3, in step S2, a first oxide layer 14 is formed overlying the gate structure 10. A first void 15 is formed in the first oxide layer 14 between the gate structures 1.
As shown in fig. 4, in step S3, the first oxide layer 14 on top of the gate structure 1 is removed to expose the top surface of the gate structure 1.
A selective etching process may be specifically employed to remove a portion of the first oxide layer 14. The top surface of the gate structure 1 is higher than the upper surface of the first oxide layer 14.
In step S4, a metal silicide is formed on the top surface of the gate structure 1.
As shown in fig. 5, in step S5, an oxide layer 17 is formed covering the metal silicide 16 and the first oxide layer 14. A second void 18 is formed in the oxide layer 17 between the metal silicides.
The semiconductor device formed by the formation method of the comparative example has the advantages that the width of the first oxide layer between the adjacent gate structures is larger, and the width of the gap is smaller, so that poor parity is easily caused, and the recyclability of the semiconductor device is affected.
In view of this, in order to improve the performance of the semiconductor device. The embodiment of the invention provides a method for forming a semiconductor device. In the embodiments of the present invention, a nand flash Memory is taken as an example for illustration, it should be understood that the forming method of the embodiments of the present invention may also be used for forming other semiconductor devices, such as Fin Field-Effect Transistor (Fin-FET) and Static Random-Access Memory (SRAM).
Fig. 6 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention. As shown in fig. 6, the method for forming a semiconductor device according to an embodiment of the present invention includes the steps of:
step S100, a semiconductor substrate is provided. The semiconductor substrate comprises active areas and shallow trench isolation structures, the active areas are arranged at intervals along a first direction, the shallow trench isolation structures are used for isolating the active areas, the semiconductor substrate comprises a storage unit area, a plurality of first stacked gate structures are formed on each active area of the storage unit area, the first stacked gate structures are arranged at intervals along a second direction, the first stacked gate structures comprise first control gate structures, the first control gate structures also extend onto the shallow trench isolation structures of the storage unit area along the first direction, and the first direction is perpendicular to the second direction;
Step 200, forming a first groove in part of the shallow trench isolation structures between the first control gate structures and part of the shallow trench isolation structures in the area below the first control gate structures;
and step S300, forming a dielectric layer on the first control gate structure and the semiconductor substrate.
Fig. 7 is a schematic perspective view of a semiconductor substrate according to an embodiment of the present invention. Fig. 8 is a cross-sectional view taken along the NN line of fig. 7. Fig. 9 is a cross-sectional view taken along line MM in fig. 7. As shown in fig. 8, the cross-section passes through the active region. As shown in fig. 9, the cross-section passes through shallow trench isolation regions. As shown in fig. 7 to 9, in step S100, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a memory CELL region CELL and a peripheral region PERI. The semiconductor substrate 100 includes Active Areas (AA) 101 arranged at intervals along a first direction and shallow trench isolation structures 102 for isolating the Active areas 101, a plurality of first stacked gate structures 103 arranged at intervals along a second direction are formed on each of the Active areas 101 of the memory CELL Area CELL, the first stacked gate structures 103 include first control gate structures which also extend onto the shallow trench isolation structures 102 of the memory CELL Area CELL along the first direction, and the first direction is perpendicular to the second direction.
Specifically, the first direction is the direction of the coordinate axis y in fig. 7, and the second direction is the direction of the coordinate axis x in fig. 7.
The semiconductor substrate 100 may include a substrate, an active device, a passive device, and the like. Further, the active device and the passive device may be a capacitor, an inductor, a resistor, various transistors, and the like.
Wherein the substrate may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the substrate may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of epitaxial layer structure on silicon, a compound substrate, or an alloy substrate. The compound substrate comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium oxide, the alloy substrate comprises SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or a combination thereof, and the SOI substrate comprises a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer, or a germanium layer) disposed on a layer of insulating material.
The material of the shallow trench isolation structure 102 may be silicon oxide (SiO 2 ) Silicon nitride (Si) 3 N 4 ) Silicon oxynitride (SiON), low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or ultra-low K dielectric material (dielectric constant less than 2.5).
A plurality of discrete first stacked gate structures 103 are formed on the semiconductor substrate 100 within the memory CELL region CELL. In this embodiment, a part of the number of first stacked gate structures 30 is a storage gate structure, and a part of the number of first stacked gate structures 103 is a select gate structure. The first stacked gate structure 103 includes a first floating gate dielectric layer (not shown), a first floating gate 103a, a first control gate dielectric layer 103b, and a first control gate 103c stacked in this order from bottom to top. In the memory gate structure, the first floating gate 103a and the first control gate 103c are isolated by the first control gate dielectric layer 103 b. In the select gate structure, the first control gate dielectric layer 103b between the first floating gate 103a and the first control gate 103c has a pattern, that is, the first control gate dielectric layer 103b cannot completely cover the first floating gate 103a, so that the first control gate 103c penetrates a portion of the first control gate dielectric layer 103b to connect with the first floating gate 103a, and an electrical connection is formed between the first floating gate 103a and the first control gate 103c.
The first floating gate dielectric layer and the first floating gate 103a constitute a first floating gate structure.
The first control gate dielectric layer 103b and the first control gate 103c constitute a first control gate structure.
A plurality of second stacked gate structures 105 are formed on each active region 101 of the peripheral region and are arranged at intervals along the second direction, the second stacked gate structures 105 include second control gate structures, the second control gate structures further extend onto the shallow trench isolation structures of the peripheral region along the first direction, and second trenches 106 are formed between the second stacked gate structures 105 and the first stacked gate structures 103 and between adjacent second stacked gate structures 105. A first trench 106a is provided between adjacent first stacked gate structures 103.
The first floating gate 103a and the first control gate 103c may be formed using polysilicon. Because the first floating gate 103a and the first control gate 103c need to be conductive, the polysilicon may be doped polysilicon. The doping element can be P-type impurities such as boron, or N-type impurities such as phosphorus. The doping mode can adopt in-situ doping of doping while depositing, and can also adopt ion implantation doping after depositing.
The first control gate dielectric layer 103b may be an oxide, nitride or stack of multiple layers of oxide. The first control gate dielectric layer 103b may be formed by one or more processes. A channel region (not shown) is formed in the active region 101 under the first stacked gate structure 103, and diffusion regions (not shown) of source and drain are formed in the active region 101 at both sides of the channel region.
The memory cell is programmed (Programming) by introducing hot electron injection from the channel region into the first floating gate 103a to establish a non-volatile negative charge on the first floating gate 103a. Specifically, a relatively high positive voltage (around 14-18V) is applied to the first control gate 103c (i.e., the corresponding word line) of the memory cell to be programmed, while a low voltage is applied to the corresponding bit line, such that a bias voltage is applied between the drain and source of the memory cell. When the drain-to-source bias accelerates electrons toward the drain. The voltage of the first control gate 103c causes the first floating gate 103a to generate an induced voltage of about 10V. This creates an electric field between the first floating gate 103a and the channel, under which electrons in the channel gain energy to tunnel into the first floating gate 103a.
Once programmed, the negative charge on the first floating gate 103a dissipates energy across the semiconductor gate and has the effect of increasing the threshold voltage of the field effect transistor (Field Effect Transistor, FET) of the features formed by the source region, drain region, channel region and control gate. During "reading" a memory cell, the programmed and unprogrammed states of the memory cell can be detected by detecting the magnitude of the current flowing between the source and drain at a predetermined first control gate 103c voltage.
Each memory transistor in the first stacked gate structure 103 within the memory CELL region CELL constitutes a memory CELL. The stacked structures are arranged in a matrix such that bit lines can be shared by memory cells in the second direction x and word lines can be shared by memory cells in the first direction y. More specifically, within the semiconductor substrate is a channel region associated with each memory cell that is located below the first stacked gate structure. The source region and the drain region are located between the channel regions. When a bias is applied to the control gate, the source and drain regions are turned on, corresponding to a bit line in the second direction x.
The peripheral region PERI includes a plurality of second stacked gate structures 105, and the second stacked gate structures 105 formed on the peripheral circuit region PERI are used to form peripheral circuits for controlling reading and writing of the memory. These peripheral circuits may include various circuit devices, such as CMOS transistors, suitable for formation on a substrate. The second stacked gate structure 105 includes a second floating gate dielectric layer (not shown), a second floating gate 105a, a patterned second control gate dielectric layer 105b, and a second control gate 105c stacked in this order from bottom to top. The second control gate dielectric layer 105b between the second floating gate 105a and the second control gate 105c of the second stacked gate structure 105 has a pattern such that an electrical connection is formed between the second floating gate 105a and the second control gate 105c. In the schematic diagram shown in fig. 7, the width of the second stacked gate structure 105 is larger than the width of the first stacked gate structure 103.
The second floating gate dielectric layer and the second floating gate 105a constitute a second floating gate structure.
The second control gate dielectric layer 105b and the second control gate 105c constitute a second control gate structure.
In an alternative implementation, the top of the first and second stacked gate structures 103, 105 also has a hard mask 108. The material of the hard mask 108 may be silicon nitride.
In other alternative implementations, an insulating layer (not shown) is formed between the first stacked gate structure 103 and the active region 101. The insulating layer is used for protecting the active region. Meanwhile, an insulating layer (not shown) is also formed between the active region 101 and the shallow trench isolation region 102.
Fig. 10 is a schematic view based on fig. 9. Fig. 11 is a schematic view based on fig. 8. As shown in fig. 10 to 11, in step S200, a first groove 109 is formed in a portion of the shallow trench isolation structure 102 between the first control gate structures and a portion of the shallow trench isolation structure 102 in a region under the first control gate structures.
Specifically, the first grooves 109 at the bottoms of the adjacent memory gate structures are penetrated to each other.
In this embodiment, during the process of forming the first groove 109, a second groove 109a is formed in a portion of the shallow trench isolation structure 102 at the bottom of the second trench 106; the second grooves 109a and the first grooves 109 are separated from each other, and the second grooves 109a on both sides of the second stacked gate structure 105 are separated from each other.
In an alternative implementation manner, the embodiment further includes: forming a first protection layer covering the sidewalls of the first stacked gate structure 103 before forming the first recess 109; etching a part of the shallow trench isolation structure between the first control gate structures and a part of the shallow trench isolation structure in the area below the first control gate structures by using the first protection layer and the first stacked gate structure 103 as masks and adopting an isotropic etching process to form the first groove 109; after the first groove 109 is formed, the first protective layer is removed.
In this embodiment, the first protection layer also covers the sidewalls of the second stacked gate structure 105.
In this embodiment, after the first recess 109 is formed, and before the dielectric layer is formed, the first protection layer is removed.
Specifically, a chemical vapor deposition process is used to form a first protection material layer that covers the sidewall and the top of the first stacked gate structure 103, and also covers the active region 101 and the shallow trench isolation structure 102 at the side of the first stacked gate structure 103, and the first protection material layer also covers the sidewall and the top of the second stacked gate structure, and the active region 101 and the shallow trench isolation structure 102 at the side of the second stacked gate structure.
Specifically, the method of forming the first protective material layer may be chemical vapor deposition, for example, low Temperature Chemical Vapor Deposition (LTCVD), plasma Chemical Vapor Deposition (PCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).
Specifically, an anisotropic etching process is adopted to etch back the first protection material layer, so as to form a final first protection layer.
The material of the first protective layer is silicon nitride. The thickness of the first protective layer is 30-50 angstroms.
The shallow trench isolation structure 102 is etched using an isotropic etching process to form a first recess 109.
Specifically, the shallow trench isolation structure 102 may be etched using a wet etching process. Further, the shallow trench isolation structures 102 may be etched using a dilute hydrofluoric acid solution (DFH) or a buffered oxide etchant (BufferedOxide Etch, BOE) as an etching solution. Specifically, the mass percentage of the dilute hydrofluoric acid solution can be 1:100-1:1000. The buffer oxide etching solution can be formed by mixing hydrofluoric acid (49%) with water or ammonium fluoride with water.
Since the isotropic etching process can etch the shallow trench isolation structure 102 from all directions and the width of the memory gate structure is small in the cross section as shown in fig. 10, a portion of the shallow trench isolation structure 102 in the area under the first control gate structure can be removed by using the isotropic etching process, thereby forming the first recess 109 between the active regions 101 of the memory region.
Optionally, the depth of the first groove 109 is 100 a to 5000 a.
Specifically, a wet etching process may be used to remove the first protective layer.
Fig. 12 is a schematic view of the base of fig. 10. Fig. 13 is a schematic view of the base of fig. 11. Referring to fig. 12 and 13, a second initial protection layer 110a is formed on the sidewalls of the first and second stacked gate structures 103 and 105, and the inner walls of the first and second grooves 109 and 109 a.
The material of the second preliminary protection layer 110a includes silicon oxide.
Fig. 14 is a schematic view of the base of fig. 12. Fig. 15 is a schematic view of the base of fig. 13. Referring to fig. 14 to 15, after the second initial protection layer is formed, a sacrificial layer 111 is formed in the first trench 106a and the first groove 109, and the sacrificial layer 111 exposes the second trench 106 and the second groove 109a, and a top surface of the sacrificial layer 111 is lower than a top surface of the first stacked gate structure 103.
A sacrificial layer 111 is formed on the semiconductor substrate 100, the sacrificial layer 111 being located between the first stacked gate structures 103, a top surface of the sacrificial layer 111 being lower than a top surface of the first stacked gate structures 103.
The sacrificial layer 111 is used for protecting the second initial protection layer 110a of the sidewall of the first stacked gate structure 103, so as to control the height of the second initial protection layer 110a, so as to control the thickness of the metal silicide layer formed in the subsequent process.
Specifically, the material of the sacrificial layer 111 is a high-temperature carbon material. Optionally, the material of the sacrificial layer 111 is ultra-thin laid carbon fiber (Automated Fiber Placement, AFP). The use of the high-temperature carbon material can facilitate the removal of the sacrificial layer 111 by ashing in a subsequent process without damaging other structures of the semiconductor device and without leaving impurity ions on the semiconductor device.
The forming of the sacrificial layer 111 specifically includes the following steps: forming a sacrificial material layer on the semiconductor substrate 100, wherein the upper surface of the sacrificial material layer is higher than the top of the first stacked gate structure 103, the sacrificial material layer covers the first stacked gate structure 103 and the second stacked gate structure 105 and fills the first trench 106a and the second trench 106, and the first groove 109 and the second groove 109a; planarizing the sacrificial material layer; thereafter, forming a photoresist layer on the sacrificial material layer in the area above the first stacked gate structure 103; the sacrificial material layer and the photoresist layer are etched to remove the sacrificial material layer in the second trench 106 and the second groove 109a and a portion of the sacrificial material layer located in the first groove 109 such that the sacrificial material layer forms the sacrificial layer 111. Specifically, the sacrificial material layer may be formed using a spin coating or a blade coating process or the like.
Specifically, the process of planarizing the sacrificial material layer is: and flattening the top surface of the sacrificial material layer by adopting a chemical mechanical polishing process.
Specifically, the process of etching the sacrificial material layer and the photoresist layer to remove the sacrificial material layer in the second trench 106 and the second groove 109a and a portion of the sacrificial material layer located in the first groove 109 includes: etching to remove the sacrificial material layer in the second groove 106 and the second groove 109a by using the photoresist layer as a mask, wherein part of the photoresist layer is consumed or the photoresist layer is consumed in the process of etching to remove the sacrificial material layer in the second groove 106 and the second groove 109 a; the etching back of the sacrificial material layer continues until part of the sacrificial material layer in the first recess 109 is removed.
After the etching is completed, the top surface of the sacrificial layer 111 is formed lower than the top surface of the control gate of the first stacked gate structure 103. Optionally, the top surface of the sacrificial layer 111 is 100-200 angstroms below the top surface of the first control gate 103c of the first stacked gate structure 103.
Referring to fig. 16-19, after the sacrificial layer 111 is formed, a sidewall 112 and a filling dielectric layer 114 are formed, the sidewall 112 is located on a sidewall of the second trench 106, the filling dielectric layer 114 is located in the second trench 106 and the second groove 109a and covers the sidewall of the sidewall 112, and top surfaces of the filling dielectric layer 114 and the sidewall 112 are lower than the top surface of the second stacked gate structure 105.
Fig. 16 is a schematic view of the base of fig. 14. Fig. 17 is a schematic view of the base of fig. 15. Fig. 18 is a schematic view of the base of fig. 16. Fig. 19 is a schematic view of the base of fig. 17. The specific steps for forming the sidewalls 112 and filling the dielectric layer 114 are described in detail below with reference to fig. 16-19.
Referring to fig. 16 and 17, an initial sidewall 112a is formed on the sidewall of the second trench 106, and an additional sidewall 112b on the sacrificial layer 111 is formed on the top region of the first trench 106a during the formation of the initial sidewall 112 a.
The material of the initial sidewall 112a and the additional sidewall 112b is silicon oxide. The initial sidewall 112a is used to protect the sidewall of the second trench 106, and to avoid the second source-drain region formed at the bottom of the second trench 106 from shorting with the second stacked gate structure 105. Functioning to isolate the second source drain region from the second stacked gate structure 105. The additional sidewall 112b serves to protect the underlying sacrificial layer 111.
Specifically, the method for forming the initial sidewall 112a and the additional sidewall 112b may use atomic layer deposition (Atomic Layer Deposition, ALD), high temperature oxidation (HighTemperature Oxidation, HTO), or low pressure tetraethoxysilane growth (LP-TEOS).
Before forming the initial filling dielectric layer, a second source drain region is formed in the active region of the peripheral region at two sides of the second stacked gate structure 105 by using the initial sidewall 112a and the second stacked gate structure 105 as masks.
Specifically, ion implantation is performed at the bottom of the second trench 106 to form a second source drain region (not shown in the figure).
Referring to fig. 16 and 17, a stop layer 113 is formed on the additional sidewall 112b, on the top of the first and second stacked gate structures 103 and 105, and on the surface of the initial sidewall 112 a.
The stop layer 113 is used to protect the first stacked gate structure 103 of the memory CELL during subsequent planarization of the protection layer. The rates at which the memory CELL region CELL and the peripheral region PERI are etched are made different.
In an alternative implementation, the material of the stop layer 113 may be silicon nitride, and the stop layer 113 may be formed by using a chemical vapor deposition process.
The method of forming the stop layer 113 may be chemical vapor deposition, for example, low Temperature Chemical Vapor Deposition (LTCVD), plasma Chemical Vapor Deposition (PCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).
Referring to fig. 16 and 17, after forming the initial sidewall 112a, an initial filling dielectric layer 114a filling the second trench 106 and the second groove 109 is formed.
Specifically, the initial filling dielectric layer 114a is used to protect the second source-drain region at the bottom of the second trench 106, and the first stacked gate structure 103 and the second stacked gate structure 105 at two sides of the second trench 106.
The material of the initial filling dielectric layer 114a is silicon dioxide or silicon dioxide doped with Boron and Phosphorus (BPSG). Specifically, the optional forming method may be a high aspect ratio chemical vapor deposition (High Aspect Ratio CVD, HARP) process, a high-concentration plasma chemical vapor deposition (HDP CVD) process, or the like, to form the dielectric material layer. And then, a planarization process is adopted to make the upper surface of the dielectric material layer substantially flush with the upper surface of the stop layer 113, so as to form the initial filling dielectric layer 114a.
Referring to fig. 18 and 19, in the process of etching back the initial filling dielectric layer 114a and the initial sidewall 112a, the stop layer 113 is etched back to remove the stop layer 113 above the memory cell region and the stop layer 113 on top of the second stacked gate structure 105, and the top surface of the stop layer 113 covering the sidewall 112 is made lower than the second stacked gate structure 105.
Specifically, the additional sidewall 112b, the first stacked gate structure 103, and the stop layer 113 on the second stacked gate structure 105 are removed.
The stop layer 113 may be etched using a dry etching process. The etch process employed etches the stop layer 113 at a greater rate than the initial fill dielectric layer 114 a.
Referring to fig. 18 and 19, the initial filling dielectric layer 114a and the initial sidewall 112a are etched back, the initial sidewall 112a is formed into a sidewall 112, the initial filling dielectric layer 114a is formed into a filling dielectric layer 114, during the process of etching back the initial filling dielectric layer 114a and the initial sidewall 112a, the additional sidewall 112b and the second initial protection layer 110a are etched back to remove the additional sidewall 112b, and the second initial protection layer 110a is formed into the second protection layer 110.
The additional sidewall 112b may be etched by a dry etching process. The etching process is used to etch the additional sidewall 112b at a rate greater than the etching rate of the filling dielectric layer 114, and at the same time, the etching rate of the additional sidewall 112b is also greater than the etching rate of the sacrificial layer 111. Further, the etching process in this step may be completed in the same process as the etching back of the stop layer 113.
Referring to fig. 18 and 19, in the process of forming the filling dielectric layer 114 and the sidewalls 112, the second initial protective layer 110a covering the top region of the first stacked gate structure 103 and the top region of the second stacked gate structure 105 is removed, such that the second initial protective layer 110a forms the second protective layer 110.
Since the fill dielectric layer 114 is etched at a relatively low rate, only the top portion of the initial sidewall 112a beneath the fill dielectric layer 114 is etched a small amount. Further, the material of the first protection layer 110 is the same as that of the additional sidewall 112b, and thus, the first protection layer 110 on both sides of the additional sidewall 112b is also etched. Further, the material of the mask layer 108 is the same as that of the additional sidewall 112b, and thus, the mask layer 108 is also etched to expose the top and top sidewalls of the first stacked gate structure 103 and to expose the top and top sidewalls of the second stacked gate structure 105. After the etching is completed, the distance from the top of the first stacked gate structure 103 to the top of the second protection layer 110 is 300 a to 400 a.
Fig. 20 is a schematic view of the fig. 18 base. Fig. 21 is a schematic view of the fig. 19 base. Referring to fig. 20 and 21, after the filling dielectric layer 114 and the sidewall 112, the second protective layer 110 are formed, the sacrificial layer 111 is removed.
Specifically, the sacrificial layer 111 is removed by ashing.
Referring to fig. 20 and 21, after the sacrificial layer 111 is removed and before the dielectric layer is formed, a metal silicide process is performed on the top region of the first stacked gate structure 103 and the top region of the second stacked gate structure 105.
Specifically, a first metal silicide region 115 is formed on a top region of the first stacked gate structure 103. A second metal silicide region 115a is formed on a top region of the second stacked gate structure 105.
The first metal silicide regions 115 may electrically connect the plurality of first stacked gate structures 103 in the first direction as word lines in the NAND structure. Meanwhile, the first metal silicide region 115 is used as a metal contact layer, so that the contact resistance between the first stacked gate structure 103 and a metal electrode formed later can be reduced.
In an alternative implementation, the metal silicidation process may be performed by means of metal atom diffusion. Performing metal atom diffusion on the first stacked gate structure 103 may include the steps of: depositing a metal layer on the first stacked gate structure 103; annealing treatment; and removing the redundant metal layer.
Specifically, the material of the metal layer may be nickel (Ni) or a nickel alloy, and specifically, the nickel alloy may be an alloy of nickel and at least one material selected from the group consisting of tantalum (Ta), zirconium (Zr), titanium (Ti), hafnium (Hf), tungsten (W), cobalt (Co), platinum (Pt), molybdenum (Mo), palladium (Pd), vanadium (V), and niobium (Nb).
The annealing process may diffuse the metal atoms to form a first metal silicide region 115 at the top region of the first stacked gate structure 103 and a second metal silicide region 115a at the top region of the second stacked gate structure 105.
Specifically, the metal layer is subjected to thermal annealing to form a metal silicide layer. In the process of annealing the metal, the annealing temperature is 600-1000 ℃. Alternatively, the annealing process may be a rapid thermal anneal (Rapid Thermal Annealing, RTA). The first control gate 103c and the second control gate 105c, which are polysilicon in metal and material, form a first metal silicide region 115 at a top region of the first stacked gate structure 103 and a second metal silicide region 115a at a top region of the second stacked gate structure 105 at a high temperature. The metal silicide may be nickel silicide (Ni 2 Si)。
In the annealing process, metal atoms of the metal layer are downwards diffused on the upper surface of the first stacked gate structure made of polysilicon, and the metal atoms and the polysilicon form a metal silicide layer at high temperature. As the metal atoms diffuse downward, the lower surface of the metal silicide layer is continually moved downward such that the lower surface of the metal silicide layer is below the top of the void.
The first protective layer 60 can function as a metal silicide blocking layer (Silicide Area Block, SAB) while forming a metal silicide on top of the first stacked gate structure, and thus, a pickling process can be used to remove the metal deposited on the first protective layer 60 after annealing.
In other alternative implementations, the first metal silicide region may be formed on top of the first stacked gate structure 103 by using an ion implantation method. Specifically, a mask is used to expose the top of the first stacked gate structure 103, and then ion implantation is performed on the first stacked gate structure 103. In addition, the first metal silicide regions 115 may also be formed using a chemical vapor deposition process.
Fig. 22 is a schematic view of the base of fig. 20. Fig. 23 is a schematic view of the base of fig. 21. Referring to fig. 22 and 23, in step S300, a dielectric layer 116 is formed on the first control gate structure 103 and the semiconductor substrate 100, a void 117 in the dielectric layer 116 is formed during the formation of the dielectric layer 116, the void 117 is located on the active region 101 and the shallow trench isolation structure 102 between adjacent first control gate structures 103, and the void 117 communicates with the first recess 109.
Specifically, the dielectric layer 116 is silicon oxide, and the dielectric layer 116 is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The dielectric layer 116 may also be formed using a low pressure tetraethoxysilane growth process (LP-TEOS).
Since the filling ability of the process of forming the dielectric layer 116 is weak and the distance between the adjacent first stacked gate structures 103 is small, it is easy to form the void 117 communicating with the bottom first groove 109 in the dielectric layer 116 between the adjacent first stacked gate structures 103.
It should be understood that the shape of the voids shown in the drawings of the present application is merely exemplary. In practice, however, the shape of the voids will vary depending on conditions such as process parameters, and generally, due to the related principles of dielectric layer formation during dielectric layer deposition, the voids will form into irregular shapes with narrow tops.
In the embodiment of the application, the first grooves are formed between the active areas of the storage unit areas by removing part of the shallow groove isolation structures between the first control gate structures and part of the shallow groove isolation structures in the area below the first control gate structures, and then the dielectric layers with gaps are formed on the first stacked gate structures and the semiconductor substrate, wherein the dielectric layers are not filled in the first grooves or are very little filled. The gap is positioned on the active area and the shallow trench isolation structure between the adjacent first control gate structures and is communicated with the first groove, so that the total space of the first groove and the gap is larger. Because the dielectric constants of the gap and the first groove are low, the average dielectric constants between the active areas of the memory cell areas and between the first stacked gate structures are reduced, so that the capacitance between the active areas of the memory cell areas and between the first stacked gate structures can be reduced, programming crosstalk is avoided, and the circularity of the semiconductor device is improved. Therefore, the method for forming the semiconductor device can improve the performance of the semiconductor device. Meanwhile, in the forming process of the embodiment of the application, the peripheral area can be protected in the forming process of the gap by forming the structures such as the sacrificial layer, the side wall, the stop layer, the protective layer and the like.
The embodiment of the invention also provides a semiconductor device. Fig. 24 is a cross-sectional view of the semiconductor device through an active region. Fig. 25 is a cross-sectional view of the semiconductor device through a shallow trench isolation structure. In an alternative implementation, as shown in fig. 24-25, the semiconductor device 100' includes:
the semiconductor substrate 100' includes memory CELL regions CELL, and active regions 101' and shallow trench isolation structures 102' spaced apart along a first direction for isolating the active regions.
A plurality of first stacked gate structures 103 'located on each active region 101' of the memory CELL and arranged at intervals along the second direction, wherein the first stacked gate structures 103 'include first control gate structures, and the first control gate structures further extend onto the shallow trench isolation structures 102' of the memory CELL along the first direction, and the first direction is perpendicular to the second direction.
A first recess (not shown in the figure, refer to 109 in fig. 10) is located in a portion of the shallow trench isolation structure 102 'between the first stacked gate structures 103' and in a portion of the shallow trench isolation structure 102 'in a region below the first stacked gate structures 103'.
A dielectric layer 116 'on the first control gate structures and the semiconductor substrate 100', the dielectric layer 116 'having voids 117' therein, the voids 117 'being located on the active region 101' and the shallow trench isolation structures 102 'between adjacent first control gate structures, and the voids 117' being in communication with the first recesses.
In an alternative implementation, the first recess has a depth of 100 angstroms to 5000 angstroms.
In an alternative implementation, the semiconductor substrate 100' further includes a peripheral region PERI; a first trench (not labeled in the figure, refer to 106a in fig. 10) is provided between adjacent first stacked gate structures 103'.
A plurality of second stacked gate structures 105 'spaced apart along the second direction on each active region of the peripheral region, the second stacked gate structures 105' including second control gate structures.
The second control gate structure further extends onto the shallow trench isolation structure 102 'of the peripheral region along the first direction, and there are second trenches between the second stacked gate structure 105' and the first stacked gate structure 103', and between adjacent second stacked gate structures 105'.
The second grooves (not shown, refer to 109a in fig. 10) in the shallow trench isolation structure 102 'are located at the bottom of the second grooves (not shown, refer to 106 in fig. 10), the second grooves and the first grooves are separated from each other, and the second grooves on both sides of the second stacked gate structure 105' are separated from each other.
The dielectric layer 116 is also located on the second stacked gate structure 105' and in the top region of the second trench.
In an alternative implementation, the semiconductor device further includes:
the second protection layer 110 'is located on a part of the sidewall of the first stacked gate structure 103' and a part of the sidewall of the second stacked gate structure 105', and the top surface of the second protection layer 110' is lower than the top surface of the first stacked gate structure 103 'and the top surface of the second stacked gate structure 105'.
And a sidewall 112' covering the sidewall of the second trench, wherein the top surface of the sidewall 112' is lower than the top surface of the second stacked gate structure 105 '.
And a filling medium layer 114' located in the second trench and the second groove, wherein the top surface of the filling medium layer 114' is lower than the top surface of the second stacked gate structure 105 '.
A first metal silicide region 115 'located at a top region of the first stacked gate structure 103'.
A second metal silicide region 115a 'located at a top region of the second stacked gate structure 105'.
In an alternative implementation, the method further includes: and second source and drain regions (not shown) in the peripheral region PERI active region 101' on both sides of the sidewall 112' and the second stacked gate structure 105 '.
The fill dielectric layer 114' also covers the second source drain regions.
In an alternative implementation manner, the first stacked gate structure includes a first floating gate 103c ', a first control gate dielectric layer 103b ', and a first control gate 103a ' stacked in order from bottom to top; the first control gate structure 103' is divided into a storage gate structure and a selection gate structure; in the memory gate structure, the first floating gate 103c ' and the first control gate 103a ' are isolated by the first control gate dielectric layer 103b '; in the select gate structure, a first control gate 103a ' is connected to a first floating gate 103c ' through a first control gate dielectric layer 103b '.
In an alternative implementation manner, the second stacked gate structure 105' includes a second floating gate 105c ', a second control gate dielectric layer 105b ', and a second control gate 105a ' stacked in sequence from bottom to top, where the second control gate 105a ' penetrates through the second control gate dielectric layer 105b ' and is connected to the second floating gate 105c '.
In an alternative implementation, the material of the second protective layer 110' includes silicon oxide; the material of the sidewall 112' includes silicon oxide.
In an alternative implementation, the semiconductor device includes an insulating layer 107'.
In the embodiment of the invention, grooves are formed between the active regions, and gaps communicated with the grooves are formed between each first stacked gate structure and each supporting structure. Because the dielectric constant of air is low, the forming method of the embodiment of the invention reduces the average dielectric constant between the active areas and between the first stacked gate structures, thereby avoiding programming crosstalk and improving the circularity of the semiconductor device. Therefore, the semiconductor device of the embodiment of the invention can improve the performance of the semiconductor device.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises an active region and a shallow trench isolation structure, the active region and the shallow trench isolation structure are arranged at intervals along a first direction, the semiconductor substrate comprises a memory cell region, a plurality of first stacked gate structures are formed on each active region of the memory cell region and are arranged at intervals along a second direction, the first stacked gate structures comprise first control gate structures, the first control gate structures also extend onto the shallow trench isolation structure of the memory cell region along the first direction, the first direction is perpendicular to the second direction, a peripheral region is formed on each active region of the peripheral region, a plurality of second stacked gate structures are formed on each active region of the peripheral region and are arranged at intervals along the second direction, second trenches are formed between the second stacked gate structures and the first stacked gate structures, and between the adjacent second stacked gate structures, and first trenches are formed between the adjacent first stacked gate structures;
Forming a first groove in a part of the shallow trench isolation structures between the first control gate structures and a part of the shallow trench isolation structures in a region below the first control gate structures;
forming a second groove in part of the shallow trench isolation structure at the bottom of the second groove in the process of forming the first groove;
forming a second initial protection layer on the side wall of the first stacked gate structure, the side wall of the second stacked gate structure, the inner wall of the first groove and the inner wall of the second groove;
removing the second initial protection layer covering the top area of the first stacked gate structure and the top area of the second stacked gate structure, so that the second initial protection layer forms a second protection layer;
and forming a dielectric layer on the first control gate structure and the semiconductor substrate, and forming a gap in the dielectric layer in the process of forming the dielectric layer, wherein the gap is positioned on the active region and the shallow trench isolation structure between adjacent first control gate structures and is communicated with the first groove.
2. The method for forming a semiconductor device according to claim 1, further comprising: forming a first protection layer covering the side wall of the first stacked gate structure before forming the first groove;
Etching part of the shallow trench isolation structure between the first control gate structures and part of the shallow trench isolation structure in the area below the first control gate structures by using the first protection layer and the first stacked gate structures as masks through an isotropic etching process to form the first grooves;
after the first groove is formed and before the dielectric layer is formed, the first protection layer is removed.
3. The method of forming a semiconductor device of claim 2, wherein the isotropic etching process etch comprises a wet etching process.
4. The method of forming a semiconductor device according to claim 2, wherein a material of the first protective layer comprises silicon nitride; the thickness of the first protective layer is 30-50 angstroms.
5. The method of forming a semiconductor device according to claim 1, wherein a depth of the first recess is 100 to 5000 angstroms.
6. The method of forming a semiconductor device of claim 1, wherein the dielectric layer is formed using a plasma enhanced chemical vapor deposition process.
7. The method of forming a semiconductor device of claim 1, wherein the second stacked gate structure comprises a second control gate structure that also extends in the first direction onto the shallow trench isolation structure of the peripheral region;
The second grooves and the first grooves are separated from each other, and the second grooves on two sides of the second stacked gate structure are separated from each other;
the dielectric layer is also formed on the second stacked gate structure and in a top region of the second trench.
8. The method for forming a semiconductor device according to claim 7, wherein,
after forming the first recess and the second recess, and before forming the dielectric layer, the method further includes:
forming a second initial protection layer, and then forming a sacrificial layer in the first groove and the first groove, wherein the sacrificial layer exposes the second groove and the second groove, and the top surface of the sacrificial layer is lower than the top surface of the first stacked gate structure;
after the sacrificial layer is formed, forming a side wall and a filling medium layer, wherein the side wall is positioned on the side wall of the second groove, the filling medium layer is positioned in the second groove and covers the side wall of the side wall, and the top surfaces of the filling medium layer and the side wall are lower than the top surface of the second stacked gate structure;
removing the second initial protection layer covering the top area of the first stacked gate structure and the top area of the second stacked gate structure in the process of forming the filling dielectric layer and the side wall, so that the second initial protection layer forms a second protection layer;
After forming a filling dielectric layer, a side wall and a second protective layer, removing the sacrificial layer;
after the sacrificial layer is removed and before the dielectric layer is formed, metal silicidation is carried out on the top area of the first stacked gate structure and the top area of the second stacked gate structure;
the dielectric layer is also formed on the second protective layer, the side wall and the filling dielectric layer.
9. The method of forming a semiconductor device according to claim 8, wherein the method of forming the filling dielectric layer and the sidewall comprises:
after the sacrificial layer is formed, forming an initial side wall on the side wall of the second groove, and forming an additional side wall on the sacrificial layer in the top area of the first groove in the process of forming the initial side wall;
after forming the initial side wall, forming an initial filling medium layer filling the second groove and the second groove;
and etching the initial filling dielectric layer and the initial side wall back to form the side wall by the initial side wall, forming the filling dielectric layer by the initial filling dielectric layer, and etching the additional side wall and the second initial protective layer back to remove the additional side wall and form the second protective layer by the second initial protective layer in the process of etching the initial filling dielectric layer and the initial side wall back.
10. The method for forming a semiconductor device according to claim 9, further comprising:
and before forming the initial filling dielectric layer, forming a second source drain region in the active region of the peripheral region at two sides of the second stacked gate structure by taking the initial side wall and the second stacked gate structure as masks.
11. The method for forming a semiconductor device according to claim 9, wherein,
before forming the initial fill dielectric layer, the method further comprises:
forming a stop layer on the surface of the side wall, the top of the first stacked gate structure and the top of the second stacked gate structure and the surface of the side wall; and in the process of etching back the initial filling medium layer and the initial side wall, etching back the stop layer to remove the stop layer above the storage unit area and the stop layer at the top of the second stacked gate structure, and enabling the top surface of the stop layer covering the side wall to be lower than that of the second stacked gate structure.
12. The method for forming a semiconductor device according to claim 8, wherein a material of the sacrificial layer is a carbon-containing organic polymer material or amorphous carbon;
the material of the second protective layer includes silicon oxide.
13. A semiconductor device, the semiconductor device comprising:
A semiconductor substrate including active regions arranged at intervals along a first direction and shallow trench isolation structures for isolating the active regions, the semiconductor substrate including a memory cell region;
the semiconductor device comprises a plurality of storage unit areas, a plurality of first stacked gate structures, a plurality of second stacked gate structures, a plurality of first control gate structures, a plurality of second control gate structures and a plurality of first control gate structures, wherein the plurality of first stacked gate structures are arranged on each active area of the storage unit areas at intervals along a second direction;
a first groove located in a part of the shallow trench isolation structures between the first control gate structures and a part of the shallow trench isolation structures in a region below the first control gate structures;
the dielectric layer is positioned on the first control gate structure and the semiconductor substrate, a gap is formed in the dielectric layer, the gap is positioned on the active area and the shallow trench isolation structure between the adjacent first control gate structures, and the gap is communicated with the first groove;
And the top surface of the second protection layer is lower than the top surfaces of the first stacked gate structure and the second stacked gate structure.
14. The semiconductor device of claim 13, wherein a depth of the first recess is 100 angstroms to 5000 angstroms.
15. The semiconductor device of claim 13, wherein adjacent first stacked gate structures have first trenches therebetween;
the second stacked gate structure comprises a second control gate structure which also extends onto the shallow trench isolation structure of the peripheral region along the first direction, and a second trench is formed between the second stacked gate structure and the first stacked gate structure and between adjacent second stacked gate structures;
the second grooves are positioned at the bottom of the second groove and are separated from the first grooves, and the second grooves at two sides of the second stacked gate structure are separated from each other;
the dielectric layer is also located on the second stacked gate structure and in a top region of the second trench.
16. The semiconductor device according to claim 15, wherein the semiconductor device further comprises:
The side wall covers the side wall of the second groove, and the top surface of the side wall is lower than the top surface of the second stacked gate structure;
the filling medium layer is positioned in the second groove and the second groove, and the top surface of the filling medium layer is lower than the top surface of the second stacked gate structure;
a first metal silicide region located in a top region of the first stacked gate structure;
and the second metal silicide region is positioned at the top area of the second stacked gate structure.
17. The semiconductor device according to claim 16, further comprising: the second source-drain regions are positioned in the peripheral region active regions at the two sides of the side wall and the second stacked gate structure;
the filling medium layer also covers the second source drain region.
18. The semiconductor device of claim 13, wherein the first control gate structure comprises a first floating gate, a first control gate dielectric layer, and a first control gate stacked in sequence from bottom to top; the first control gate structure is divided into a storage gate structure and a selection gate structure; in the storage grid structure, a first floating gate and a first control gate are isolated by a first control gate dielectric layer; in the selection grid structure, a first control grid penetrates through a first control grid dielectric layer and is connected with a first floating gate.
19. The semiconductor device of claim 15, wherein the second stacked gate structure comprises a second floating gate, a second control gate dielectric layer, and a second control gate stacked in sequence from bottom to top, the second control gate connected to the second floating gate through the second control gate dielectric layer.
20. The semiconductor device according to claim 16, wherein a material of the second protective layer comprises silicon oxide; the material of the side wall comprises silicon oxide.
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