CN113539776A - Calibration method of radio frequency power supply, semiconductor process method and equipment - Google Patents
Calibration method of radio frequency power supply, semiconductor process method and equipment Download PDFInfo
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- H—ELECTRICITY
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- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
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Abstract
The invention provides a calibration method of a radio frequency power supply, a semiconductor process method and equipment, wherein the method comprises the following steps: for a process step, acquiring a set value of a common excitation phase-locking angle of an upper radio frequency power supply and a lower radio frequency power supply in the process step; and calibrating the set value according to a preset calibration value of the common excitation phase-locking angle to determine an actual value of the common excitation phase-locking angle, wherein the calibration value is the value of the corresponding common excitation phase-locking angle when the bias value of the surface of the wafer is minimum under the preset process condition. The calibration method of the radio frequency power supply in the semiconductor process equipment, the semiconductor process method and the semiconductor process equipment can realize the consistency of process results among different process chambers.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a calibration method of a radio frequency power supply in semiconductor process equipment, the semiconductor process method and the semiconductor process equipment.
Background
The feature size of an integrated circuit is continuously reduced, the required processing technology is more and more strict, one of the important requirements is the consistency problem of an etching product, and in the process, the consistency of the process results of all process chambers of a machine table with the same model is strictly required to avoid the process risk caused by the consistency problem of each chamber, so that the consistency of the process results is realized through strict process control among different chambers.
An inductively coupled plasma etching method is a common etching method in the field of integrated circuits at present, and an existing inductively coupled plasma apparatus is shown in fig. 1, and includes a process chamber 13, an upper rf power supply 1, and a lower rf power supply 5, where a pedestal 10 (e.g., an electrostatic chuck) for carrying a wafer 9 is disposed in the process chamber 13, and the lower rf power supply 5 is electrically connected to the pedestal 10 through a lower matcher 4 for loading bias power to the pedestal 10. And, a dielectric window 8 is arranged at the top of the process chamber 13, and an upper electrode is arranged above the dielectric window 8, the upper electrode includes an outer coil 6 and an inner coil 7 of the inductive coupling coil, both of which are electrically connected with the current distribution unit 3, the upper rf power supply 1 is electrically connected with the current distribution unit 3 through the upper matcher 2, and is used for loading rf power to the outer coil 6 and the inner coil 7 through the matcher 2 and the current distribution unit 3, and rf energy is coupled into the process chamber 13 through the dielectric window 8. Furthermore, a nozzle 12 is provided on the dielectric window 8 for introducing process gas into the process chamber 13. The rf energy excites the process gas to produce a plasma 11.
In addition, the above inductively coupled plasma apparatus further includes a phase-locked cable 14 having both ends electrically connected to the upper rf power supply 1 and the lower rf power supply 5, respectively, in which case one of the upper rf power supply 1 and the lower rf power supply 5 is generally defined as a Master (Master) and the other is defined as a Slave (Slave). By adjusting the phase difference of the output waveforms of the upper rf power supply 1 and the lower rf power supply 5, i.e., the Common Excitation (CEX) phase-locked angle, the coupling phase difference between the upper electrode and the lower electrode of the process chamber 13 on the surface of the wafer 9 can be adjusted, so as to affect the ion energy and the sheath potential above the wafer 9, and further change the etching Rate and Map distribution of the wafer 9, i.e., the change of the CEX phase-locked angle can directly affect the etching Rate (ER, Etch Rate) and Map distribution.
However, even if the lengths of the phase-locked cable 14, the set CEX phase-locked angle, and the lengths of the cables between the upper rf power supply 1 and the lower rf power supply 5 and between the upper matching unit 2 and the lower matching unit 4, respectively, are the same for different process chambers, it is not possible to ensure that the coupling phase differences are the same because: under the influence of the matcher, the coil, the lower electrode and the relevant distributed parasitic parameters in the upper electrode loop and the lower electrode loop, the consistency of some phase shift factors (such as the phase shift between the input end of the upper matcher 2 and the lower part of the dielectric window 8, the phase shift between the input end of the lower matcher 4 and the upper part of the lower electrode and the like) between different process chambers cannot be ensured, so that the consistency of process results between different process chambers cannot be ensured.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, and provides a calibration method of a radio frequency power supply in semiconductor process equipment, the semiconductor process method and the semiconductor process equipment, which can realize the consistency of process results among different process chambers.
The invention provides a calibration method of a radio frequency power supply in semiconductor processing equipment for achieving the aim, the semiconductor processing equipment comprises a process chamber, an upper radio frequency power supply and a lower radio frequency power supply, wherein the process chamber is internally provided with a pedestal for bearing a wafer, the upper radio frequency power supply is used for exciting process gas in the process chamber to form plasma, and the lower radio frequency power supply is used for loading radio frequency bias voltage to the pedestal; characterized in that the calibration method comprises:
for a process step, acquiring a set value of a common excitation phase-locking angle of the upper radio frequency power supply and the lower radio frequency power supply in the process step;
calibrating the set value according to a preset calibration value of the common excitation phase-locking angle to determine an actual value of the common excitation phase-locking angle, wherein the calibration value is the value of the corresponding common excitation phase-locking angle when the bias value of the surface of the wafer is minimum under a preset process condition;
wherein the set value is calibrated according to the following formula:
if alpha + theta is less than 360 degrees, M is alpha + theta;
if the alpha + theta is more than or equal to 360 degrees, the M is alpha + theta-360 degrees;
wherein M is the actual value; alpha is the set value; theta is the calibration value.
Optionally, the calibration value is determined by:
obtaining a corresponding relation curve of the common excitation phase-locking angle and the bias voltage value of the surface of the wafer under the preset process condition;
and determining the minimum value of the bias voltage value and the value of the common excitation phase locking angle corresponding to the minimum value based on the corresponding relation curve.
Optionally, the obtaining a corresponding relationship curve between the common excitation phase-locked angle and the bias value of the wafer surface under the preset condition specifically includes:
the preset process conditions are adopted to carry out a plurality of times of test processes on the process chamber respectively, a plurality of test values of the common excitation phase-locking angle are set in sequence according to time sequence in the process of carrying out the plurality of times of test processes, and the corresponding bias voltage value of the surface of the wafer is collected and stored after each setting; when the set test value is increased by a specified difference value compared with the last set test value, the first set test value is 0 degrees, and the last set test value is 360 degrees;
and obtaining a corresponding relation curve of the common excitation phase-locking angle and the bias voltage value of the surface of the wafer according to each test value and each corresponding bias voltage value.
Optionally, the sequentially setting the test values of the plurality of common excitation phase-locked angles according to the time sequence, and acquiring and storing the corresponding bias voltage value of the wafer surface after each setting specifically includes:
sequentially setting a plurality of test values of the common excitation phase-locking angle according to time sequence;
after setting one test value each time and before setting the next test value, when the upper radio frequency power supply and the lower radio frequency power supply realize impedance matching, collecting the bias voltage value of the surface of the wafer at each preset time interval until the quantity of the collected bias voltage values reaches a preset quantity, then calculating the average value of the preset quantity of the bias voltage values, and storing the average value.
Optionally, the obtaining a corresponding relationship curve between the common excitation phase-locked angle and the bias value of the wafer surface according to each of the test values and each of the corresponding bias values specifically includes:
and fitting to obtain the corresponding relation curve according to each test value and each corresponding bias voltage value.
Optionally, in the process of performing the test process, the sequentially setting the test values of the multiple common excitation phase-locked angles according to a time sequence specifically includes:
in the process of carrying out the test process for multiple times, the phase angle of the output waveform of one of the upper radio frequency power supply and the lower radio frequency power supply is always maintained at 0 degree, and the phase angle of the output waveform of the other one of the upper radio frequency power supply and the lower radio frequency power supply is set to be a plurality of test values in time sequence.
Optionally, in the process of performing the test process, the phase angle of the output waveform of the upper radio frequency power supply is maintained at 0 °, and the phase angles of the output waveforms of the lower radio frequency power supply are sequentially set as the plurality of test values according to a chronological order.
As another technical solution, the present invention further provides a semiconductor process including at least one process step involving plasma excitation and rf bias loading, wherein the semiconductor process specifically includes:
when the process steps are started, the actual values are obtained by adopting the calibration method provided by the invention;
the process step is performed based on the actual value.
Optionally, the performing the process step based on the actual value includes:
setting a phase angle of an output waveform of one of the upper and lower RF power supplies to 0 °;
setting the phase angle of the other output waveform to the actual value.
As another technical solution, the present invention further provides a semiconductor processing apparatus, including a controller, a process chamber, an upper rf power supply and a lower rf power supply, wherein the process chamber is provided with a pedestal for carrying a wafer, the upper rf power supply is configured to excite a process gas in the process chamber to form a plasma, and the lower rf power supply is configured to apply an rf bias to the pedestal, and the controller is configured to perform a process on the wafer by using the semiconductor processing method provided by the present invention.
Optionally, the radio frequency power supply further comprises a phase-locked cable, and two ends of the phase-locked cable are electrically connected with the upper radio frequency power supply and the lower radio frequency power supply respectively.
The invention has the following beneficial effects:
the invention provides a calibration method of a radio frequency power supply in semiconductor process equipment, a semiconductor process method and a technical scheme of the semiconductor process equipment, wherein for one process step, a set value of a common excitation phase-locking angle of an upper radio frequency power supply and a lower radio frequency power supply in the process step is obtained; and calibrating the set value according to a preset calibration value of the common excitation phase-locking angle, and determining the actual value of the common excitation phase-locking angle, wherein the calibration value is the value of the corresponding common excitation phase-locking angle when the bias value of the surface of the wafer is minimum under the preset process condition. By calibrating the set value of the common excitation phase locking angle, the coupling phase difference between the upper electrode and the lower electrode of the process chamber on the surface of the wafer tends to be consistent when the set values of different process chambers are the same, so that the process result consistency between different process chambers can be improved.
Drawings
FIG. 1 is a schematic structural diagram of a conventional inductively coupled plasma apparatus;
FIG. 2 is a diagram illustrating the influence of coupling phase differences;
FIG. 3 is a block flow diagram of a method for calibrating an RF power supply in semiconductor processing equipment according to an embodiment of the present invention;
FIG. 4 is a graph showing the relationship between the coupling phase difference and the bias voltage and etching rate;
FIG. 5 is a block flow diagram of a process for determining calibration values as employed by an embodiment of the present invention;
FIG. 6A is a graph illustrating a coupling phase difference and a bias voltage when different process chambers have the same set value according to the prior art;
FIG. 6B is a graph illustrating a relationship between a coupling phase difference and a bias voltage when different process chambers have the same set value;
FIG. 7 is a block diagram of a process for obtaining a corresponding relationship between a common excitation phase-lock angle and a bias value of a wafer surface according to an embodiment of the present invention;
FIG. 8 is a block diagram of a process for obtaining bias voltage values during a test process as utilized in an embodiment of the present invention;
FIG. 9 is a plot of a fit of test values and bias values with respect to CEX phase lock angle as employed by an embodiment of the present invention;
FIG. 10 is a block flow diagram of a semiconductor processing method according to an embodiment of the present invention;
fig. 11 is a block diagram of a flow chart of obtaining an actual value in a semiconductor processing method according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the calibration method of the radio frequency power supply in the semiconductor processing equipment, the semiconductor processing method and the semiconductor processing equipment provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
The present embodiment provides a calibration method for an rf power supply in a semiconductor processing apparatus, which takes the inductively coupled plasma apparatus shown in fig. 1 as an example, and includes a process chamber 13, an upper rf power supply 1, and a lower rf power supply 5. Wherein, a pedestal 10 for bearing a wafer 9 is arranged in the process chamber 13, the upper radio frequency power supply 1 is used for exciting the process gas in the process chamber 13 to form plasma, and the lower radio frequency power supply 5 is used for loading radio frequency bias voltage to the pedestal 10.
The energy coupled into the process chamber 13 from the upper rf power source 1 includes both capacitive coupling and inductive coupling, while the energy coupled into the process chamber 13 from the lower rf power source 5 is primarily capacitively coupled energy. By adjusting the phase difference of the output waveforms of the upper radio frequency power supply 1 and the lower radio frequency power supply 5, that is, the Common Excitation (CEX) phase-locking angle, the coupling phase difference between the upper electrode (including the structures of the upper matcher 2, the isolation cavity connecting strip, the coil, and the like) and the lower electrode (including the structures of the lower matcher 4, the base 10, the capacitance to ground, the distribution resistance, and the like) of the process chamber 13 on the surface of the wafer 9 can be adjusted, and the coupling phase difference can affect the ion energy and the sheath potential above the wafer, so as to achieve the purpose of adjusting the angular distribution state of the plasma, and further change the etching Rate and Map distribution of the workpiece to be processed, that is, the CEX phase-locking angle can directly affect the etching Rate (ER, Etch Rate) and Map distribution.
In practical applications, taking the inductively coupled plasma apparatus shown in fig. 2 as an example, as shown in fig. 2, the coupling phase difference between the upper electrode and the lower electrode of the process chamber on the wafer surface is generally determined by several factors:
the factor one is as follows: the phase shift X between the input ends of the upper radio frequency power supply 1 and the upper matcher 2 is related to the cable between the two;
factor two: the phase shift Y between the lower radio frequency power supply 5 and the input end of the lower matcher 4 is related to the cable between the lower radio frequency power supply and the input end of the lower matcher;
factor three: the length of the phase-locked cable between the upper radio frequency power supply 1 and the lower radio frequency power supply 5 and the superposition phase shift Z of the CEX phase-locked angle between the upper radio frequency power supply and the lower radio frequency power supply;
factor four: the phase shift M between the input end of the upper matcher 2 and the lower surface of the dielectric window 8 is related to the structures of the upper matcher 2, the isolation cavity connecting strip, the coil and the like;
factor five: the phase shift N between the input terminal of the lower matching unit 4 and the upper surface of the base 10 is related to the structure of the lower matching unit 4, the base 10, the capacitance to ground, the distributed resistance, and the like.
For different process chambers, the coupling phase difference between the upper electrode and the lower electrode of the process chamber on the surface of the wafer can be consistent only if the superposition phase shift differences of the five influencing factors are completely the same. However, of the five factors mentioned above, only the phase shifts X, Y and Z can achieve quantitative analysis (the cable has a fixed physical length, which can be converted to a fixed phase angle), so that consistency of the phase shifts X, Y and Z between different process chambers can be achieved. However, since the phase shifts M and N involve the superposition of various hardware, the phase angle relationship thereof cannot be directly quantified, and thus the consistency of the phase shifts M and N between different process chambers cannot be ensured, and therefore, even if the phase shifts X, Y and Z are the same, the consistency of the coupling phase difference between the upper electrode and the lower electrode between different process chambers on the wafer surface cannot be ensured.
In order to solve the above problem, referring to fig. 3, the calibration method of the rf power source in the semiconductor processing equipment provided in this embodiment includes:
s101, for a process step, acquiring a set value of a common excitation phase-locking angle of an upper radio frequency power supply 1 and a lower radio frequency power supply 5 in the process step;
the set value of the common excitation phase-locked angle may be obtained by setting the phase angles of the output waveforms of the upper rf power supply 1 and the lower rf power supply 5, respectively, for example, if the set value of the first phase angle of the output waveform of the upper rf power supply 1 is 0 °, and the set value of the second phase angle of the output waveform of the lower rf power supply 5 is 5 °, the set value of the common excitation phase-locked angle is 5 °.
In practical applications, the common excitation phase lock angle can be kept constant during the execution of one process step, i.e. one process step corresponds to one set value. Or, the process step may be divided into a plurality of time periods, and each time period keeps the common excitation phase-locking angle unchanged within the process time, that is, the plurality of time periods in one process step respectively correspond to a plurality of set values, and the set values corresponding to different time periods are different, which is beneficial to adjusting the plasma distribution above the wafer, so that the plasma angular distribution of the whole process step is averaged as a whole.
S102, calibrating the set value according to a preset calibration value of the common excitation phase-locking angle to determine an actual value of the common excitation phase-locking angle.
After calibration, the process steps are performed based on the actual values.
And, the calibration value is the value of the corresponding common excitation phase-locked angle when the bias value of the wafer surface is minimum under the preset process condition. Wherein the above set value can be calibrated according to the following formula:
if alpha + theta is less than 360 degrees, M is alpha + theta;
if the alpha + theta is more than or equal to 360 degrees, the M is alpha + theta-360 degrees;
wherein M is the actual value; alpha is the above-mentioned set value; theta is the above calibration value.
FIG. 4 is a graph showing the relationship between the coupling phase difference and the bias voltage and etching rate. As shown in fig. 4, the bias voltage value VDC refers to a bias voltage value on the surface of the wafer during the semiconductor process. When the wafer surface CEX (i.e., the coupling phase difference between the upper electrode and the lower electrode of the process chamber on the wafer surface) changes, the magnitude of the bias voltage value VDC (and the etching rate ER) also changes, and as can be seen from fig. 4, when the coupling phase difference is 0 °, the corresponding bias voltage value VDC is the minimum value VDCmin, and the corresponding etching rate ER is the minimum value ERmin; when the coupling phase difference is 180 °, the corresponding bias voltage value VDC is a maximum value VDCmax, and the corresponding etching rate ER is a maximum value ERmax. When the coupling phase difference is 0 degrees, the corresponding bias value of the wafer surface is the minimum value VDCmin, and based on the minimum value VDCmin, the calibration value is set to be the value of the common excitation phase locking angle corresponding to the minimum value VDCmin, so that the coupling phase differences of different process chambers when the bias value of the wafer surface is the minimum value VDCmin can be all 0 degrees when the same preset process condition and the same set value are adopted to execute the process steps, the coupling phase differences of the different process chambers tend to be consistent, and the consistency of the process results among the different process chambers can be improved.
In some alternative embodiments, as shown in fig. 5, the above calibration value θ may be determined by:
s201, obtaining a corresponding relation curve of a common excitation phase locking angle and a bias voltage value of the surface of the wafer under a preset process condition;
s202, based on the corresponding relation curve, the minimum value of the bias voltage value and the value of the corresponding common excitation phase-locked angle are determined.
FIG. 6A is a graph illustrating a coupling phase difference and a bias voltage when different process chambers have the same set value according to the prior art; FIG. 6B is a graph illustrating the coupling phase difference and the bias voltage when the same setting is applied to different process chambers in this embodiment. As can be seen from comparing fig. 6A and 6B, when the 5 different process chambers adopt the same preset process condition and the same set value α of the CEX phase-locking angle, if the set value α is not calibrated, that is, the process steps are performed based on the set value α, as shown in fig. 6A, when the 5 different process chambers perform the process steps, the coupling phase differences (i.e., the wafer surface CEX) when the bias voltage VDC of the wafer surface is the minimum value VDCmin are respectively a1-a5, and the magnitudes are different, and the corresponding relationship curves of the 5 different process chambers also have larger deviations, thereby causing the consistency of the coupling phase differences to be poor.
If the set value α is calibrated, that is, the process step is executed based on the actual value M obtained after calibration, as shown in fig. 6B, when 5 different process chambers perform the process step, the coupling phase differences when the bias voltage value VDC of the wafer surface is the minimum value VDCmin are the same, all are 0 °, and the coincidence degree of the correspondence curves of the 5 different process chambers is obviously improved as compared with fig. 6A, so that the coupling phase differences of the different process chambers tend to be consistent, and further, the consistency of the process results between the different process chambers can be improved.
In some embodiments, optionally, as shown in fig. 7, the step S201 specifically includes:
s2011, a process chamber is subjected to multiple testing processes respectively by adopting preset process conditions;
taking the inductively coupled plasma apparatus shown in fig. 1 as an example, the flow of the testing process mainly includes: and introducing process gas into the process chamber, and starting the upper radio frequency power supply 1 and the lower radio frequency power supply 5 to realize plasma glow starting. The test process adopts the following process parameters: the process gas comprises argon (Ar) with a flow rate of 200 sccm; the radio frequency power output by the upper radio frequency power supply 1 is 300W; the bias power output by the lower radio frequency power supply 5 is 50W; the chamber pressure is 15 mT. The test process described above may not use a wafer.
Different process chambers adopt the same preset process conditions to carry out the test process, and specifically, the same process parameters are adopted.
In the step S2011, during the testing process, the testing values of the plurality of CEX lock-in angles are sequentially set in time order, and the corresponding bias voltage value of the wafer surface is collected and stored after each setting; when the set test value is increased by a specified difference value compared with the last set test value, the first set test value is 0 degrees, and the last set test value is 360 degrees.
For example, if the specified difference is 5 °, the first test value is set to 0 °, the second test value is set to 5 °, the third test value is set to 10 °, the fourth test value is set to 15 °, and so on until the last test value is set to 360 °.
In some embodiments, in order to improve the testing accuracy, optionally, the step S2011 specifically includes:
sequentially setting test values of a plurality of CEX phase locking angles according to time sequence;
after setting the test value each time and before setting the next test value, when the upper rf power supply 1 and the lower rf power supply 5 both realize impedance matching, the bias voltage values of the wafer surface are collected at every preset time interval until the number of the collected bias voltage values reaches a preset number, and then an average value of the preset number of bias voltage values is calculated and stored. Therefore, the test precision can be improved, and a more accurate bias voltage value can be obtained.
The preset number and the preset time interval can be freely set according to specific test precision requirements.
In some embodiments, optionally, the step S2011 specifically includes:
taking the inductively coupled plasma apparatus shown in fig. 1 as an example, in the process of performing the above test process, a first phase angle of an output waveform of one of the upper rf power supply 1 and the lower rf power supply 5 is always maintained at 0 °, and a second phase angle of an output waveform of the other of the upper rf power supply 1 and the lower rf power supply 5 is sequentially set to a plurality of test values in time series, and since the first phase angle is 0 °, the test values are equal to a common excitation phase-lock angle (a difference between the second phase angle and the first phase angle) of the upper rf power supply 1 and the lower rf power supply 5.
Specifically, as shown in fig. 8, at the beginning of the test process, the first phase angle of the output waveform of the upper rf power supply 1 is always maintained at 0 °, and the second phase angle of the output waveform of the lower rf power supply 5 is set to a plurality of test values in chronological order. For example, if the above-indicated difference is 5 °, the above-indicated second phase angles are set to 0 °, 5 °, 10 °, 360 ° in chronological order. After each setting of the test value of the second phase angle, the corresponding bias voltage value of the wafer surface is collected and stored.
S2012, obtaining the corresponding relation curve of the CEX phase-locked angle and the bias voltage value of the wafer surface according to each test value and each corresponding bias voltage value.
The method for obtaining the corresponding relationship curve may be various, for example, the corresponding relationship curve may be obtained by fitting each test value and each corresponding bias voltage value. For example, as shown in fig. 9, the abscissa is the calibration value θ of the CEX phase-locked angle; the ordinate is the bias voltage VDC of the wafer surface.
According to the calibration method of the radio frequency power supply in the semiconductor process equipment, provided by the embodiment of the invention, the set values of the common excitation phase locking angles are calibrated, so that the coupling phase differences between the upper electrode and the lower electrode of the process chambers on the surface of the wafer tend to be consistent when the set values of the different process chambers are the same, and the consistency of the process results among the different process chambers can be improved.
As another technical solution, the embodiment of the present invention further provides a semiconductor processing method, which includes at least one process step involving plasma excitation and rf bias loading. For example, in the inductively coupled plasma apparatus shown in FIG. 1, the upper RF power source 1 is turned on to excite the process gas in the process chamber 13 to form a plasma, and the lower RF power source 5 is turned on to apply an RF bias to the susceptor 10 during the above-mentioned process steps.
Specifically, referring to fig. 10, a semiconductor processing method according to an embodiment of the present invention includes:
s1, when the process steps begin, the actual value M is obtained by adopting the calibration method provided by the embodiment of the invention;
and S2, executing the process steps based on the actual values.
In some embodiments, optionally, the step S2 specifically includes:
setting the phase angle of the output waveform of one of the upper radio frequency power supply 1 and the lower radio frequency power supply 5 to 0 degree;
the phase angle of the output waveform of the other of the upper rf power supply 1 and the lower rf power supply 5 is set to the actual value M.
After the setting of the actual value M is completed, the process steps are started.
In some embodiments, optionally, the semiconductor processing method includes N process steps, and at the beginning of each process step, the actual value M corresponding to the current process step is obtained.
In step S1, the fixed value M is calculated by using the same set value α for each process chamber and calling up the preset calibration value θ, and using the above formula (i.e., if α + θ < 360 °, M is α + θ; and if α + θ is not less than 360 °, M is α + θ -360 °).
That is, the set value α corresponding to each process step is preset in the process recipe adopted by the semiconductor process method, and the same set value α is set in different process chambers; on the basis, when each process step is started, the respective calibration value theta is called, and the fixed value M can be calculated and obtained by using the formula, so that the set values corresponding to the process steps of different process chambers do not need to be calibrated independently, and the calibration of the set value of the CEX phase-locked angle can be automatically completed only by carrying out the calling process when each process step is started.
Specifically, as shown in fig. 11, the semiconductor process method specifically includes:
before the first process Step1 is started, the first phase angle of the output waveform of one of the upper RF power supply 1 and the lower RF power supply 5 (e.g. the upper RF power supply 1) is maintained at 0 °; setting a second phase angle (equal to the common excitation phase-locked angle α) of the output waveform of the other of the upper rf power supply 1 and the lower rf power supply 5 (e.g., the lower rf power supply 5) to 0 °;
starting the first process Step1, setting the second phase angle to M1;
wherein the second phase angle M1 satisfies the following condition:
if α 1+ θ < 360 °, M1 ═ α 1+ θ;
if the alpha 1+ theta is more than or equal to 360 degrees, the M is alpha 1+ theta-360 degrees;
the above α 1 is the set value of the common excitation phase locking angle corresponding to the first process Step 1.
After the first process Step1 is finished, the second process Step2 is started, and the second phase angle is set to M2, wherein the conditions of M2 are similar to those of M1.
And the rest is repeated until the Nth process step StepN is finished.
In summary, in the semiconductor processing method provided in this embodiment, the calibration is performed on the set value α in each process step, so that the coupling phase differences between the upper electrode and the lower electrode of the process chamber on the surface of the wafer tend to be consistent when the set values of the different process chambers are the same, and the consistency of the process results between the different process chambers can be improved.
As another technical solution, the present embodiment further provides a semiconductor processing apparatus, which takes the inductively coupled plasma apparatus shown in fig. 1 as an example, and includes a controller (not shown), a process chamber 13, an upper rf power supply 1, and a lower rf power supply 5. Wherein, a pedestal 10 for bearing a wafer 9 is arranged in the process chamber 13, the upper radio frequency power supply 1 is used for exciting the process gas in the process chamber 13 to form plasma, and the lower radio frequency power supply 5 is used for loading radio frequency bias voltage to the pedestal 10.
The controller is used for processing the wafer by adopting the semiconductor processing method provided by the embodiment of the invention.
In some embodiments, optionally, the semiconductor processing apparatus further includes a phase-locked cable 14, two ends of which are electrically connected to the upper rf power supply 1 and the lower rf power supply 5, respectively, and a coupling phase difference between the upper electrode of the process chamber 13 and the susceptor 10 on the surface of the wafer 9 can be adjusted by adjusting a phase difference of output waveforms of the upper rf power supply 1 and the lower rf power supply 5, that is, a Common Excitation (CEX) phase-locked angle, so as to affect ion energy and a sheath potential above the wafer 9, thereby changing an etching Rate and a Map distribution of the wafer 9, that is, a change in the CEX phase-locked angle can directly affect the etching Rate (ER, Etch Rate) and the Map distribution.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (11)
1. A calibration method of a radio frequency power supply in semiconductor process equipment comprises a process chamber, an upper radio frequency power supply and a lower radio frequency power supply, wherein the process chamber is internally provided with a pedestal for bearing a wafer, the upper radio frequency power supply is used for exciting process gas in the process chamber to form plasma, and the lower radio frequency power supply is used for loading radio frequency bias voltage to the pedestal; characterized in that the calibration method comprises:
for a process step, acquiring a set value of a common excitation phase-locking angle of the upper radio frequency power supply and the lower radio frequency power supply in the process step;
calibrating the set value according to a preset calibration value of the common excitation phase-locking angle to determine an actual value of the common excitation phase-locking angle, wherein the calibration value is the value of the corresponding common excitation phase-locking angle when the bias value of the surface of the wafer is minimum under a preset process condition;
wherein the set value is calibrated according to the following formula:
if alpha + theta is less than 360 degrees, M is alpha + theta;
if the alpha + theta is more than or equal to 360 degrees, the M is alpha + theta-360 degrees;
wherein M is the actual value; alpha is the set value; theta is the calibration value.
2. Calibration method according to claim 1, characterized in that the calibration value is determined by:
obtaining a corresponding relation curve of the common excitation phase-locking angle and the bias voltage value of the surface of the wafer under the preset process condition;
and determining the minimum value of the bias voltage value and the value of the common excitation phase locking angle corresponding to the minimum value based on the corresponding relation curve.
3. The calibration method as claimed in claim 2, wherein the obtaining of the corresponding relationship curve of the common excitation phase-lock angle and the bias voltage value of the wafer surface under the predetermined condition comprises:
the preset process conditions are adopted to carry out a plurality of times of test processes on the process chamber respectively, a plurality of test values of the common excitation phase-locking angle are set in sequence according to time sequence in the process of carrying out the plurality of times of test processes, and the corresponding bias voltage value of the surface of the wafer is collected and stored after each setting; when the set test value is increased by a specified difference value compared with the last set test value, the first set test value is 0 degrees, and the last set test value is 360 degrees;
and obtaining a corresponding relation curve of the common excitation phase-locking angle and the bias voltage value of the surface of the wafer according to each test value and each corresponding bias voltage value.
4. The calibration method according to claim 3, wherein the sequentially setting the test values of the plurality of common excitation phase-locked angles in time sequence and acquiring and storing the corresponding bias voltage value of the wafer surface after each setting specifically comprises:
sequentially setting a plurality of test values of the common excitation phase-locking angle according to time sequence;
after setting one test value each time and before setting the next test value, when the upper radio frequency power supply and the lower radio frequency power supply realize impedance matching, collecting the bias voltage value of the surface of the wafer at each preset time interval until the quantity of the collected bias voltage values reaches a preset quantity, then calculating the average value of the preset quantity of the bias voltage values, and storing the average value.
5. The calibration method according to claim 3, wherein the obtaining a corresponding relationship curve of the common excitation phase-locked angle and the bias voltage value of the wafer surface according to each of the test values and the corresponding bias voltage values comprises:
and fitting to obtain the corresponding relation curve according to each test value and each corresponding bias voltage value.
6. The calibration method according to claim 3, wherein the sequentially setting the test values of the plurality of common excitation phase-locked angles in chronological order during the plurality of test processes comprises:
in the process of carrying out the test process for multiple times, the phase angle of the output waveform of one of the upper radio frequency power supply and the lower radio frequency power supply is always maintained at 0 degree, and the phase angle of the output waveform of the other one of the upper radio frequency power supply and the lower radio frequency power supply is set to be a plurality of test values in time sequence.
7. The calibration method according to claim 6, wherein during the plurality of test processes, the phase angle of the output waveform of the upper RF power supply is maintained at 0 °, and the phase angle of the output waveform of the lower RF power supply is sequentially set to the plurality of test values in chronological order.
8. A semiconductor processing method, comprising at least one processing step involving plasma excitation and RF bias loading, characterized in that the semiconductor processing method specifically comprises:
-obtaining said actual value at the beginning of said process step, using the calibration method according to any one of claims 1 to 7;
the process step is performed based on the actual value.
9. The semiconductor processing method of claim 8, wherein said performing the process step based on the actual value comprises:
setting a phase angle of an output waveform of one of the upper and lower RF power supplies to 0 °;
setting the phase angle of the other output waveform to the actual value.
10. Semiconductor processing equipment comprising a controller, a process chamber, an upper rf power supply and a lower rf power supply, wherein the process chamber is provided with a pedestal for carrying a wafer, the upper rf power supply is configured to excite a process gas in the process chamber to form a plasma, and the lower rf power supply is configured to apply an rf bias to the pedestal, wherein the controller is configured to process the wafer using the semiconductor processing method of claim 8 or 9.
11. The semiconductor processing apparatus of claim 10, further comprising a phase-locked cable having two ends electrically connected to the upper rf power supply and the lower rf power supply, respectively.
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| CN105092985A (en) * | 2014-12-30 | 2015-11-25 | 北京无线电计量测试研究所 | Phase-locked amplifier based attenuation parameter measurement device |
| CN110752135A (en) * | 2019-10-31 | 2020-02-04 | 北京北方华创微电子装备有限公司 | Radio frequency bias voltage adjusting method and device and plasma etching equipment |
| CN112530773A (en) * | 2020-11-27 | 2021-03-19 | 北京北方华创微电子装备有限公司 | Semiconductor processing equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105092985A (en) * | 2014-12-30 | 2015-11-25 | 北京无线电计量测试研究所 | Phase-locked amplifier based attenuation parameter measurement device |
| CN110752135A (en) * | 2019-10-31 | 2020-02-04 | 北京北方华创微电子装备有限公司 | Radio frequency bias voltage adjusting method and device and plasma etching equipment |
| CN112530773A (en) * | 2020-11-27 | 2021-03-19 | 北京北方华创微电子装备有限公司 | Semiconductor processing equipment |
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