CN113535204A - FPGA (field programmable Gate array) online upgrading method based on Flash reconstruction technology - Google Patents
FPGA (field programmable Gate array) online upgrading method based on Flash reconstruction technology Download PDFInfo
- Publication number
- CN113535204A CN113535204A CN202110770809.2A CN202110770809A CN113535204A CN 113535204 A CN113535204 A CN 113535204A CN 202110770809 A CN202110770809 A CN 202110770809A CN 113535204 A CN113535204 A CN 113535204A
- Authority
- CN
- China
- Prior art keywords
- fpga
- program area
- flash
- area
- upper computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000001360 synchronised effect Effects 0.000 claims description 15
- 230000008859 change Effects 0.000 claims description 3
- 238000005192 partition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
Abstract
The invention discloses an FPGA (field programmable gate array) online upgrading method based on a Flash reconstruction technology. The method comprises the steps that the Flash is reconstructed and partitioned into a boot area and an update program area, the update program area comprises a first update program area and a second update program area, whether an effective boot header exists in the boot area is checked, if yes, whether at least one stored program in the first update program area and the second update program area can be normally used is further checked; after receiving an upgrading instruction of an upper computer, the FPGA executes the operation of reading the first 256 bytes of the first updating program area and the second updating program area of the Flash; and executing upgrading operation according to the reading result. The invention optimizes the storage mode of the FPGA program in Flash, and the FPGA can run a newer program before the upgrade failure under the condition of the system upgrade failure; and under the condition that the system is upgraded successfully, the Flash stores a newer program and a newest program.
Description
Technical Field
The invention relates to the technical field of Flash reconstruction technology and FPGA (field programmable gate array) online upgrading, in particular to an FPGA online upgrading method based on Flash reconstruction technology.
Background
The FPGA online upgrading means that an upper computer sends an upgrading program to the FPGA through an interface, then an FPGA internal module writes the upgrading program into a corresponding interval of the Flash, and the FPGA loads the upgrading program after the system is powered off and restarted.
The existing FPGA online upgrading technology divides a storage space of Flash into a guide area, a Golden program area and a Next program area, wherein the guide area and the Golden program area are respectively used for storing a guide head and a factory program, and data of the two storage areas are not changed after equipment leaves a factory; when the device is upgraded online each time, data stored in a Next program area of Flash is erased, and then an upgrade program is written into the Next program area. The main problem of this upgrade method is that in the case of each failure of FPGA update, the newer programs are erased, and at this time, the device can only use factory programs lacking some functions. .
Disclosure of Invention
The invention aims to provide an FPGA (field programmable gate array) online upgrading method based on a Flash reconstruction technology aiming at the defects in the prior art.
In order to achieve the aim, the invention provides an FPGA online upgrading method based on a Flash reconstruction technology, which comprises the following steps:
step 1, dividing a Flash reconstruction area into a boot area and an update program area, wherein the update program area comprises a first update program area and a second update program area, checking whether the boot area has an effective boot header, if so, further checking whether at least one stored program in the first update program area and the second update program area can be normally used, and if so, entering the next step;
step 2, the upper computer sends an upgrading instruction to the FPGA;
step 3, after receiving the upgrading instruction of the upper computer, the FPGA executes the operation of reading the front 256 bytes of the first updating program area and the second updating program area of the Flash;
and 4, executing upgrading operation according to the result of reading the first 256 bytes of the first updating program area and the second updating program area of the Flash.
Further, if a sync word is read in the first update program area or the second update program area, the step 4 includes:
step 411, the Flash driver module in the FPGA starts erasing the data of the update program area that is not read to the sync word, and does not change the data stored in the boot area and the update program area that is read to the sync word;
step 412, if the update program area which does not read the synchronous words is completely erased, the FPGA responds to the upper computer to erase the completion signal, and step 413 is executed, otherwise, step 411 is executed;
step 413, the upper computer sends an upgrade program and 4-byte check bits generated by the upper computer to the FPGA;
step 414, the FPGA writes the received upgrade program into an update program area of unread synchronous words of the Flash in real time;
step 415, the upper computer inquires whether the writing of Flash by the FPGA is finished, if so, executing step 416, otherwise, executing step 414;
step 416, the FPGA upgrading module compares the 4-byte check bits generated by the FPGA with the received 4 check bytes, if the two check bytes are equal, the step 417 is executed, otherwise, the step 418 is executed;
step 417, the FPGA sends a signal of successful upgrade to the upper computer and finishes the upgrade operation;
and 418, sending an upgrading failure signal to the upper computer by the FPGA, erasing the first 256 bytes of the upgrading program written in the Flash in the step 414, and then finishing the upgrading operation.
Further, if a sync word is read in both the first update program area and the second update program area, the step 4 includes:
step 421, a Flash drive module in the FPGA firstly erases data of a guide area, then exchanges Golden address and Next address of an original guide head, writes the guide head data after exchanging the addresses into the guide area again, and then erases data of a first updating program area or a second updating program area corresponding to the original Golden address;
step 422, if the data in the first updating program area or the second updating program area corresponding to the original Golden address is completely erased, the FPGA responds to an erasing completion signal to the upper computer, and step 423 is executed, otherwise, step 421 is executed;
step 423, the upper computer sends the upgrade program and the check bits of 4 bytes generated by the upper computer to the FPGA;
424, writing the received upgrading program into a first updating program area or a second updating program area corresponding to the original Golden address of the Flash in real time by the FPGA;
step 425, the upper computer inquires whether the writing of Flash by the FPGA is finished, if so, step 426 is executed, and if not, step 424 is executed;
step 426, the FPGA upgrade module compares the 4-byte check bits generated by the FPGA with the received 4 check bytes, if the two check bits are equal, then step 427 is executed, otherwise step 428 is executed;
427, the FPGA sends a signal of successful upgrade to the upper computer and finishes the upgrade operation;
step 428, the FPGA sends a signal of failed upgrade to the upper computer, erases the first 256 bytes of the upgrade program written in step 424, and then ends the upgrade operation.
Has the advantages that: the invention optimizes the storage mode of the FPGA program in Flash, and the method is used for carrying out FPGA on-line upgrade, so that iterative update of the FPGA program can be realized, namely under the condition of system upgrade failure, the FPGA can run a newer program before the upgrade failure; and under the condition that the system is upgraded successfully, the Flash stores a newer program and a newest program.
Drawings
FIG. 1 is a schematic structural diagram of a Flash after reconstructing partitions according to an embodiment of the present invention;
FIG. 2 is a flow chart of an FPGA online upgrading method based on a Flash reconstruction technology.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific examples, which are carried out on the premise of the technical solution of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 1 and 2, an embodiment of the present invention provides an FPGA online upgrade method based on a Flash reconfiguration technology, including:
step 1, dividing a Flash reconstruction area into a boot area and an update program area, wherein the update program area comprises a first update program area and a second update program area, checking whether the boot area has an effective boot header, if so, further checking whether at least one stored program in the first update program area and the second update program area can be normally used, and if so, entering the next step. The reconstructed partition is a physical partition, i.e. a fixed area only writes a specific program, and the original data is not lost. The boot header is a part of the program, and generally, Flash is always provided with the boot header as long as the program is available. The checking whether at least one of the stored programs in the first updating program area and the second updating program area can be normally used is to reserve a normally used program later when the upgrading operation is executed, so that the original normally used program is prevented from being erased when the updating fails.
And 2, sending an upgrading instruction to the FPGA by the upper computer.
And 3, after receiving the upgrading instruction of the upper computer, the FPGA executes the operation of reading the front 256 bytes of the first updating program area and the second updating program area of the Flash. 256 bytes is the minimum unit for each flash read. The read operation is to confirm whether or not there is a sync word in the first and second update program areas. The synchronous word is similar to a software switch, when the synchronous word exists, the subsequent program can be loaded by the FPGA power-on logic, and if the synchronous word cannot be traversed all the time, the subsequent program is not loaded by the FPGA. Similarly, if a sync word is read from a certain update program area, it indicates that the program is stored in the update program area.
And 4, executing upgrading operation according to the result of reading the first 256 bytes of the first updating program area and the second updating program area of the Flash. The result of reading the first 256 bytes of the first updating program area and the second updating program area of the Flash can be divided into two cases, and different upgrading operations are executed under different cases.
Specifically, in one case, if a sync word is read in the first updater area or the second updater area, step 4 includes:
step 411, the Flash driver module in the FPGA starts erasing the data in the update program area that is not read to the sync word, and does not change the data stored in the boot area and the update program area that is read to the sync word. Specifically, if the synchronous word is read in the first updating program area and the synchronous word is not read in the second updating program area, the Flash drive module in the FPGA starts to erase the data in the second updating program area in this step, and the data stored in the boot area and the first updating program area are not changed. Similarly, if the synchronous word is read in the second updating program area and the synchronous word is not read in the first updating program area, the Flash driving module in the FPGA in the step begins to erase the data in the first updating program area, and the data stored in the boot area and the second updating program area are not changed.
And step 412, if the updating program area which does not read the synchronous words is completely erased, the FPGA responds to the upper computer to erase the completion signal, and step 413 is executed, otherwise, step 411 is executed.
And step 413, the upper computer sends the upgrade program and 4-byte check bits generated by the upper computer to the FPGA.
And 414, writing the received upgrading program into an updating program area of the unread synchronous words of the Flash by the FPGA in real time.
Step 415, the upper computer inquires whether the writing of Flash by the FPGA is finished, if so, step 416 is executed, and if not, step 414 is executed.
And step 416, the FPGA upgrading module compares the 4-byte check bits generated by the FPGA with the received 4 check bytes, if the two check bits are equal, the step 417 is executed, otherwise, the step 418 is executed.
And 417, sending a signal of successful upgrade to the upper computer by the FPGA, and finishing the upgrade operation.
And 418, sending an upgrading failure signal to the upper computer by the FPGA, erasing the first 256 bytes of the upgrading program written in the Flash in the step 414, and then finishing the upgrading operation. The first 256 bytes of the upgrade program written in Flash in the erasing step 414 are to erase the sync word in the written program to avoid affecting the subsequent upgrade operation.
Alternatively, if a sync word is read in both the first update program area and the second update program area, step 4 comprises:
and 421, a Flash drive module in the FPGA firstly erases data in a guide area, then exchanges Golden addresses and Next addresses of original guide heads, writes the guide head data after exchanging the addresses into the guide area again, and then erases data in a first updating program area or a second updating program area corresponding to the original Golden addresses. Specifically, if the original Golden address corresponds to a first updating program area, the first updating program area is erased; and if the original Golden address corresponds to the second updating program area, erasing the second updating program area. Wherein, Golden address and Next address have the following meanings: when the FPGA is electrified, firstly loading the content of a boot header area of the flash, wherein the boot header comprises a Golden address, a Next address and other instructions; further, the FPGA loads a program with a Next address as an initial address, and if the synchronous words are traversed in the region, the FPGA loads the program in the region into the FPGA; and if the synchronous word is not traversed, the FPGA loads a program taking the Golde address as an initial address. When updating, the updated program area corresponding to the original Golden address is erased, namely, in order to erase the older program, and the newer program in the updated program area corresponding to the Next address is reserved. After the update is finished, because the Golden address and the Next address of the original leading head are exchanged during the update, the initial address of the latest program is changed into the Next address, and the initial address of the newer program in the update program area corresponding to the original Next address is changed into the Golden address, on one hand, the FPGA can load the latest program when being electrified, and on the other hand, the iterative update is convenient for the later period.
And step 422, if the data in the first updating program area or the second updating program area corresponding to the original Golden address is completely erased, the FPGA responds to an erasing completion signal to the upper computer, and step 423 is executed, otherwise, step 421 is executed.
And step 423, the upper computer sends the upgrade program and the check bits of 4 bytes generated by the upper computer to the FPGA.
And 424, writing the received upgrading program into a first updating program area or a second updating program area corresponding to the original Golden address of the Flash in real time by the FPGA.
And step 425, the upper computer inquires whether the writing of Flash by the FPGA is finished, if so, the step 426 is executed, and if not, the step 424 is executed.
And 426, comparing the 4-byte check bits generated by the FPGA with the received 4 check bytes by the FPGA upgrading module, if the two check bits are equal to each other, executing the step 427, otherwise, executing the step 428.
And 427, sending a signal of successful upgrade to the upper computer by the FPGA, and finishing the upgrade operation.
Step 428, the FPGA sends a signal of failed upgrade to the upper computer, erases the first 256 bytes of the upgrade program written in step 424, and then ends the upgrade operation. Similarly, the first 256 bytes of the upgrade program written in Flash in the erasing step 414 are to erase the sync word in the written program, so as to avoid affecting the subsequent upgrade operation.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to those of ordinary skill in the art. Without departing from the principle of the invention, several improvements and modifications can be made, and these improvements and modifications should also be construed as the scope of the invention.
Claims (3)
1. An FPGA online upgrading method based on a Flash reconstruction technology is characterized by comprising the following steps:
step 1, dividing a Flash reconstruction area into a boot area and an update program area, wherein the update program area comprises a first update program area and a second update program area, checking whether the boot area has an effective boot header, if so, further checking whether at least one stored program in the first update program area and the second update program area can be normally used, and if so, entering the next step;
step 2, the upper computer sends an upgrading instruction to the FPGA;
step 3, after receiving the upgrading instruction of the upper computer, the FPGA executes the operation of reading the front 256 bytes of the first updating program area and the second updating program area of the Flash;
and 4, executing upgrading operation according to the result of reading the first 256 bytes of the first updating program area and the second updating program area of the Flash.
2. The FPGA online upgrading method based on Flash reconstruction technology according to claim 1, wherein if a sync word is read in the first update program area or the second update program area, the step 4 comprises:
step 411, the Flash driver module in the FPGA starts erasing the data of the update program area that is not read to the sync word, and does not change the data stored in the boot area and the update program area that is read to the sync word;
step 412, if the update program area which does not read the synchronous words is completely erased, the FPGA responds to the upper computer to erase the completion signal, and step 413 is executed, otherwise, step 411 is executed;
step 413, the upper computer sends an upgrade program and 4-byte check bits generated by the upper computer to the FPGA;
step 414, the FPGA writes the received upgrade program into an update program area of unread synchronous words of the Flash in real time;
step 415, the upper computer inquires whether the writing of Flash by the FPGA is finished, if so, executing step 416, otherwise, executing step 414;
step 416, the FPGA upgrading module compares the 4-byte check bits generated by the FPGA with the received 4 check bytes, if the two check bytes are equal, the step 417 is executed, otherwise, the step 418 is executed;
step 417, the FPGA sends a signal of successful upgrade to the upper computer and finishes the upgrade operation;
and 418, sending an upgrading failure signal to the upper computer by the FPGA, erasing the first 256 bytes of the upgrading program written in the Flash in the step 414, and then finishing the upgrading operation.
3. The FPGA online upgrading method based on the Flash reconstruction technology according to claim 1, wherein if a sync word is read in both the first update program area and the second update program area, the step 4 comprises:
step 421, a Flash drive module in the FPGA firstly erases data of a guide area, then exchanges Golden address and Next address of an original guide head, writes the guide head data after exchanging the addresses into the guide area again, and then erases data of a first updating program area or a second updating program area corresponding to the original Golden address;
step 422, if the data in the first updating program area or the second updating program area corresponding to the original Golden address is completely erased, the FPGA responds to an erasing completion signal to the upper computer, and step 423 is executed, otherwise, step 421 is executed;
step 423, the upper computer sends the upgrade program and the check bits of 4 bytes generated by the upper computer to the FPGA;
424, writing the received upgrading program into a first updating program area or a second updating program area corresponding to the original Golden address of the Flash in real time by the FPGA;
step 425, the upper computer inquires whether the writing of Flash by the FPGA is finished, if so, step 426 is executed, and if not, step 424 is executed;
step 426, the FPGA upgrade module compares the 4-byte check bits generated by the FPGA with the received 4 check bytes, if the two check bits are equal, then step 427 is executed, otherwise step 428 is executed;
427, the FPGA sends a signal of successful upgrade to the upper computer and finishes the upgrade operation;
step 428, the FPGA sends a signal of failed upgrade to the upper computer, erases the first 256 bytes of the upgrade program written in step 424, and then ends the upgrade operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110770809.2A CN113535204A (en) | 2021-07-08 | 2021-07-08 | FPGA (field programmable Gate array) online upgrading method based on Flash reconstruction technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110770809.2A CN113535204A (en) | 2021-07-08 | 2021-07-08 | FPGA (field programmable Gate array) online upgrading method based on Flash reconstruction technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113535204A true CN113535204A (en) | 2021-10-22 |
Family
ID=78098034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110770809.2A Withdrawn CN113535204A (en) | 2021-07-08 | 2021-07-08 | FPGA (field programmable Gate array) online upgrading method based on Flash reconstruction technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113535204A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014029181A1 (en) * | 2012-08-21 | 2014-02-27 | 武汉电信器件有限公司 | In-application upgrade method for optical module firmware not breaking service |
| CN108108193A (en) * | 2016-11-24 | 2018-06-01 | 厦门脉视数字技术有限公司 | A kind of easy-to-use firmware upgrade method of safety and system |
| CN110231952A (en) * | 2019-06-17 | 2019-09-13 | 合肥巨一动力系统有限公司 | A kind of ECU program backup and circulation upgrade control method and device |
| CN110244971A (en) * | 2019-05-28 | 2019-09-17 | 湖北三江航天险峰电子信息有限公司 | A kind of On-line Product upgrade-system and method based on multiple load |
-
2021
- 2021-07-08 CN CN202110770809.2A patent/CN113535204A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014029181A1 (en) * | 2012-08-21 | 2014-02-27 | 武汉电信器件有限公司 | In-application upgrade method for optical module firmware not breaking service |
| CN108108193A (en) * | 2016-11-24 | 2018-06-01 | 厦门脉视数字技术有限公司 | A kind of easy-to-use firmware upgrade method of safety and system |
| CN110244971A (en) * | 2019-05-28 | 2019-09-17 | 湖北三江航天险峰电子信息有限公司 | A kind of On-line Product upgrade-system and method based on multiple load |
| CN110231952A (en) * | 2019-06-17 | 2019-09-13 | 合肥巨一动力系统有限公司 | A kind of ECU program backup and circulation upgrade control method and device |
Non-Patent Citations (1)
| Title |
|---|
| 周琼;周鹏;: "单核FPGA系统的可靠性远程升级设计", 中国新通信, no. 02, 20 January 2018 (2018-01-20) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9678761B2 (en) | Technology for selectively updating memory-resident images | |
| US8171257B2 (en) | Determining an end of valid log in a log of write records using a next pointer and a far ahead pointer | |
| WO2022007656A1 (en) | Bootloader software updating method and apparatus, embedded controller, and storage medium | |
| US20110004871A1 (en) | Embedded electronic device and firmware updating method thereof | |
| CN105808292A (en) | Firmware upgrade method of embedded terminal device | |
| CN110096300B (en) | FPGA program file backup management system, operation method and upgrading method | |
| CN106598654B (en) | Method for updating PowerPC mainboard boot chip on line | |
| CN107566169B (en) | Firmware upgrading method based on openwrt and router | |
| CN111026427B (en) | Remote online upgrading method for embedded system containing CPU and FPGA | |
| US20110252209A1 (en) | Data access method and system, storage medium controller and storage system | |
| CN111142907A (en) | Partition upgrading method for off-line keyword recognition system | |
| CN113064604A (en) | Firmware upgrading method and device | |
| CN113641390B (en) | System upgrading method, device, equipment and storage medium | |
| CN113867750A (en) | SOC processor software online upgrading method | |
| CN109947445A (en) | A kind of firmware upgrade method and system | |
| CN113835735A (en) | FPGA remote upgrading method, system and storage medium | |
| CN112346770A (en) | Embedded program online updating method | |
| CN113535204A (en) | FPGA (field programmable Gate array) online upgrading method based on Flash reconstruction technology | |
| CN115469911A (en) | Parameter configuration method, system and computer readable storage medium | |
| JPH1063497A (en) | Program updating method | |
| CN116501354B (en) | FPGA configuration file safety online upgrading method in fiber channel network node equipment | |
| CN116204353B (en) | Recovery and restoration method, device and equipment of vehicle-mounted system and storage medium | |
| CN116302019B (en) | BootLoader program self-updating method, system and storage medium | |
| US20220100496A1 (en) | Tracking history of firmware program updates | |
| CN114003265A (en) | Firmware upgrading method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20211022 |