CN113533943A - Input parameter test circuit and method for chip - Google Patents
Input parameter test circuit and method for chip Download PDFInfo
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- CN113533943A CN113533943A CN202111084023.1A CN202111084023A CN113533943A CN 113533943 A CN113533943 A CN 113533943A CN 202111084023 A CN202111084023 A CN 202111084023A CN 113533943 A CN113533943 A CN 113533943A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
Abstract
The invention relates to an input parameter test circuit for a chip, the test circuit being included in the chip and comprising a plurality of test cells connected in series, each test cell comprising: a first end connected to a packaged pin or an unpackaged pin; the second end is connected with the output of the upper-level test unit; and the control module is used for setting the test unit connected with the packaged pin to be in an activated state and setting the test unit connected with the unpackaged pin to be in a bypass state in an initialization stage. In the invention, in the initialization stage, the test unit connected with the unpackaged pin is set to be in a bypass state, so that in the subsequent test process, the test unit is excluded from a test link, and the test unit set to be in an activated state is used for testing the packaged pin. Therefore, by adding an initialization step, the structure of the test unit can be automatically adjusted according to the packaging form, so that the minimization of the test TREE is realized.
Description
Technical Field
The present invention relates to the field of integrated circuit testing technologies, and in particular, to a circuit and a method for testing input parameters of a chip.
Background
The input parameter test is used to measure the input level. Since the functional mode is prone to noise problems in the test environment, NAND Tree, a commonly used IC test technique, is often used. This technique is mainly used to test whether the connection between the pins I/O Pin of the chip and the PADs (PADs in a PCB) of the chip is problematic. The method of testing is briefly: and NAND gates (NAND gates) are introduced into all the Pin and PAD connections, one end of each NAND gate is connected with the PAD, and the other end of each NAND gate is connected with the output of the NAND gate at the upper stage, so that the NAND gates are cascaded and finally output through a Pin output. By observing the transition of the Pin, it is determined whether there is a Pin connection problem.
The NAND Tree link is design dependent and cannot be modified once fixed. Due to the different packages, some of the IOs will not be controlled by the external tester at test time in the final package format. Therefore, in the conventional design, a plurality of NAND trees need to be designed according to different packages to adapt to different packages.
Disclosure of Invention
According to an aspect of the present invention, there is provided an input parameter test circuit for a chip, the test circuit being included in the chip, including a plurality of test units connected in series, each test unit including:
a first end connected to a packaged pin or an unpackaged pin;
the second end is connected with the output of the upper-level test unit;
and the control module is used for setting the test unit connected with the packaged pin to be in an activated state and setting the test unit connected with the unpackaged pin to be in a bypass state in an initialization stage.
In the input parameter test circuit for the chip provided by the invention, the control module comprises a PMOS tube, a latch, an NAND gate and a multiplexer, in an initialization stage, a tester applies a logic low level on the packaged pin, and the PMOS tube pulls the unpackaged pin up to a logic high level; the latch locks the states of the packaged pin and the unpackaged pin, and controls the latch of the test unit connected with the packaged pin to be in an activated state and the latch of the test unit connected with the unpackaged pin to be in a bypass state through an output end.
In the input parameter test circuit for the chip provided by the invention, after initialization, the package pins are tested by using the test unit which is set to be in an activated state.
In the input parameter test circuit for the chip provided by the invention, the source electrode of the PMOS tube is connected with the first end, the gate of the PMOS tube is connected with the first output end of the latch, and the source electrode of the PMOS tube is connected with a high level; the input end of the latch is connected with the first end, and the second output end of the latch is connected with the selection end of the multiplexer; the first input end of the NAND gate is connected with the first end, the second input end of the NAND gate is connected with the second end, and the output end of the NAND gate is connected with the first input end of the multiplexer; a second input end of the multiplexer is connected with the second end; the output end of the multiplexer is the output end of the test unit.
According to another aspect of the present invention, there is also provided an input parameter testing method for a chip, the chip including a plurality of serially connected test units, each test unit including a first terminal, a second terminal, and a control module, the testing method including:
connecting a packaged pin or an unpackaged pin via the first end;
in the initialization stage, the test unit connected with the packaged pin is set to be in an activated state through the control module, and the test unit connected with the unpackaged pin is set to be in a bypass state.
In the input parameter testing method for the chip provided by the invention, in the initialization stage, the step of setting the test unit connected with the packaged pin to be in the activated state and the step of setting the test unit connected with the unpackaged pin to be in the bypass state through the control module comprises the following steps:
in an initialization stage, a tester applies a logic low level to the packaged pin, and a PMOS (P-channel metal oxide semiconductor) tube of the control module pulls the unpackaged pin up to a logic high level;
and the latch of the control module locks the states of the packaged pin and the unpackaged pin, and simultaneously controls the latch of the test unit connected with the packaged pin to be in an activated state and the latch of the test unit connected with the unpackaged pin to be in a bypass state through an output end.
The input parameter testing method for the chip provided by the invention further comprises the following steps: after initialization, the package pins are tested using the test unit set to the active state.
According to still another aspect of the present invention, there is also provided a chip including the input parameter test circuit as described above.
The input parameter test circuit has the following beneficial effects: the test circuit provided by the invention replaces the traditional single NAND logic gate by a control module comprising a NAND gate, a latch and a multiplexer. During the initialization phase, all pins on the package are pulled low by the logic low applied by the tester, while the pins without the outer package are pulled high to logic high through the PMOS on the IO. This state is latched by a latch in the control module, the latch output controlling whether the nand gate is bypassed or activated. Since the reset signal of the latch is controlled separately, the state can be maintained without being affected by other resets. After initialization, the logic is reset and testing of NANDTREE can be performed. This NANDTREE has automatically bypassed pins without an outer package in order to accommodate the NANDTREE of the current package. By adding an initialization step, the invention can automatically adjust the TREE unit according to the packaging form, thereby realizing the minimization of the test TREE.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
fig. 1 is a schematic diagram of an input parameter testing circuit for a chip according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of an input parameter testing circuit for a chip according to an embodiment of the present invention. As shown in fig. 1, the test circuit provided by the present invention includes a plurality of test units (test unit 1, test unit 2, test unit N, where N is a positive integer greater than or equal to 1), specifically, a first end and a second end of a first test unit 1 are respectively connected to a packaged Pin or an unpackaged Pin, a first end of a second test unit 2 is connected to a packaged Pin or an unpackaged Pin, a second end of the second test unit is connected to an output end of the first test unit 1, and so on, a first end of an nth test unit N is connected to a packaged Pin or an unpackaged Pin, and a second end of the nth test unit N is connected to an output end of an nth-1 test unit N-1, so that the test units are cascaded and finally output through an output Pin. By observing the transition of the Pin, it is determined whether there is a Pin connection problem.
Specifically, in one embodiment of the present invention, each test cell includes a first end 101, connected to a packaged pin or an unpackaged pin; a second terminal 102 connected to an output of the upper-level test unit; and the control module 103 is configured to, in an initialization stage, set the test unit connected to the packaged pin to an active state, and set the test unit connected to the unpackaged pin to a bypass state. In particular, when the test cell is the first test cell, the first end 101 and the second end 102 are both connected to a packaged pin or an unpackaged pin. If the test cell is set to the bypass state during the initialization phase, the test cell is excluded from the test link during subsequent testing, and the package pin is tested using the test cell set to the active state. Therefore, by adding an initialization step, the structure of the test unit can be automatically adjusted according to the packaging form, so that the minimization of the test TREE is realized.
Further, the control module 103 includes a PMOS transistor 104, a latch 105, a nand gate 106, and a multiplexer 107, wherein a source of the PMOS transistor 104 is connected to the first end 101, a gate of the PMOS transistor 104 is connected to a first output end of the latch 105, and a source of the PMOS transistor 104 is connected to a high level; the input end of the latch 105 is connected to the first end, and the second output end of the latch 105 is connected to the selection end of the multiplexer 107; a first input end of the nand gate 106 is connected to the first end, a second input end of the nand gate 106 is connected to the second end 102, and an output end of the nand gate 106 is connected to a first input end of the multiplexer 107; a second input end of the multiplexer 107 is connected to the second end 102; the output of the multiplexer 107 is the output of the test unit.
In an initialization stage, a tester applies a logic low level to the packaged pin, and the PMOS tube pulls the unpackaged pin high to a logic high level; the latch locks the states of the packaged pin and the unpackaged pin, and controls the latch of the test unit connected with the packaged pin to be in an activated state and the latch of the test unit connected with the unpackaged pin to be in a bypass state through an output end.
For example, if the pin connected to the test unit 1 is a package pin, in the initialization stage, the first end of the test unit 1 is at a low level, and the latch locks this state; the output of the latch of test unit 1 is low, and the select terminal of the multiplexer of test unit 1 is selected as the output of test unit 1 from the nand gate of test unit 1 connected to the first terminal of the multiplexer, i.e. test unit 1 is activated. If the pin connected to the test unit 2 is an unpackaged pin, in an initialization stage, the PMOS transistor of the test unit 2 pulls the first end of the test unit 2 high, and the latch locks this state; the output terminal of the latch of the test unit 2 is at a high level, and the selection terminal of the multiplexer of the test unit 2 selects the output from the test unit 1 connected to the second terminal of the multiplexer as the output of the test unit 2, i.e. the test unit 2 is bypassed.
The test circuit provided by the invention replaces the traditional single NAND logic gate by a control module comprising a NAND gate, a latch and a multiplexer. During the initialization phase, all pins on the package are pulled low by the logic low applied by the tester, while the pins without the outer package are pulled high to logic high through the PMOS on the IO. This state is latched by a latch in the control module, the latch output controlling whether the nand gate is bypassed or activated. Since the reset signal of the latch is controlled separately, the state can be maintained without being affected by other resets. After initialization, the logic is reset and testing of NANDTREE can be performed. This NANDTREE has automatically bypassed pins without an outer package in order to accommodate the NANDTREE of the current package. By adding an initialization step, the invention can automatically adjust the TREE unit according to the packaging form, thereby realizing the minimization of the test TREE.
The invention also provides an input parameter testing method which can be used for the chip, and the testing method comprises the following steps: connecting a packaged pin or an unpackaged pin via the first end; in the initialization stage, the test unit connected with the packaged pin is set to be in an activated state through the control module, and the test unit connected with the unpackaged pin is set to be in a bypass state.
Specifically, in an embodiment of the present invention, in an initialization stage, the tester applies a logic low level to the packaged pin, and the PMOS transistor of the control module pulls the unpackaged pin high to a logic high level; and the latch of the control module locks the states of the packaged pin and the unpackaged pin, and simultaneously controls the latch of the test unit connected with the packaged pin to be in an activated state and the latch of the test unit connected with the unpackaged pin to be in a bypass state through an output end.
Specifically, in an embodiment of the present invention, after initialization, a package pin is tested by using a test unit set to an active state.
Certain specific embodiments of the present invention have been described above. Note that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. For example, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Although several embodiments of the present invention have been described above with reference to the accompanying drawings, it is to be understood that the invention is not limited to the specific embodiments disclosed. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
Claims (8)
1. An input parameter test circuit for a chip, said test circuit being included in said chip, comprising a plurality of test cells connected in series, each test cell comprising:
a first end connected to a packaged pin or an unpackaged pin;
the second end is connected with the output of the upper-level test unit;
and the control module is used for setting the test unit connected with the packaged pin to be in an activated state and setting the test unit connected with the unpackaged pin to be in a bypass state in an initialization stage.
2. The input parameter test circuit for the chip of claim 1, wherein the control module comprises a PMOS transistor, a latch, a nand gate and a multiplexer, and in an initialization phase, the tester applies a logic low level to the packaged pin, and the PMOS transistor pulls the unpackaged pin high to a logic high level; the latch locks the states of the packaged pin and the unpackaged pin, and controls the latch of the test unit connected with the packaged pin to be in an activated state and the latch of the test unit connected with the unpackaged pin to be in a bypass state through an output end.
3. The input parameter test circuit for a chip according to claim 2, wherein the package pins are tested after initialization using the test unit set to an active state.
4. The input parameter test circuit for the chip according to claim 2, wherein a source of the PMOS transistor is connected to the first terminal, a gate of the PMOS transistor is connected to the first output terminal of the latch, and a source of the PMOS transistor is connected to a high level; the input end of the latch is connected with the first end, and the second output end of the latch is connected with the selection end of the multiplexer; the first input end of the NAND gate is connected with the first end, the second input end of the NAND gate is connected with the second end, and the output end of the NAND gate is connected with the first input end of the multiplexer; a second input end of the multiplexer is connected with the second end; the output end of the multiplexer is the output end of the test unit.
5. An input parameter testing method for a chip, wherein the chip comprises a plurality of serially connected test units, each test unit comprises a first terminal, a second terminal and a control module, the testing method comprises:
connecting a packaged pin or an unpackaged pin via the first end;
in the initialization stage, the test unit connected with the packaged pin is set to be in an activated state through the control module, and the test unit connected with the unpackaged pin is set to be in a bypass state.
6. The input parameter testing method for the chip according to claim 5, wherein in the initialization phase, the test unit connected to the packaged pin is set to an active state and the test unit connected to the unpackaged pin is set to a bypass state via the control module, comprising:
in an initialization stage, a tester applies a logic low level to the packaged pin, and a PMOS (P-channel metal oxide semiconductor) tube of the control module pulls the unpackaged pin up to a logic high level;
and the latch of the control module locks the states of the packaged pin and the unpackaged pin, and simultaneously controls the latch of the test unit connected with the packaged pin to be in an activated state and the latch of the test unit connected with the unpackaged pin to be in a bypass state through an output end.
7. The input parameter testing method for the chip according to claim 6, further comprising: after initialization, the package pins are tested using the test unit set to the active state.
8. A chip comprising an input parameter test circuit as claimed in any one of claims 1 to 4.
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