CN113519067A

CN113519067A - Sensor chip and distance measuring device

Info

Publication number: CN113519067A
Application number: CN202080015426.8A
Authority: CN
Inventors: 松本晃; 北野良昭; 高塚祐辅
Original assignee: Sony Semiconductor Solutions Corp
Current assignee: Sony Semiconductor Solutions Corp
Priority date: 2019-03-29
Filing date: 2020-02-21
Publication date: 2021-10-19
Also published as: JP2020167249A; WO2020202888A1; US20220181363A1

Abstract

The sensor chip of the embodiment of the present disclosure includes: a semiconductor substrate having a pixel array section in which a plurality of pixels are arranged in an array; a light receiving element that is provided in the semiconductor substrate for each pixel and includes a multiplication region in which carriers are avalanche-multiplied by a high electric field region; and a first pixel separating portion provided between the pixels, the first pixel separating portion extending from one surface of the semiconductor substrate to the other surface opposite to the one surface and having a bottom in the semiconductor substrate.

Description

Sensor chip and distance measuring device

Technical Field

The present disclosure relates to a sensor chip using, for example, an avalanche photodiode and a ranging apparatus including the sensor chip.

Background

In a ranging image sensor (ranging device) using a Single Photon Avalanche Diode (SPAD), light emission in a high electric field region of a pixel causes photons to be incident on an adjacent pixel at the time of carrier multiplication, thereby causing a signal to be accidentally detected in the adjacent pixel. To solve this problem, for example, patent document 1 discloses a sensor chip in which: in the sensor chip, an inter-pixel separation section that physically separates a pixel from another adjacent pixel is provided in a semiconductor substrate on which an avalanche photodiode element is formed.

List of cited documents

Patent document

Patent document 1: japanese unexamined patent application publication No. 2018-88488

Disclosure of Invention

Meanwhile, it is required to reduce the pixel size of a sensor chip constituting the ranging apparatus.

It is desirable to provide a sensor chip and a ranging apparatus that can reduce the pixel size.

The sensor chip of the embodiment of the present disclosure includes: a semiconductor substrate having a pixel array section in which a plurality of pixels are arranged in an array; a light receiving element provided in the semiconductor substrate for each of the pixels and having a multiplication region in which carriers are avalanche-multiplied by a high electric field region; and a first pixel separating portion disposed between the pixels, the first pixel separating portion extending from one surface of the semiconductor substrate to the opposite surface, and having a bottom in the semiconductor substrate.

The distance measuring device of the embodiment of the present disclosure includes an optical system, a sensor chip, and a signal processing circuit that calculates a distance to a measurement target object from an output signal of the sensor chip. The ranging apparatus includes the sensor chip of the above-described embodiment of the present disclosure as a sensor chip.

According to the sensor chip and the ranging apparatus of the embodiments of the present disclosure, in the pixel array section of the semiconductor substrate in which a plurality of pixels are arranged in an array form, the first pixel separation section extending from one surface to the other surface between the pixels has a bottom portion provided in the semiconductor substrate. Therefore, the semiconductor substrate is shared on the other surface side in the pixel array section

Drawings

Fig. 1 is a schematic cross-sectional view showing an example of a schematic configuration of a sensor chip according to an embodiment of the present disclosure.

Fig. 2 is a schematic plan view showing an example of the configuration of the pixel array section of the sensor chip shown in fig. 1.

Fig. 3 is a block diagram showing an example of the configuration of the sensor chip shown in fig. 1.

Fig. 4 is an example of an equivalent circuit diagram of a pixel of the sensor chip shown in fig. 1.

Fig. 5 is a schematic diagram illustrating a structure of a pixel separating portion of the sensor chip shown in fig. 1.

Fig. 6 is a schematic cross-sectional view showing an example of a schematic configuration of a sensor chip as a reference example.

Fig. 7 is a schematic cross-sectional view illustrating the effect of the sensor chip shown in fig. 1.

Fig. 8 is a schematic cross-sectional view showing an example of a schematic configuration of a sensor chip according to modification 1 of the present disclosure.

Fig. 9 is a schematic cross-sectional view showing an example of a schematic configuration of a sensor chip according to modification 1 of the present disclosure.

Fig. 10A is a schematic plan view of the sensor chip taken along the line I-I' shown in fig. 8 and 9.

Fig. 10B is a schematic plan view of the sensor chip taken along line II-II' shown in fig. 8 and 9.

Fig. 11 is a schematic cross-sectional view showing another example of the schematic configuration of the sensor chip according to modification 1 of the present disclosure.

Fig. 12 is a schematic cross-sectional view showing another example of the schematic configuration of the sensor chip according to modification 1 of the present disclosure.

Fig. 13 is a schematic cross-sectional view showing an example of a schematic configuration of a sensor chip according to modification 2 of the present disclosure.

Fig. 14 is a schematic cross-sectional view showing an example of a schematic configuration of a sensor chip according to modification 3 of the present disclosure.

Fig. 15 is a block diagram showing an example of a schematic configuration of the vehicle control system.

Fig. 16 is a diagram for assisting in explaining an example of mounting positions of the vehicle exterior information detecting unit and the imaging unit.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following embodiments. Further, the present disclosure is not limited to the arrangement, the dimensions, the dimensional ratios, and the like of the respective components shown in the drawings. Note that the description is given in the following order.

1. Embodiment (example of a sensor chip in which a p-well is shared by pixels on the light-receiving surface side)

1-1. construction of sensor chip

1-2. method for manufacturing sensor chip

1-3. operation of the sensor chip

1-4. action and Effect

2. Modification example

Modification 1 (example in which a pixel separation section is further provided on the light incidence surface side)

2-2 variation 2 (example in which wiring is connected to pixel separation section)

2-3 variation 3 (example in which semiconductor substrate and interpixel light-shielding film are electrically connected to each other in peripheral portion)

3. Application example

<1. embodiment >

Fig. 1 schematically shows an example of a cross-sectional configuration of a sensor chip (sensor chip 1) according to an embodiment of the present disclosure. Fig. 2 schematically shows an example of a planar configuration of the pixel array section R1 of the sensor chip 1 shown in fig. 1. Fig. 3 is a block diagram showing the configuration of the sensor chip 1 shown in fig. 1, and fig. 4 shows an example of an equivalent circuit of the pixel P of the sensor chip 1 shown in fig. 1. The sensor chip 1 is configured to be suitable for use in, for example, a range image sensor (distance measuring device) or an image sensor or the like that performs distance measurement by a ToF (Time-of-Flight) method.

The sensor chip 1 includes, for example, a pixel array section R1 in which a plurality of pixels P are arranged in an array form, and a peripheral section R2 provided around the pixel array section R1. The plurality of pixels P each include, for example, a light receiving element 20, a P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 26, and a CMOS inverter 27. Further, the sensor chip 1 has, for example, a structure in which the sensor substrate 10 and the logic substrate 30 are stacked on each other. The sensor substrate 10 has a laminated structure including a semiconductor substrate 11 provided with the light receiving element 20 and a wiring layer 13 provided on the front surface (surface 11S1) side of the semiconductor substrate 11. The logic substrate 30 is laminated on the wiring layer 13 (on the side of the surface 13S1 of the wiring layer 13). The sensor chip 1 of the present embodiment has a structure in which pixel separation sections 12 are provided between pixels, the pixel separation sections 12 extending from the face 11S1 of the semiconductor substrate 11 to the back face (face 11S2, light receiving face) opposite to the face 11S1, and having a bottom section 12S in the semiconductor substrate 11. The pixel separation section 12 corresponds to a specific example of the "first pixel separation section" of the present disclosure.

(1-1. construction of sensor chip)

The sensor chip 1 is, for example, a so-called back-illuminated sensor chip in which the logic substrate 30 is laminated on the front side of the sensor substrate 10 (for example, the front side (the surface 11S1) side of the semiconductor substrate 11) and receives light from the back side of the sensor substrate 10 (for example, the back side (the surface 11S2) side of the semiconductor substrate 11).

The sensor substrate 10 includes a semiconductor substrate 11 made of, for example, a silicon substrate, and a wiring layer 13. The semiconductor substrate 11 of the present embodiment includes a P-well 21 shared by a plurality of pixels P on the back surface (surface 11S2, light receiving surface). In the semiconductor substrate 11, for example, a P-type or n-type impurity concentration is controlled for each pixel P, so that the light receiving element 20 is formed for each pixel P. Further, as described above, the semiconductor substrate 11 is provided with the pixel separation portion 12 extending from the front surface (surface 11S1) of the semiconductor substrate 11 to the back surface (surface 11S2) thereof. The pixel separation section 12 has a bottom portion 12S in the semiconductor substrate 11, whereby the P-well 21 is shared by a plurality of pixels P. The wiring layer 13 is provided on the front surface (surface 11S1) side of the semiconductor substrate 11.

The light receiving element 20 includes a multiplication region (avalanche multiplication region) in which carriers are avalanche multiplied by a high electric field region. The light receiving element 20 is a SPAD element capable of forming an avalanche multiplication region when a large negative voltage is applied to the anode and avalanche-multiplying electrons generated by incidence of a single photon.

The light receiving element 20 includes, for example, an n-type semiconductor region 22, an n-type diffusion region 23, and a p-type diffusion region 24 formed in the semiconductor substrate 11. In the light receiving element 20, the avalanche multiplication region X is formed by a depletion layer formed in a region in which the n-type diffusion region 23 and the p-type diffusion region 24 are connected to each other.

The n-type semiconductor region 22 is a region in which the impurity concentration of the semiconductor substrate 11 is controlled to be n-type. The n-type semiconductor region 22 is provided in a part of the front surface (the surface 11S1) of the semiconductor substrate and its vicinity. In the n-type semiconductor region 22, an electric field for transferring electrons generated by photoelectric conversion in the light receiving element 20 to the avalanche multiplication region X is formed.

The n-type diffusion region 23 is an n-type semiconductor region (n-type semiconductor region 22) which is formed in the vicinity of the front surface (surface 11Sl) of the semiconductor substrate 11 and has an impurity concentration higher than that of the n-type semiconductor region 22 in the n-type semiconductor region 22⁺). The n-type diffusion region 23 is formed to extend over almost the entire surface of the pixel P. In addition, one of n-type diffusion regions 23The portion is in a protruding shape facing the front surface (surface 11S1) of the semiconductor substrate 11 so as to be electrically connected to the contact electrode 17 (cathode).

The p-type diffusion region 24 is a p-type semiconductor region (p) formed in the n-type semiconductor region 22 in the vicinity of the front surface (surface 11Sl) of the semiconductor substrate 11⁺) And the p-type diffusion region 24 is formed on the light receiving surface (surface 11S2) side with respect to the n-type diffusion region 23. Similar to the n-type diffusion region 23, the P-type diffusion region 24 is formed to extend over almost the entire surface of the pixel P.

The avalanche multiplication region X is a high electric field region formed in the interface between the n-type diffusion region 23 and the p-type diffusion region 24 by applying a large negative voltage to the anode (in the present embodiment, the contact electrode 17 connected to the p-well in the peripheral portion R2). In the avalanche multiplication region X, electrons (e) generated from single photons incident on the light receiving element 20^-) Is multiplied.

The pixel separation section 12 is provided between the pixels on the front surface (surface 11S1) of the semiconductor substrate 11, and serves to electrically and optically separate the adjacent pixels P from each other on the front surface (surface 11S1) side of the semiconductor substrate 11. The pixel isolation portion 12 is formed by, for example, filling an isolation groove 11H1 with a light-shielding film 12A and an insulating film 12B, the isolation groove 11H1 extending in the thickness direction (Y-axis direction) of the semiconductor substrate 11 in the p-well 21 between the pixels. In other words, the pixel separation portion 12 includes the light shielding film 12A and the insulating film 12B, and the insulating film 12B is provided to cover the surface (side surface and bottom surface) of the light shielding film 12A. The light-shielding film 12A corresponds to a specific example of "first light-shielding film" of the present disclosure.

The separation groove 11H1 is formed from the front surface (surface 11S1) toward the back surface (surface 11S2) of the semiconductor substrate 11, and the bottom thereof remains in the semiconductor substrate 11 having the p-well 21. That is, the depth (d2) of the separation groove 11H1 is less than or equal to the thickness (d1) of the semiconductor substrate 11. As a result, the P-well 21 is shared by the plurality of pixels P.

The light shielding film 12A includes a conductive material having light shielding properties. Examples of such materials include tungsten (W), silver (Ag), copper (Cu), aluminum (Al), and alloys of aluminum and copper (Cu), and the like. Note that, as shown in fig. 5, for example, a void V may be formed inside the light shielding film 12A. InsulationThe film 12B is made of, for example, silicon oxide (SiO)_x) And the like.

The semiconductor substrate 11 is also provided with n-

type semiconductor regions

25A and 25B with, for example, a p-well 21 interposed therebetween in the peripheral portion R2.

The wiring layer 13 is provided in contact with the front surface (the surface 11S1) of the semiconductor substrate 11, and the wiring layer 13 includes, for example, an interlayer insulating film 14,

wirings

15A and 15B, and

pad sections

16A and 16B. The

wirings

15A and 15B and the

pad portions

16A and 16B are used, for example, to supply voltages applied to the p-well 21 and the light receiving element 20, and to extract charges (for example, electrons) generated in the light receiving element 20. For example, the wiring 15A is electrically connected to the n-type diffusion region 23 via the contact electrode 17, and the pad portion 16A is electrically connected to the wiring 15A via the contact electrode 18. In the peripheral portion R2, the wiring 15B is electrically connected to the p-well 21 via the contact electrode 17, and the pad portion 16B is electrically connected to the wiring 15B via the contact electrode 18. It is to be noted that although fig. 1 shows an example in which a single layer of wirings (wirings 15A and 15B) is formed in the wiring layer 13, the total number of wirings in the wiring layer 13 is not limited, and wirings including two or more layers may be formed. Hereinafter, the same applies to modification 1 to modification 3 (fig. 8, 9, and 11 to 14).

The interlayer insulating film 14 is made of, for example, silicon oxide (SiO)_x) TEOS, silicon nitride (SiN)_x) And silicon oxynitride (SiO)_xN_y) Etc. or a laminated film composed of two or more of these.

The

wirings

15A and 15B are formed in the interlayer insulating film 14. The wiring 15A is formed, for example, in a range wider than the avalanche multiplication region X so as to cover the avalanche multiplication region X, and the wiring 15A also serves as a reflection plate for reflecting the light transmitted through the light receiving element 20 to the light receiving element 20. The wiring 15A corresponds to a specific example of the "light reflection section" of the present disclosure. The wiring 15B is electrically connected to the p-well 21 with the contact electrode 17 as an anode in the peripheral portion R2, for example. The

wires

15A and 15B are made of, for example, aluminum (Al), copper (Cu), tungsten (W), or the like.

The

pad portions

16A and 16B are exposed on the junction surface of the interlayer insulating film 14 and the logic substrate 30 (for example, the surface 13S1 of the wiring layer 13), and the

pad portions

16A and 16B are used for connection with the logic substrate 30, for example. The

pad portions

16A and 16B are composed of, for example, copper (Cu) pads.

The logic substrate 30 includes a wiring layer 31 and a semiconductor substrate (not shown) in which a bias voltage applying portion 51 (see fig. 3) and a P-type MOSFET 26 and a CMOS inverter 27 constituting a pixel P are formed, the wiring layer 31 being in contact with a bonding surface (for example, a surface 13S1 of the wiring layer 13) of the sensor substrate 10, and the semiconductor substrate (not shown) being opposed to the sensor substrate 10. The wiring layer 31 includes an interlayer insulating film 32, an insulating film 33,

pad portions

34A and 34B, and

pad electrodes

35A and 35B.

The wiring layer 31 includes an interlayer insulating film 32 and an insulating film 33 in this order from the sensor substrate 10 side. The interlayer insulating film 32 and the insulating film 33 are provided to be laminated with each other. Like the interlayer insulating film 14, the interlayer insulating film 32 and the insulating film 33 are composed of, for example, silicon oxide (SiO)_x) TEOS, silicon nitride (SiN)_x) And silicon oxynitride (SiO)_xN_y) Etc. or a laminated film composed of two or more of these.

The

pad portions

34A and 34B are exposed on the bonding surface of the interlayer insulating film 32 to the sensor substrate 10 (for example, the surface 31S2 of the wiring layer 31), and the

pad portions

34A and 34B are used for connection to the sensor substrate 10, for example. The

pad portions

34A and 34B are composed of, for example, copper (Cu) pads. The

pad electrodes

35A and 35B are used for connection with, for example, a semiconductor substrate of the logic substrate 30, and the

pad electrodes

35A and 35B are composed of, for example, aluminum (Al), copper (Cu), tungsten (W), or the like. The

pad portions

34A and 34B and the

pad electrodes

35A and 35B are used, for example, to supply voltages to be applied from the bias voltage applying portion 51 to the p-well 21 and the light receiving element 20, and to extract charges (for example, electrons) generated in the light receiving element 20. For example, the

pad portions

34A and 34B are electrically connected to the

pad electrodes

35A and 35B via the contact electrodes 36, respectively.

In the sensor chip 1, for example, Cu — Cu bonding is established between the

pad portions

16A and 16B and the

pad portions

34A and 34B. As a result, for example, the pad electrode 35A in the pixel array section R1 is electrically connected to the n-type diffusion region 23 via, for example, the contact electrode 36, the pad section 34A, the pad section 16A, the contact electrode 18, the wiring 15A, and the contact electrode 17. Further, the pad electrode 35B in the peripheral portion R2 is electrically connected to the p-well 21 via, for example, the contact electrode 36, the pad portion 34B, the pad portion 16B, the contact electrode 18, the wiring 15B, and the contact electrode 17.

The bias voltage applying section 51 applies a bias voltage to each of the plurality of light receiving elements 20 arranged for each pixel P in the pixel array section R1. When the voltage generated by the avalanche-multiplied electrons in the light receiving element 20 reaches a negative voltage (V)_BD) At this time, the p-type MOSFET 26 performs quenching to release avalanche-multiplied electrons in the light receiving element 20, thereby restoring the initial voltage. The CMOS inverter 27 forms a voltage generated by the avalanche-multiplied electrons in the light receiving element 20, thereby outputting a light receiving signal (apdout) generated by a pulse waveform with the arrival time of a single photon as a viewpoint.

For example, on the light receiving surface side of the sensor substrate 10 (the back surface (surface 11S2) of the semiconductor substrate 11), for example, an on-chip lens 42 is provided for each pixel P via a passivation film 41. Further, an inter-pixel light-shielding film 43 is provided between the pixels.

The passivation film 41 protects the back surface (surface 11S2) of the semiconductor substrate 11. The passivation film 41 may have an antireflection function, for example. The passivation film 41 includes a silicon nitride (SiN) film, aluminum oxide (AlO)_x) Film, silicon oxide (SiO)_x) Film, tantalum oxide (TaO)_x) Film or made of hafnium oxide (HfO)_x) Titanium oxide (TiO)_x) Or an oxide film of STO.

The on-chip lens 42 is for condensing light incident from above onto the light receiving element 20, and the on-chip lens 42 includes, for example, silicon oxide (SiO)_x) And the like. The inter-pixel light-shielding film 43 is used to suppress crosstalk of oblique incident light between adjacent pixels. The inter-pixel light-shielding film 43 is provided, for example, between adjacent pixels P in the pixel array section R1, and the inter-pixel light-shielding film 43 has, for example, a lattice shape. Similarly to the light shielding film 12A, the interpixel light shielding film 43 also includes a conductive material having light shielding properties. Specifically, the inter-pixel light shielding film 43 includes tungsten (W), silver (Ag), copper (Cu), aluminum (Al), or an alloy of aluminum and copper (Cu), or the like.

As described above, the sensor chip 1 includes the pixel array section R1 and the peripheral section R2 disposed around the pixel array section R1. In the pixel array section R1, a plurality of pixels P are arranged in an array, and each pixel P is provided with the light receiving element 20, the P-type MOSFET 26, the CMOS inverter 27, and the like described above. In the peripheral portion R2, for example, n-

type semiconductor regions

25A and 25B with the p-well 21 interposed therebetween are provided. The wiring 15B, the

pad portions

16B and 34B, and the pad electrode 35B are connected to the p-well 21 between the n-type semiconductor region 25A and the n-type semiconductor region 25B in this order via, for example, the

contact electrodes

17, 18, and 36. The pad electrode 35B is connected to, for example, Ground (GND).

(1-2. method for manufacturing sensor chip)

For example, the sensor chip 1 can be manufactured in the following manner. First, the p-type or n-type impurity concentration of the semiconductor substrate 11 is controlled by ion implantation, thereby forming the p-well 21, the n-type semiconductor region 22, the n-type diffusion region 23, and the p-type diffusion region 24. Subsequently, for example, with a material such as SiO_xThe front surface (surface 11S1) of the semiconductor substrate 11 is patterned using the oxide film or the nitride film as a hard mask, and then the separation grooves 11H1 are formed from the front surface (surface 11S1) side by etching. Subsequently, the insulating film 12B and the light-shielding film 12A are sequentially formed on the side surfaces and the bottom surface of the separation groove 11H1 by, for example, a CVD (Chemical Vapor Deposition) method, a PVD (Physical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, a Vapor Deposition method, or the like. Next, the light-shielding film 12A and the insulating film 12B on the front surface (surface 11S1) of the semiconductor substrate 11 are removed by, for example, CMP (Chemical Mechanical Polishing) with the hard mask as a barrier layer, and then the wiring layer 13 is formed on the front surface (surface 11S1) of the semiconductor substrate 11. Thereafter, the logic substrate 30 formed separately is bonded to the wiring layer 13. At this time, the

pad portions

16A and 16B exposed on the bonding surface 14S1 of the wiring layer 13 and the

pad portions

34A and 34B exposed on the bonding surface 32S1 of the wiring layer 31 on the logic substrate 30 side are bonded to each other by Cu — Cu bonding. Subsequently, the back surface (surface 11S2) of the semiconductor substrate 11 is polished by, for example, CMP, followed by sequentially forming the passivation film 41, the inter-pixel light-shielding film 43, and the on-chip lens 42. Thereby completing the sensing shown in FIG. 1And a device chip 1.

(1-3. operation of sensor chip)

In the light receiving element 20, when a large negative voltage (V) is applied_BD) When applied to the anode (the contact electrode 17 connected to the p-well in the peripheral portion R2), the depletion layer spreads from the pn junction between the n-type diffusion region 23 and the p-type diffusion region 24 connected thereto, thereby forming the avalanche multiplication region X. In the avalanche multiplication region X, electrons generated by incidence of a single photon can be avalanche multiplied. The avalanche-multiplied electrons are extracted as signal charges, and signal processing is performed by a signal processing circuit.

The sensor chip 1 may be used as a ranging sensor by the ToF method. In the ToF method, a signal delay time between a signal generated by a signal charge and a reference signal is converted into a distance to a measurement target object. The signal processing circuit calculates a signal delay time from, for example, a signal generated from the signal charge obtained from each pixel P and a reference signal. The obtained signal delay time is converted into a distance. Thereby measuring the distance to the measurement target object.

(1-4. action and Effect)

In the sensor chip 1 of the present embodiment, between the pixels in the pixel array section R1 in which a plurality of pixels P are arranged in an array, the pixel separation section 12 that extends from the front surface (the surface 11S1) to the back surface (the surface 11S2) in the semiconductor substrate 11 and has the bottom 12S in the semiconductor substrate 11 is provided, whereby the P-well 21 formed in the semiconductor substrate 11 is shared by a plurality of pixels. Therefore, it is not necessary to provide an anode for each pixel P, and a plurality of pixels can share the anode. As will be explained below.

Fig. 6 schematically shows a cross-sectional configuration of a general sensor chip 100 as a reference example. As described above, in a general sensor chip including an avalanche photodiode element for each pixel P, an inter-pixel separation portion physically separating the pixel from another adjacent pixel is provided in order to prevent color mixing due to hot carrier light emission between the adjacent pixels. Like the pixel separation portion 1200 shown in fig. 6, the pixel separation portion penetrates the semiconductor substrate 1100, and the semiconductor substrate 1100 is divided in units of pixels P. Therefore, in the sensor chip 100, the anode 2419, a wiring connected to the anode 2419, and the like need to be provided for each pixel P.

In the sensor chip having the above-described configuration, it is necessary to secure a region where an anode is to be formed in the pixel P, and thus it is difficult to reduce the pixel size.

In contrast, in the present embodiment, the bottom portion 12S of the pixel separation portion 12 is provided in the semiconductor substrate 11, and the P-well 21 formed in the semiconductor substrate 11 is shared by the plurality of pixels P on the back surface (surface 11S2) side of the semiconductor substrate 11. Therefore, it is not necessary to form an anode for each pixel P, and the pixel size can be reduced by the size of the anode forming region described above.

Alternatively, the areas of the n-type diffusion region 23 and the p-type diffusion region 24 may be increased by the size of the anode forming region while maintaining the pixel size. As a result, the size of the avalanche multiplication region X can be increased. Further, since it is not necessary to provide the wiring structure C to be connected to the anode 2110 as in the sensor chip 100 shown in fig. 6, a reflection plate (wiring 15A) for reflecting light transmitted through the semiconductor substrate 11 to the light receiving element 20 can be formed in a larger size. Therefore, Photon Detection Efficiency (PDE) can be improved.

Further, in the typical sensor chip 100, as shown in fig. 6, the pixel separation portion 1200 is integrated with an inter-pixel light shielding film 4300 provided between pixels on the light receiving surface (surface 1100S) side of the semiconductor substrate 1100. In contrast, in the sensor chip 1 of the present embodiment, the pixel separation portion 12 and the inter-pixel light-shielding film 43 are formed independently of each other. Therefore, as indicated by an arrow a shown in fig. 7, the on-chip lens 42 and the inter-pixel light-shielding film 43 can be easily displaced with respect to the pixel P. That is, the degree of freedom in designing the on-chip lens 42 and the inter-pixel light-shielding film 43 with respect to the pixel P is improved. Therefore, pupil correction can be easily performed.

Next, modifications of the present disclosure will be explained. Hereinafter, the same components as in the above-described embodiment are denoted by the same reference numerals, and the description thereof is appropriately omitted.

<2. modification >

(2-1. modified example 1)

Fig. 8 schematically shows an example of a cross-sectional configuration of a sensor chip (sensor chip 2) according to modification 1 of the present disclosure. Fig. 9 schematically shows an example of the cross-sectional configuration at another position in the sensor chip 2. Fig. 10A schematically shows a planar composition taken along the line I-I 'shown in fig. 8 and 9, and fig. 10B schematically shows a planar composition taken along the line II-II' shown in fig. 8 and 9. Note that fig. 8 shows a cross section taken along the line a-a 'shown in fig. 10A and 10B, and fig. 9 shows a cross section taken along the line B-B' shown in fig. 10A and 10B. Similar to the sensor chip 1 of the foregoing embodiment, the sensor chip 2 is configured as, for example, a range image sensor (ranging device) suitable for distance measurement by the ToF method. The sensor chip 2 of the present modification differs from the foregoing embodiment in that a pixel separation portion 61A extending from the back surface (surface 11S2) of the semiconductor substrate 11 to the front surface (surface 11S1) opposite to the back surface is provided between the pixels. The pixel separation section 61A corresponds to a specific example of "second pixel separation section" of the present disclosure.

The pixel separation section 61A is for electrically separating the adjacent pixels P from each other on the rear surface (surface 11S2) side of the semiconductor substrate 11. The pixel separation portion 61A is formed by filling a separation groove 11H2 with a passivation film 61 for protecting the back surface (surface 11S2) of the semiconductor substrate 11, the separation groove 11H2 extending in the thickness direction (Y-axis direction) from the back surface (surface 11S2) of the semiconductor substrate 11. The passivation film 61 may have, for example, an antireflection function, similarly to the foregoing passivation film 41. The passivation film 61 includes, for example, a silicon nitride (SiN) film or a film such as aluminum oxide (AlO)_x) Film, silicon oxide (SiO)_x) Film or tantalum oxide (TaO)_x) Oxide films such as films. Note that the pixel separation portion 61A may not have the above-described configuration, and may have a configuration in which an antireflection film is embedded in an oxide film. Specifically, the inter-pixel light-shielding film 43 may be embedded together with an oxide film (see fig. 11).

As shown in fig. 9, the bottom portion 61S of the pixel separation portion 61A is in contact with the bottom portion 12S of the pixel separation portion 12 extending in the thickness direction (Y-axis direction) from the front surface (surface 11S1) of the semiconductor substrate 11. Further, as shown in fig. 10A, for example, the pixel separation section 61A is provided in the pixel array section R1 arranged in, for example, 5 rows × 2 columns, except for the intersection I between adjacent pixels. As a result, the P-well 21 of the semiconductor substrate 11 is shared by the plurality of pixels P at the intersection I between the adjacent pixels.

As described above, in the present modification, the pixel separation portion 61A extending from the rear surface (surface 11S2) of the semiconductor substrate 11 to the front surface (surface 11S1) facing the rear surface is provided between the pixels. Therefore, in addition to providing the effects of the foregoing embodiments, the light confinement effect on the incident light within the pixel P is improved.

Further, as shown in fig. 11, the interpixel light-shielding film 43 may extend in the pixel separation portion 61A. Therefore, the light confinement effect on the incident light in the pixel P can be further improved.

Further, as shown in fig. 12, the bottom portion 61S of the pixel separation portion 61A and the bottom portion 12S of the pixel separation portion 12 may have a gap G therebetween. In this case, the P-well 21 of the semiconductor substrate 11 is shared by the plurality of pixels P via the gap G, and therefore the pixel separation section 61A may also be provided at the intersection I between adjacent pixels, similarly to the planar shape of the pixel separation section 12 shown in fig. 10B.

(2-2. modification 2)

Fig. 13 schematically shows an example of a cross-sectional configuration of a sensor chip (sensor chip 3) according to modification 2 of the present disclosure. Similar to the sensor chip 1 of the foregoing embodiment, the sensor chip 3 is configured as, for example, a range image sensor (ranging device) suitable for distance measurement by the ToF method. The sensor chip 3 of the present modification differs from the foregoing embodiment in that wiring is connected to the pixel separation section 12.

The wiring 15C, the

pad portions

16C and 34C, and the pad electrode 35C are electrically connected to the pixel separation portion 12 of the present modification via the

contact electrodes

17, 18, and 36, and a voltage can be applied to the pixel separation portion 12 independently of the anode (the contact electrode 17 in the peripheral portion R2) and the cathode (the contact electrode 17 in the pixel array portion R1). As a result, pinning can be performed, thereby suppressing generation of dark current. Further, the electric field applied to the insulating film 12B between the light shielding film 12A and the semiconductor substrate 11 can be reduced, thereby preventing deterioration of the insulating film 12B. Therefore, in addition to providing the effects of the foregoing embodiments, the reliability can be improved.

(2-3. modification 3)

Fig. 14 schematically shows an example of a cross-sectional configuration of a sensor chip (sensor chip 4) according to modification 3 of the present disclosure. Similar to the sensor chip 1 of the foregoing embodiment, the sensor chip 4 is configured as, for example, a range image sensor (ranging device) suitable for distance measurement by the ToF method. The sensor chip 4 of the present modification differs from the foregoing embodiment in that the inter-pixel light-shielding film 43 extends to the peripheral portion R2, and in the peripheral portion R2, the inter-pixel light-shielding film 43 is electrically connected to the p-well 21 of the semiconductor substrate 11 via the opening 41H provided in the passivation film 41.

In the sensor chip 4 of the present modification, as described above, the inter-pixel light-shielding film 43 is electrically connected to the p-well 21 of the semiconductor substrate 11 in the peripheral portion R2. In the peripheral portion R2, the contact electrode 17 is connected as an anode to the p-well 21, and is electrically connected to the bias voltage applying portion 51 via the wiring 15B, the contact electrode 18, the

pad portions

16B and 34B, the contact electrode 36, and the pad electrode 35B. Therefore, the anode potential can be applied to the inter-pixel light-shielding film 43 as well.

Further, in the peripheral portion R2, as shown in fig. 14, for example, the insulating film 19 penetrating the semiconductor substrate 11 may be provided, and different potentials may be applied to the inside and the outside of the insulating film 19. The outside of the insulating film 19 may be connected to Ground (GND), for example. Therefore, in the foregoing embodiment, it is possible to reduce the influence on the connection or the like of the lower substrate (for example, logic substrate 30) due to the potential also being applied to the peripheral portion R2.

<3. application example >

(application example of Mobile body)

The techniques according to the present disclosure are applicable to a variety of products. For example, the techniques according to the present disclosure may be implemented as a device mounted on any type of mobile body, such as an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a boat, a robot, and so on.

Fig. 15 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technique according to the embodiment of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example shown in fig. 15, the vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Further, the microcomputer 12051, the audio/video output section 12052, and the in-vehicle network interface (I/F)12053 are shown as functional configurations of the integrated control unit 12050.

The drive system control unit 12010 controls the operations of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device of: a driving force generating device such as an internal combustion engine or a driving motor for generating a driving force of the vehicle; a driving force transmission mechanism for transmitting a driving force to a wheel; a steering mechanism for adjusting a steering angle of the vehicle; and a brake device for generating a braking force of the vehicle, and the like.

The vehicle body system control unit 12020 controls the operations of various devices provided to the vehicle body according to various programs. For example, the vehicle body system control unit 12020 functions as a control device of a keyless entry system, a smart key system, a power window device, or various lights such as a headlamp, a tail light, a brake light, a turn signal light, or a fog light. In this case, a radio wave or a signal of various switches transmitted from a portable device as a substitute for the key can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, power window device, lamp, and the like of the vehicle.

The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection means 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to form an image of the outside of the vehicle, and receives the captured image. On the basis of the received image, the vehicle-exterior information detection unit 12030 may perform detection processing of objects such as a person, a vehicle, an obstacle, a mark, or a symbol on a road surface, or detection processing of distances to these objects.

The image pickup section 12031 is an optical sensor for receiving light and outputting an electric signal corresponding to the amount of light of the received light. The image pickup section 12031 may output an electric signal as an image, or may output an electric signal as information on a measured distance. Further, the light received by the image pickup portion 12031 may be visible light, or may be invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that images the driver. The in-vehicle information detecting unit 12040 may calculate the degree of fatigue of the driver or the degree of concentration of the driver, or may determine whether the driver is dozing, on the basis of the detection information input from the driver state detecting section 12041.

The microcomputer 12051 can calculate a control target value of the driving force generation device, the steering mechanism, or the brake device on the basis of information on the inside or outside of the vehicle, which is obtained by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 may execute cooperative control intended to realize functions of an Advanced Driver Assistance System (ADAS), including: collision avoidance or collision mitigation of the vehicle, following travel based on the inter-vehicle distance, vehicle speed maintenance travel, vehicle collision warning, vehicle lane departure warning, or the like.

Further, the microcomputer 12051 may execute cooperative control intended for autonomous driving, which causes the vehicle to autonomously run by controlling a driving force generating device, a steering mechanism, a braking device, or the like on the basis of information about the inside or outside of the vehicle, which is obtained by the outside-vehicle information detecting unit 12030 or the inside-vehicle information detecting unit 12040, without depending on the operation of the driver, or the like.

Further, the microcomputer 12051 can output a control command to the vehicle body system control unit 12020 on the basis of information on the outside of the vehicle, which is obtained by the vehicle-exterior information detecting unit 12030. For example, the microcomputer 12051 may perform cooperative control aimed at preventing glare by controlling headlights to change from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detecting unit 12030.

The sound/image output portion 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or aurally notifying a passenger of the vehicle or the outside of the vehicle of information. In the example of fig. 15, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a flat display.

Fig. 16 is a diagram showing an example of the mounting position of the imaging unit 12031.

In fig. 16, the image pickup portion 12031 includes

image pickup portions

12101, 12102, 12103, 12104, and 12105.

The

image pickup portions

12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on a front nose, side mirrors, a rear bumper, and a rear door of the vehicle 12100 and at a position on an upper portion of a vehicle interior windshield. The camera portion 12101 provided to the nose and the camera portion 12105 provided to the upper portion of the vehicle interior windshield mainly obtain an image of the front of the vehicle 12100. The

image pickup portions

12102 and 12103 provided to the side mirrors mainly obtain images of the side of the vehicle 12100. An image pickup unit 12104 provided to a rear bumper or a rear door mainly obtains an image of the rear of the vehicle 12100. The image pickup portion 12105 provided to the upper portion of the windshield in the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, fig. 16 shows an example of the shooting ranges of the image pickup sections 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided to the nose. Imaging ranges 12112 and 12113 represent imaging ranges of the

imaging portions

12102 and 12103 provided to the side mirrors, respectively. The imaging range 12114 indicates an imaging range of an imaging unit 12104 provided to a rear bumper or a rear door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing image data captured by the image capturing sections 12101 to 12104.

At least one of the image pickup portions 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the image pickup sections 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 may determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in the distance (relative speed to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, thereby extracting the closest three-dimensional object as the preceding vehicle, in particular, the three-dimensional object existing on the traveling path of the vehicle 12100 and traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km/hr). Further, the microcomputer 12051 may set in advance an inter-vehicle distance to be maintained ahead of the preceding vehicle, and execute automatic braking control (including following stop control), automatic acceleration control (including following start control), or the like. Therefore, it is possible to perform cooperative control intended for autonomous driving, which causes the vehicle to travel autonomously without depending on the operation of the driver or the like.

For example, the microcomputer 12051 may classify three-dimensional object data on a three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large-sized vehicles, pedestrians, utility poles, and other three-dimensional objects on the basis of distance information obtained from the image pickup portions 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid an obstacle. For example, the microcomputer 12051 recognizes obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 has difficulty visually recognizing. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display portion 12062, and performs forced deceleration or avoidance steering by the drive system control unit 12010. The microcomputer 12051 can thus assist driving to avoid collision.

At least one of the image pickup portions 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the image capturing sections 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a program of extracting feature points in captured images of the image capturing sections 12101 to 12104 as infrared cameras and a program of determining whether or not it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the image capturing sections 12101 to 12104 and thus identifies a pedestrian, the sound/image output section 12052 controls the display section 12062 such that a square contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound/image output portion 12052 may also control the display portion 12062 so that an icon or the like representing a pedestrian is displayed at a desired position.

The description has been given above with reference to the embodiment and modifications 1 to 3; however, the present disclosure is not limited to the foregoing embodiments and the like, and may be modified in various ways. For example, in the foregoing embodiments and the like, an example in which electrons are used as signal charges has been explained; however, holes may also be used as signal charges.

Further, in the foregoing embodiments and the like, the description has been made taking the semiconductor substrate 11 including the p-well 21 as an example; however, in the semiconductor substrate 11, an n-well in which the impurity concentration is controlled to be n-type may also be formed instead of the p-well 21. Further, in the foregoing embodiments and the like, an example in which a negative potential is applied to the anode has been explained; however, each potential is not limited as long as avalanche multiplication occurs by applying a reverse bias between the anode and the cathode.

Further, the effects described in the foregoing embodiments and the like are merely exemplary, and may be any other effects or may also include any other effects.

Note that the present disclosure may have the following constitution. According to the present disclosure having the following configuration, in a pixel array section of a semiconductor substrate in which a plurality of pixels are arranged in an array, a first pixel separation section extending from one face to the other face between the pixels has a bottom portion provided in the semiconductor substrate. Therefore, the semiconductor substrate is shared on the other surface side. As a result, for example, it is not necessary to provide an anode for each pixel, and thus the anode can be commonly used among a plurality of pixels. Therefore, the pixel size can be reduced.

(1) A sensor chip, comprising:

a semiconductor substrate having a pixel array section in which a plurality of pixels are arranged in an array;

a light receiving element provided in the semiconductor substrate for each of the pixels and having a multiplication region in which carriers are avalanche-multiplied by a high electric field region; and

a first pixel separation portion provided between the pixels, the first pixel separation portion extending from one surface of the semiconductor substrate to the opposite other surface and having a bottom in the semiconductor substrate.

(2) The sensor chip according to (1), wherein,

the semiconductor substrate has a well for each of the pixels, and

the well is shared by a plurality of the pixels on the other surface side of the semiconductor substrate.

(3) The sensor chip according to (1) or (2), further comprising a light reflecting section that is laminated on the one surface side of the semiconductor substrate and is provided so as to cover at least a part of the high electric field region.

(4) The sensor chip according to any one of (1) to (3), wherein the first pixel separation portion is constituted by a first light-shielding film including a conductive material having a light-shielding property and an insulating film covering a surface of the first light-shielding film in the semiconductor substrate.

(5) The sensor chip according to any one of (2) to (4), wherein the well is electrically connected to an anode provided in a peripheral portion around the pixel array portion.

(6) The sensor chip according to (5), wherein the anode is commonly used by the plurality of pixels.

(7) The sensor chip according to any one of (1) to (6), wherein the semiconductor substrate further includes a second pixel separation portion that is provided between the pixels and extends from the other surface toward the one surface.

(8) The sensor chip according to (7), wherein the second pixel separation portion is formed of an oxide film.

(9) The sensor chip according to (7) or (8), wherein, in the semiconductor substrate, a bottom of the second pixel separation portion is in contact with a bottom of the first pixel separation portion.

(10) The sensor chip according to any one of (7) to (9), wherein the second pixel separation portion has an opening at an intersection of the plurality of pixels adjacent to each other.

(11) The sensor chip according to (7) or (8), wherein a gap is provided between a bottom of the first pixel separation portion and a bottom of the second pixel separation portion.

(12) The sensor chip according to any one of (1) to (11), further comprising a second light-shielding film between the pixels on the other surface of the semiconductor substrate.

(13) The sensor chip according to (12), wherein the second light-shielding film is electrically connected to the semiconductor substrate in the peripheral portion.

(14) The sensor chip according to any one of (7) to (13), further comprising a second light-shielding film between the pixels on the other surface of the semiconductor substrate,

wherein a portion of the second light shielding film extends in the second pixel separating portion.

(15) The sensor chip according to any one of (4) to (14), further comprising a voltage application section, wherein a voltage is applied from the voltage application section to the first light-shielding film.

(16) The sensor chip according to any one of (1) to (15), wherein,

the semiconductor substrate includes a peripheral portion around the pixel array section, and

the pixel array section and the peripheral section are electrically separated from each other by an insulating film.

(17) The sensor chip according to any one of (1) to (16), further comprising an on-chip lens laminated on the other surface side of the semiconductor substrate.

(18) A distance measuring apparatus includes an optical system, a sensor chip, and a signal processing circuit that calculates a distance to a measurement target object from an output signal of the sensor chip,

wherein the sensor chip comprises:

This application claims priority from japanese patent application No. 2019-065375 filed on 29.3.2019 to the present patent office, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and changes may be made in accordance with design requirements and other factors insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A sensor chip, comprising:

2. The sensor chip of claim 1,

the semiconductor substrate has a well for each of the pixels, and

3. The sensor chip according to claim 1, further comprising a light reflecting portion which is laminated on the one surface side of the semiconductor substrate and is provided so as to cover at least a part of the high electric field region.

4. The sensor chip according to claim 1, wherein the first pixel separation portion is constituted by a first light-shielding film including a conductive material having a light-shielding property, and an insulating film covering a surface of the first light-shielding film in the semiconductor substrate.

5. The sensor chip according to claim 2, wherein the well is electrically connected to an anode provided in a peripheral portion around the pixel array portion.

6. The sensor chip according to claim 5, wherein the anode is commonly used by the plurality of pixels.

7. The sensor chip according to claim 1, wherein the semiconductor substrate further comprises a second pixel separation portion that is provided between the pixels and extends from the other surface toward the one surface.

8. The sensor chip according to claim 7, wherein the second pixel separation portion is formed of an oxide film.

9. The sensor chip according to claim 7, wherein a bottom of the second pixel separation portion is in contact with a bottom of the first pixel separation portion in the semiconductor substrate.

10. The sensor chip according to claim 7, wherein the second pixel separation portion has an opening at an intersection of the adjacent plurality of pixels.

11. The sensor chip according to claim 7, wherein a gap is provided between the bottom of the first pixel isolation portion and the bottom of the second pixel isolation portion.

12. The sensor chip according to claim 1, further comprising a second light-shielding film between the pixels on the other surface of the semiconductor substrate.

13. The sensor chip according to claim 12, wherein the second light-shielding film is electrically connected to the semiconductor substrate in a peripheral portion disposed around the pixel array portion.

14. The sensor chip according to claim 7, further comprising a second light-shielding film between the pixels on the other surface of the semiconductor substrate,

15. The sensor chip according to claim 4, further comprising a voltage applying section,

wherein a voltage is applied from the voltage applying portion to the first light shielding film.

16. The sensor chip of claim 1,

17. The sensor chip according to claim 1, further comprising an on-chip lens stacked on the other surface side of the semiconductor substrate.

18. A distance measuring apparatus includes an optical system, a sensor chip, and a signal processing circuit that calculates a distance to a measurement target object from an output signal of the sensor chip,

wherein the sensor chip comprises: