CN113517185A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113517185A
CN113517185A CN202010277861.XA CN202010277861A CN113517185A CN 113517185 A CN113517185 A CN 113517185A CN 202010277861 A CN202010277861 A CN 202010277861A CN 113517185 A CN113517185 A CN 113517185A
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region
semiconductor substrate
gate
doping
forming
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蔡巧明
马丽莎
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region; forming polysilicon gates on the first region and the second region respectively; performing first ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the first region grid structure, and performing first doping on the polycrystalline silicon grid of the first region; and performing second ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid structure of the second region, and performing second doping on the polysilicon grid of the second region. On one hand, the polysilicon gates of the NFET region and the PFET region are doped, so that the threshold voltage and the unit area resistance are reduced, and the electrical performance is improved; on the other hand, the polycrystalline silicon gate is doped when the source electrode and the drain electrode are formed in the semiconductor substrate, so that the process steps are saved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, the semiconductor technology has penetrated into various fields in life, such as aerospace, medical apparatus and instruments, mobile phone communication, artificial intelligence and other aspects. In the prior art, silicon dioxide is used as a gate dielectric, but in the process of semiconductor Integrated Circuit (IC) evolution, the functional density (i.e., the number of devices connected to each other per unit area of a chip) is rapidly increased, and the geometric size (i.e., the minimum component or connection line that can be manufactured by using a manufacturing process) is continuously reduced, so that the process complexity, difficulty and manufacturing cost of the gate dielectric layer which is continuously shortened and thinned are increased; on the other hand, as the transistor size is continuously reduced, the distance between the source and the drain is also reduced, and thus a Short Channel Effect (SCE) is easily caused. Therefore, an HKMG (High-K Metal Gate) process was developed. The HKMG transistor adopts a gate dielectric layer with high dielectric constant (or called high-K) and adopts a metal material as a gate, compared with the traditional device, the device prepared by adopting the HKMG process greatly reduces leakage current and effectively improves driving current, so that the HKMG becomes the mainstream technology adopted by the high-performance transistor at present.
However, the current HKMG process still suffers from problems and there is a need to provide more efficient or reliable solutions.
Disclosure of Invention
In the HKMG technology using the gate last process, a metal gate is used for a Low Voltage device (LV, Low Voltage) and a polysilicon (Poly-Si) gate is still used for a High Voltage (HV) and Medium Voltage (MV) device, and since the gates of the High Voltage device and the Medium Voltage device are not implanted, the threshold voltages and the resistance per unit area of the NFET and the PFET are too High, which may reduce the performance of the gate.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and a third region, and the semiconductor substrate comprises an isolation structure which separates the first region, the second region and the third region; forming a gate structure, a shielding oxide layer covering the gate structure and a first hard mask covering the shielding oxide layer on the semiconductor substrate of the first region, the second region and the third region respectively, wherein the gate structure comprises a polysilicon gate; forming a patterned first mask layer on the semiconductor substrate, wherein the first mask layer exposes the first hard mask on the first region and the second region of the grid structure; removing the first hard mask on the gate structures of the first region and the second region; removing the first mask layer; performing first ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid electrode structures of the first region and the third region, and performing first doping on the polycrystalline silicon grid electrode of the first region; and performing second ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid structure of the second region, and performing second doping on the polysilicon grid of the second region.
In some embodiments of the present application, the performing a first ion implantation to form a source and a drain in the semiconductor substrate at two sides of the gate structures of the first region and the third region, and performing a first doping on the polysilicon gate of the first region includes: forming a patterned second mask layer on the semiconductor substrate, wherein the second mask layer covers the second area; performing first ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid electrode structures of the first region and the third region, and simultaneously performing first doping on the polycrystalline silicon grid electrode of the first region by the first ions; and removing the second mask layer.
In some embodiments of the present application, the performing a second ion implantation to form a source and a drain in the semiconductor substrate at two sides of the gate structure of the second region, and performing a second doping on the polysilicon gate of the second region includes: forming a patterned third mask layer on the semiconductor substrate, wherein the third mask layer covers the first area and the third area; performing second ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate on two sides of the second region, and performing second doping on the polysilicon gate of the second region by the second ions; and removing the third mask layer.
In some embodiments of the present application, the first region is a high or medium voltage NFET device region; the second region is a high or medium voltage PFET device region and the third region is a core device region.
In some embodiments of the present application, the doping concentration of the first doping is 1013-1016 atoms/cm 2; the doping concentration of the second doping is 1013-1016 atoms/cm 2.
In some embodiments of the present application, the method further comprises: and forming a second hard mask on the gate structures of the first region and the second region.
Another aspect of the present application also provides a semiconductor structure comprising: a semiconductor substrate including a first region, a second region, and a third region, and including an isolation structure separating the first region, the second region, and the third region; a gate structure on the first, second and third regions, the gate structure comprising a doped polysilicon gate; and the source electrode and the drain electrode are respectively positioned in the semiconductor substrates at two sides of the grid structure.
In some embodiments of the present application, the first region is a high-voltage or medium-voltage NFET device region, and a doping type of a polysilicon gate on the first region is N-type; the second region is a high-voltage or medium-voltage PFET device region, and the doping type of a polysilicon gate on the second region is P type.
In some embodiments of the present application, the doping concentration of the polysilicon gate on the first region is 1013-1016 atoms/cm 2; the doping concentration of the polysilicon gate on the second region is 1013-1016 atoms/cm 2.
In some embodiments of the present application, the semiconductor structure further comprises: a second hard mask over the isolation structure.
According to the semiconductor structure and the forming method thereof, on one hand, the polysilicon gates of the NFET region and the PFET region are doped, so that the threshold voltage and the unit area resistance are reduced, and the electrical performance of a device is improved; on the other hand, the doping of the polysilicon gate is completed when the source electrode and the drain electrode are formed in the semiconductor substrate, so that the process steps are saved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic plan view of a semiconductor structure according to some embodiments of the present application;
FIG. 2 is a cross-sectional flow diagram of a method of forming a semiconductor structure according to some embodiments of the present application;
fig. 3-17 are schematic cross-sectional structures of steps in a method of forming a semiconductor structure according to some embodiments of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor structure according to some embodiments of the present disclosure. Referring to fig. 1, the semiconductor structure includes a semiconductor substrate 100, and an NFET (N-type field effect transistor) area gate 101, a PFET (P-type field effect transistor) area gate 102, a core device area gate 103, a source 105 and a drain 106 on both sides of the gates, and a metal interconnection structure 104 for electrically connecting the gates are formed on the semiconductor substrate 100. It should be noted that fig. 1 does not represent a top view of the semiconductor structure, but only schematically illustrates the distribution of the core device region, the PFET region and the NFET region in the semiconductor structure, and only a part of the structure is shown in the figure, and the rest of the structure (e.g., the contact structure) is not shown. In addition, cross-sectional views of the semiconductor structure in a channel length direction and a channel width direction are provided in the specification, wherein the cross-sectional view in the channel length direction refers to a cross-sectional view along a-a direction in fig. 1, and the cross-sectional view in the channel width direction refers to a cross-sectional view along a B-B direction in fig. 1.
In the HKMG high and medium voltage devices, because the NFET region gate 101 and the PFET region gate 102 are undoped polysilicon gates, and the thickness of TiN layer under the polysilicon gates is generally thin (e.g., 10 to 25 angstroms), the threshold voltage (Vt) and sheet resistance (Rs) of the NFET and PFET regions are too high, thereby degrading gate performance. In view of the above problems, the present application provides a semiconductor structure and a method for forming the same, which dopes polysilicon gates of the NFET region and the PFET region to reduce the threshold voltage and the resistance per unit area, thereby improving the electrical performance of the gates.
Fig. 2 is a flow chart of a method of forming a semiconductor structure according to some embodiments of the present application.
Referring to fig. 2, the method for forming the semiconductor structure includes:
step S210: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and a third region, and the semiconductor substrate comprises an isolation structure which separates the first region, the second region and the third region;
step S220: forming a gate structure, a shielding oxide layer covering the gate structure and a first hard mask covering the shielding oxide layer on the semiconductor substrate of the first region, the second region and the third region respectively, wherein the gate structure comprises a polysilicon gate;
step S230: forming a patterned first mask layer on the semiconductor substrate, wherein the first mask layer exposes the first hard mask on the first region and the second region of the grid structure;
step S240: removing the first hard mask on the gate structures of the first region and the second region;
step S250: removing the first mask layer;
step S260: performing first ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid electrode structures of the first region and the third region, and performing first doping on the polycrystalline silicon grid electrode of the first region;
step S270: and performing second ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid structure of the second region, and performing second doping on the polysilicon grid of the second region.
Fig. 3 to 17 are schematic structural views of steps in a method for forming a semiconductor structure according to some embodiments of the present application. A method of forming the semiconductor structure described herein is described below with reference to fig. 3-17.
Referring to fig. 3, step S210, a semiconductor substrate 300 is provided, the semiconductor substrate 300 includes a first region 301, a second region 302 and a third region 303, and the semiconductor substrate 300 includes an isolation structure 310, the isolation structure 310 separates the first region 301, the second region 302 and the third region 303.
In some embodiments of the present application, the material of the semiconductor substrate 300 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 300 may also be a structure grown with an epitaxial layer.
In some embodiments of the present application, the first region 301 is defined as a high or medium voltage NFET device region; the second region 302 is a high or medium voltage PFET device region and the third region 303 is a core device region. The NFET device region is formed, for example, by P-type doping in the first region 301; the method of forming the PFET device region is, for example, N-type doping in the second region 302; the core device region may be P-type doped or N-type doped.
The isolation structure 310 may be made of silicon oxide or a composite layer of silicon oxide and silicon nitride or silicon oxynitride, and the first region 301, the second region 302, and the third region 303 in the semiconductor substrate 300 may be separated by the isolation structure 310.
Referring to fig. 4 to 6, in step S220, a gate structure, a shielding oxide layer 350 covering the gate structure, and a first hard mask 351 covering the shielding oxide layer 350 are formed on the semiconductor substrate 300 of the first region 301, the second region 302, and the third region 303, respectively, where the gate structure includes a gate dielectric layer 320, a blocking layer 330, a polysilicon gate 340, and sidewalls 360 on two sides of the gate dielectric layer 320, the blocking layer 330, and the polysilicon gate 340, which are sequentially located on the semiconductor substrate 300.
Referring to fig. 4, a gate dielectric layer 320, a barrier layer 330, a polysilicon gate 340 and a shield oxide layer 350 are sequentially formed on the semiconductor substrate 300 and the isolation structure 310.
The gate dielectric layer 320 comprises a high dielectric constant material, for example, in some embodiments of the present application, the gate dielectric layer 320 may comprise at least one of silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, and aluminum oxide.
In some embodiments of the present application, the gate dielectric layer 320 includes: a first dielectric layer 321 and a second dielectric layer 322 sequentially disposed on the semiconductor substrate 300 and the isolation structure 310. Wherein the material of the first dielectric layer 321 is, for example, silicon oxide; the material of the second dielectric layer 322 is, for example, hafnium oxide.
In other embodiments of the present application, the gate dielectric layer 320 may also include more dielectric layers, such as a composite structure of three dielectric layers or a composite structure of four dielectric layers. For example, the gate dielectric layer 320 may include a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially disposed on the semiconductor substrate 300 and the isolation structure 310, wherein the first dielectric layer is made of, for example, silicon oxide; the material of the second dielectric layer is hafnium oxide for example; the material of the third dielectric layer is tantalum oxide, for example.
In some embodiments of the present application, the method of forming the gate dielectric layer 320 includes a thermal oxidation process, an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or the like.
In the HKMG process, the barrier layer 330 may be used to block the diffusion of the metal element in the metal gate to the gate dielectric layer, which may cause short-circuit breakdown of the gate dielectric layer, and the barrier layer 330 may also protect the gate dielectric layer during the subsequent etching of the polysilicon gate 340.
In some embodiments of the present application, the material of the barrier layer 330 includes a metal nitride, such as titanium nitride. In other embodiments of the present application, the barrier layer material may be selected as appropriate, depending on the material selected for the actual gate and gate dielectric layers.
In some embodiments of the present application, the method for forming the barrier layer 330 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the method for forming the polysilicon gate 340 includes a chemical vapor deposition process or a physical vapor deposition process.
Since the polysilicon gate 340 on the first region 301 and the second region 302 needs to be doped in the subsequent process, if the polysilicon gate 340 is directly doped, the polysilicon gate 340 may be damaged, and the performance of the polysilicon gate 340 may be affected, so that the shield oxide layer 350 needs to be formed to protect the polysilicon gate 340 in the doping process.
In some embodiments of the present application, the material of the screen oxide layer 350 includes silicon oxide.
In some embodiments of the present application, the method for forming the shielding oxide layer 350 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 5, a first hard mask 351 is formed on the surface of the shielding oxide layer 350, and the gate dielectric layer 320, the barrier layer 330, the polysilicon gate 340 and the shielding oxide layer 350 at the joint of the first region 301 and the second region 302 and the joint of the second region 302 and the third region 303 are etched by using the first hard mask 351 as a mask layer until the isolation structure 310 is exposed, so as to form the polysilicon gate 340 and the first opening 311 and the second opening 312 with designed lengths.
In some embodiments of the present application, the material of the first hard mask 351 includes silicon nitride.
In some embodiments of the present application, a method of forming the first opening 311 and the second opening 312 includes dry etching or wet etching.
Referring to fig. 6, sidewalls 360 are formed on both sides of the first opening 311 and the second opening 312. The spacers 360 may protect the polysilicon gate 340, the barrier layer 330 and the gate dielectric layer 320.
In some embodiments of the present application, the material of the sidewall spacers 360 includes silicon nitride or silicon oxide.
In some embodiments of the present application, the sidewall spacers 360 may have a single-layer structure. In other embodiments of the present application, the sidewall spacer 360 may also be a multi-layer composite structure, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride structure.
In some embodiments of the present application, the method of forming the sidewalls 360 on both sides of the first opening 311 and the second opening 312 includes: depositing a sidewall material layer in the first opening 311 and the second opening 312 and on the first hard mask 351; and etching the side wall material layer to form the side wall 360.
In some embodiments of the present application, the method of forming the sidewall material layer in the first opening 311 and the second opening 312 and on the first hard mask 351 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the method for etching the sidewall spacer material layer to form the sidewall spacer 360 includes dry etching.
Referring to fig. 7, in step S230, a patterned first mask layer 361 is formed on the semiconductor substrate 300, wherein the first mask layer 361 exposes the first hard mask 351 and the sidewall spacers 360 on the gate structures of the first region 301 and the second region 302; in step S240, the first hard mask 351 and the sidewall spacers 360 higher than the shielding oxide layer 350 on the gate structures of the first region 301 and the second region 302 are removed.
Since the polysilicon gate on the third region 303 does not need to be doped, so as to avoid affecting the etching step of removing the polysilicon gate 340 on the third region 303 in the subsequent process, the first hard mask 351 on the third region 303 is retained, and the polysilicon gate 340 on the third region 303 is prevented from being doped.
Referring to fig. 8, in step S250, the first mask layer 361 is removed.
Referring to fig. 9, in step S260, a first ion implantation is performed to form a source 304 and a drain 305 in the semiconductor substrate 300 at two sides of the gate structures in the first region 301 and the third region 303, and a first doping is performed to the polysilicon gate 340 in the first region 301. The doping type of the first doping is opposite to the doping type of the semiconductor substrate 300 of the first region 301. Since the doping type of the third region 303 is the same as that of the first region 301, a source and a drain can be simultaneously formed.
Referring to fig. 9, the method for forming a source 304 and a drain 305 in the semiconductor substrate 300 at two sides of the gate structures in the first region 301 and the third region 303 and performing a first doping on the polysilicon gate 340 in the first region 301 includes: forming a patterned second mask layer 362 on the semiconductor substrate 300, performing first ion implantation on the second mask layer 362 to cover the second region 302, forming a source 304 and a drain 305 in the semiconductor substrate 300 on two sides of the gate structures of the first region 301 and the third region 303, and simultaneously performing first doping on the polysilicon gate of the first region 301 by the first ions.
Referring to fig. 10, in step S270, a second ion implantation is performed to form a source 304 and a drain 305 in the semiconductor substrate 300 on both sides of the gate structure of the second region 302, and a second doping is performed to the polysilicon gate 340 of the second region 302. The doping type of the second doping is opposite to the doping type of the semiconductor substrate 300 of the second region 302.
Referring to fig. 10, the second mask layer 362 is removed; forming a patterned third mask layer 363 on the semiconductor substrate 300, wherein the third mask layer 363 covers the first region 301 and the third region 303; and performing second ion implantation to form a source 304 and a drain 305 in the semiconductor substrate 300 on two sides of the second region 302, and simultaneously performing second doping on the polysilicon gate 340 of the second region 302 by the second ions.
Referring to fig. 11, the third mask layer 363 is removed.
It should be noted that, in the present application, the order of the steps of the semiconductor structure forming method is not limited, for example, step S260 may be performed first, a first ion implantation is performed, a source 304 and a drain 305 are formed in the semiconductor substrate 300 on both sides of the gate structure in the first region 301 and the third region 303, and a first doping is performed on the polysilicon gate 340 in the first region 301; step S270 may be performed first, a second ion implantation is performed, a source 304 and a drain 305 are formed in the semiconductor substrate 300 on both sides of the gate structure of the second region 302, and the polysilicon gate 340 of the second region 302 is doped second. Those skilled in the art can understand that the order of the steps of the method for forming a semiconductor structure described in the embodiments of the present application can be properly adjusted, and still achieve the technical effects of the technical solutions described in the present application.
In some embodiments of the present application, the first region 301 is a high or medium voltage NFET device region, and the first doping is of an N-type since the doping type of the first doping is opposite to the doping type of the semiconductor substrate 300 of the first region 301; the second region is a high or medium voltage PFET device region and the second doping is of a P-type due to its opposite doping type to the semiconductor substrate 300 in the second region 302. The first doping and the second doping and doping particles and the doping energy may be selected as desired.
In some embodiments of the present application, the first doped doping particle is, for example, phosphorus, with a doping concentration of 1013-1016 atoms/cm 2; the second doped doping particle is boron, for example, with a doping concentration of 1013-1016 atoms/cm 2. Adjusting the doping concentration can further adjust the resistance per unit area of the polysilicon gate 340, and the higher the doping concentration, the lower the resistance per unit area of the polysilicon gate 340.
Referring to fig. 11, in the method for forming a semiconductor structure according to this embodiment, on one hand, since the polysilicon gate layer 340 on the first region 301 and the second region 302 is doped, the resistance per unit area is reduced; on the other hand, since the doping types of the polysilicon gate layer 340 on the first region 301 and the polysilicon gate layer 340 on the second region 302 are respectively opposite to the doping types of the first region 301 and the second region 302, the gate work function is adjusted, so that the threshold voltage is reduced, and the electrical performance of the device is improved. And the polysilicon gate 340 on the third region 303 cannot be doped, so that the subsequent etching effect on the polysilicon gate 340 on the third region 303 cannot be influenced. In addition, the doping of the polysilicon gate 340 is completed at the same time of forming the source 304 and the drain 305 in the semiconductor substrate 300, thereby saving process steps.
Referring to fig. 12, a second hard mask 352 is formed on the isolation structure 310, the shielding oxide 350 of the first region 301 and the second region 302, and the sidewall spacers 360; a metal silicide 370 is formed on the source 304 and drain 305.
The first hard mask 351 and the second hard mask 352 may ensure that the metal silicide 370 is formed only on the source 304 and drain 305.
In some embodiments of the present application, the material of the second hard mask 352 comprises silicon nitride.
In some embodiments of the present application, the material of the metal silicide 370 includes nickel silicide, titanium silicide, zirconium silicide, tungsten silicide, tantalum silicide, or the like.
Referring to fig. 13, the first hard mask 351, the second hard mask 352, the shielding oxide layer 350 and the sidewalls 360 above the polysilicon gate 340 are removed.
In some embodiments of the present application, the method of removing the first hard mask 351, the second hard mask 352, the shield oxide 350 and the sidewall spacers 360 above the polysilicon gate 340 includes chemical mechanical polishing.
Referring to fig. 14, the polysilicon gate 340 in the third region 303 is removed, and a metal gate 341 is formed in the original position of the polysilicon gate 340 in the third region 303.
In some embodiments of the present application, the material of the metal gate 341 includes aluminum or copper.
In some embodiments of the present application, the method for removing the polysilicon gate 340 in the third region 303 includes dry etching or wet etching.
In some embodiments of the present application, a method of forming the metal gate 341 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 15, fig. 15 is a cross-sectional view of the semiconductor structure in a channel width direction. Etching the polysilicon gate 340, and forming a second opening and a third opening in the first region 301 and the second region 302 respectively, where the second opening and the third opening are located at the connection between the polysilicon gate 340 and the sidewall 360 on the isolation structure of the first region 301 and at the connection between the polysilicon gate 340 and the sidewall 360 on the isolation structure of the second region 302; a metal interconnect structure 380 is formed within the second opening and the third opening.
In some embodiments of the present application, the method of forming the second opening and the third opening includes dry etching or wet etching.
In some embodiments of the present application, the material of the metal interconnect structure 380 includes aluminum or copper.
In some embodiments of the present application, the method of forming the metal interconnect structure 380 includes a chemical vapor deposition process or a physical vapor deposition process, etc.
It should be noted that the metal interconnection structure 380 and the metal gate 341 may be formed simultaneously; the metal interconnection structure 380 may be formed first, and then the metal gate 341 may be formed; the metal gate 341 may be formed first, and the metal interconnection structure 380 may be formed.
Referring to fig. 16, an interlayer dielectric layer 390 is formed on the surfaces of the second hard mask 352, the metal silicide 370, the spacers 360, the metal gate 341 and the polysilicon gate 340, and a first contact structure 381 penetrating the interlayer dielectric layer 390 and electrically connecting the metal silicide 370 is formed in the interlayer dielectric layer 390.
In some embodiments of the present application, the material of the interlayer dielectric layer 390 comprises silicon oxide.
In some embodiments of the present application, the material of the first contact structure 381 is a metal, such as tungsten, copper, or aluminum.
In some embodiments of the present application, the method of forming the interlayer dielectric layer 390 includes a chemical vapor deposition process or a physical vapor deposition process, etc.
Referring to fig. 17, fig. 17 is a cross-sectional view of the semiconductor structure in a channel width direction. A second contact structure 382 is formed in the interlayer dielectric layer 390 to penetrate the interlayer dielectric layer 390 and electrically connect the metal interconnect structure 380.
In some embodiments of the present application, the material of the second contact structure 382 is a metal, such as tungsten, copper, aluminum, or the like.
According to the method for forming the semiconductor structure, on one hand, the polysilicon gates of the NFET region and the PFET region are doped, so that the threshold voltage and the unit area resistance are reduced, and the electrical performance is improved; on the other hand, the source 304 and the drain 305 are formed in the semiconductor substrate 300 while the polysilicon gate 340 is doped, and the process steps of doping the polysilicon gate 340 and the conventional source and drain forming steps are integrated, so that the process steps are saved.
Embodiments of the present application also provide a semiconductor structure, as shown with reference to fig. 16, comprising: a semiconductor substrate 300, wherein the semiconductor substrate 300 includes a first region 301, a second region 302 and a third region 303, the semiconductor substrate 300 of the first region 301, the second region 302 and the third region 303 includes a source 304 and a drain 305, and the semiconductor substrate 300 includes an isolation structure 310, the isolation structure 310 separates the first region 301, the second region 302 and the third region 303; a gate structure including a gate dielectric layer 320 on the semiconductor substrate 300; the gate structure further includes a barrier layer 330 on the gate dielectric layer 320; the gate structure further comprises a polysilicon gate 340, located on the barrier layer 330 on the first region 301 and the second region 302, wherein the polysilicon gate 340 is doped; the gate structure further comprises a metal gate 341 on the barrier layer 330 over the third region 303; the gate structure further includes spacers 360 located on both sides of the gate dielectric layer 320, the barrier layer 330, and the polysilicon gate 340.
In some embodiments of the present application, the material of the semiconductor substrate 300 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 300 may also be a structure grown with an epitaxial layer.
In some embodiments of the present application, the first region 301 is defined as a high or medium voltage NFET device region; the second region 302 is a high or medium voltage PFET device region and the third region 303 is a core device region.
The isolation structure 310 may be made of silicon oxide or a composite layer of silicon oxide and silicon nitride or silicon oxynitride, and the first region 301, the second region 302, and the third region 303 in the semiconductor substrate 300 may be separated by the isolation structure 310.
With continued reference to fig. 16, the gate dielectric layer 320 comprises a high dielectric constant material, for example, in some embodiments of the present application, the gate dielectric layer 320 may comprise at least one of silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, and aluminum oxide.
In some embodiments of the present application, the gate dielectric layer 320 includes: a first dielectric layer 321 and a second dielectric layer 322 sequentially disposed on the semiconductor substrate 300 and the isolation structure 310. Wherein the material of the first dielectric layer 321 is, for example, silicon oxide; the material of the second dielectric layer 322 is, for example, hafnium oxide.
In other embodiments of the present application, the gate dielectric layer 320 may also include more dielectric layers, such as a composite structure of three dielectric layers or a composite structure of four dielectric layers. For example, the gate dielectric layer 320 may include a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially disposed on the semiconductor substrate 300 and the isolation structure 310, wherein the first dielectric layer is made of, for example, silicon oxide; the material of the second dielectric layer is hafnium oxide for example; the material of the third dielectric layer is tantalum oxide, for example.
With continued reference to fig. 16, the barrier layer 330 may be used to block the diffusion of metal elements in the metal gate into the gate dielectric layer during the HKMG process, causing short-circuit breakdown of the gate dielectric layer, and the barrier layer 330 may also protect the gate dielectric layer during the subsequent etching of the polysilicon gate 340.
In some embodiments of the present application, the material of the barrier layer 330 includes a metal nitride, such as titanium nitride. In other embodiments of the present application, the barrier layer material may be selected as appropriate, depending on the material selected for the actual gate and gate dielectric layers.
With continued reference to fig. 16, the polysilicon gate 340 over the first region 301 and the second region 302 is doped. The material of the metal gate 341 includes aluminum or copper.
In some embodiments of the present application, the first region 301 is a high or medium voltage NFET device region, and the doping types of the polysilicon gates and 340 on the first region 301 are N-type; the second region is a high or medium voltage PFET device region, and the doping types of the polysilicon gates and 340 in the second region 302 are P-type.
In some embodiments of the present application, the doped particles of the polysilicon gates and 340 in the first region 301 are, for example, phosphorus, and the doping concentration is 1013-1016 atoms/cm 2; the doped particles of the polysilicon gate and 340 in the second region 302 are boron, for example, with a doping concentration of 1013-1016 atoms/cm 2. Adjusting the doping concentration can further adjust the resistance per unit area of the polysilicon gate 340, and the higher the doping concentration, the lower the resistance per unit area of the polysilicon gate 340.
In the method for forming a semiconductor structure according to this embodiment, on one hand, the polysilicon gate layer 340 on the first region 301 and the second region 302 is doped, so that the resistance per unit area is reduced; on the other hand, since the doping types of the polysilicon gate layer 340 on the first region 301 and the polysilicon gate layer 340 on the second region 302 are respectively opposite to the doping types of the first region 301 and the second region 302, the gate work function is adjusted, so that the threshold voltage is reduced, and the electrical performance of the device is improved.
With continued reference to fig. 16, the spacers 360 may protect the polysilicon gate 340, the barrier layer 330, and the gate dielectric layer 320.
In some embodiments of the present application, the material of the sidewall spacers 360 includes silicon nitride or silicon oxide.
In some embodiments of the present application, the sidewall spacers 360 may have a single-layer structure. In other embodiments of the present application, the sidewall spacer 360 may also be a multi-layer composite structure, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride structure.
With continued reference to fig. 16, a second hard mask 352 is formed over the isolation structure 310; a metal silicide 370 is formed on the source 304 and drain 305. The second hard mask 352 may protect the isolation structure 310 during subsequent etching of the polysilicon gate layer 340.
In some embodiments of the present application, the material of the second hard mask 352 comprises silicon nitride.
In some embodiments of the present application, the material of the metal silicide 370 includes titanium silicide, zirconium silicide, tungsten silicide, tantalum silicide, or the like.
Referring to fig. 15, fig. 15 is a cross-sectional view of the semiconductor structure in a channel width direction. A metal interconnection structure 380 is formed at the junction between the polysilicon gate layer 340 and the sidewall spacer 360 on the first region 301 isolation structure and at the junction between the polysilicon gate layer 340 and the sidewall spacer 360 on the second region 302 isolation structure.
In some embodiments of the present application, the material of the metal interconnect structure 380 includes aluminum or copper.
With reference to fig. 16, an interlayer dielectric layer 390 is formed on the surfaces of the second hard mask 352, the metal silicide 370, the spacers 360, the metal gate 341 and the polysilicon gate 340, and a first contact structure 381 penetrating the interlayer dielectric layer 390 and electrically connecting the metal silicide 370 is formed in the interlayer dielectric layer 390.
In some embodiments of the present application, the material of the interlayer dielectric layer 390 comprises silicon oxide.
In some embodiments of the present application, the material of the first contact structure 381 is a metal, such as tungsten, copper, or aluminum.
Referring to fig. 17, fig. 17 is a cross-sectional view of the semiconductor structure in a channel width direction. A second contact structure 382 is formed in the interlayer dielectric layer 390 to penetrate the interlayer dielectric layer 390 and electrically connect the metal interconnection structure 380.
In some embodiments of the present application, the material of the second contact structure 382 is a metal, such as tungsten, copper, aluminum, or the like.
In the semiconductor structure, the polysilicon gates of the NFET region and the PFET region are doped, so that the threshold voltage and the unit area resistance are reduced, and the electrical performance is improved.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and a third region, and the semiconductor substrate comprises an isolation structure which separates the first region, the second region and the third region;
forming a gate structure, a shielding oxide layer covering the gate structure and a first hard mask covering the shielding oxide layer on the semiconductor substrate of the first region, the second region and the third region respectively, wherein the gate structure comprises a polysilicon gate;
forming a patterned first mask layer on the semiconductor substrate, wherein the first mask layer exposes the first hard mask on the first region and the second region of the grid structure;
removing the first hard mask on the gate structures of the first region and the second region;
removing the first mask layer;
performing first ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid electrode structures of the first region and the third region, and performing first doping on the polycrystalline silicon grid electrode of the first region;
and performing second ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid structure of the second region, and performing second doping on the polysilicon grid of the second region.
2. The method of claim 1, wherein the first ion implantation to form a source and a drain in the semiconductor substrate on opposite sides of the gate structure in the first region and the third region, and the first doping of the polysilicon gate in the first region comprises:
forming a patterned second mask layer on the semiconductor substrate, wherein the second mask layer covers the second area;
performing first ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid electrode structures of the first region and the third region, and simultaneously performing first doping on the polycrystalline silicon grid electrode of the first region by the first ions;
and removing the second mask layer.
3. The method of claim 1, wherein performing a second ion implantation to form a source and a drain in the semiconductor substrate on both sides of the second region gate structure, and performing a second doping of the polysilicon gate in the second region comprises:
forming a patterned third mask layer on the semiconductor substrate, wherein the third mask layer covers the first area and the third area;
performing second ion implantation, forming a source electrode and a drain electrode in the semiconductor substrate on two sides of the second region, and performing second doping on the polysilicon gate of the second region by the second ions;
and removing the third mask layer.
4. The method of forming of claim 1, in which the first region is an NFET device region; the second region is a PFET device region and the third region is a core device region.
5. The method of claim 1, wherein the first doping has a doping concentration of 1013-1016atom/cm2(ii) a The doping concentration of the second doping is 1013-1016atom/cm2。
6. The method of forming a semiconductor structure of claim 1, further comprising: and forming a second hard mask on the gate structures of the first region and the second region.
7. A semiconductor structure, comprising:
a semiconductor substrate including a first region, a second region, and a third region, and including an isolation structure separating the first region, the second region, and the third region;
a gate structure on the first, second and third regions, the gate structure comprising a doped polysilicon gate;
and the source electrode and the drain electrode are respectively positioned in the semiconductor substrates at two sides of the grid structure.
8. The semiconductor structure of claim 7, wherein the first region is an NFET device region, and a doping type of a polysilicon gate on the first region is N-type; the second region is a PFET device region, and the doping type of a polysilicon gate on the second region is P type.
9. The semiconductor structure of claim 7, wherein a doping concentration of the polysilicon gate over the first region is 1013-1016atom/cm2(ii) a The doping concentration of the polysilicon gate on the second region is 1013-1016atom/cm2。
10. The semiconductor structure of claim 7, further comprising: a second hard mask over the isolation structure.
CN202010277861.XA 2020-04-10 2020-04-10 Semiconductor structure and forming method thereof Pending CN113517185A (en)

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