CN113516948B - Display device and driving method - Google Patents
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- CN113516948B CN113516948B CN202110848554.7A CN202110848554A CN113516948B CN 113516948 B CN113516948 B CN 113516948B CN 202110848554 A CN202110848554 A CN 202110848554A CN 113516948 B CN113516948 B CN 113516948B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The invention provides a display device and a driving method, wherein the display device comprises: a plurality of display panels tiled together, each of the display panels including a plurality of pixel circuits arranged in an array and a signal processor coupled to the plurality of pixel circuits; wherein each of the pixel circuits includes a drive transistor and a data read circuit coupled to a gate of the drive transistor, wherein: the data reading circuit is used for reading the grid potential of the corresponding driving transistor, and the grid potential comprises the threshold voltage of the driving transistor and a data writing signal; the signal processor is used for determining compensation data of other display panels except for the reference display panel in the plurality of display panels according to the grid potential, compensating data signals of the other display panels according to the compensation data, and obtaining compensated data signals so that the other display panels can display according to the compensated data signals.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display device and a driving method thereof.
Background
With the continuous development of the AMOLED flexible display technology, the functions of flexible special-shaped display, splicing display and the like are widely applied.
In the existing AMOLED spliced product, due to differences of process procedures, internal electrical parameters such as mobility, unit area and threshold voltage of each spliced unit are different, so that when the spliced units display the same gray scale, the luminous current is different, the final display brightness of each spliced unit is different, and the screen display effect and the product yield are influenced.
Disclosure of Invention
The invention provides a display device and a driving method, which are used for improving the display uniformity of each spliced panel and ensuring the display effect and the product yield.
In a first aspect, an embodiment of the present invention provides a display device, including:
a plurality of display panels tiled together, each of the display panels including a plurality of pixel circuits arranged in an array and a signal processor coupled to the plurality of pixel circuits; wherein each of the pixel circuits includes a drive transistor and a data read circuit coupled to a gate of the drive transistor, wherein:
the data reading circuit is used for reading the grid potential of the corresponding driving transistor, and the grid potential comprises the threshold voltage of the driving transistor and a data writing signal;
the signal processor is used for determining compensation data of other display panels except the reference display panel in the plurality of display panels according to the grid potential, compensating data signals of the other display panels according to the compensation data, and obtaining compensated data signals so that the other display panels display according to the compensated data signals.
In one possible implementation manner, the signal processor includes an analog-to-digital conversion circuit coupled to at least some of the plurality of pixel circuits and a digital processing circuit coupled to the analog-to-digital conversion circuit, the analog-to-digital conversion circuit is configured to convert analog signals corresponding to the gate potentials obtained from at least some of the pixel circuits into digital signals, and the digital processing circuit is configured to process the digital signals and determine compensation data of the corresponding display panel.
In a possible implementation manner, each display panel further includes a display driver chip, the analog-to-digital conversion circuit and the digital processing circuit are integrated in the display driver chip, and the display driver chip is configured to control the corresponding display panel to display according to the compensated data signal.
In a possible implementation manner, each display panel further includes a display driver chip, and the analog-to-digital conversion circuit and the digital processing circuit are both independently disposed from the display driver chip, wherein the display driver chip is coupled to the digital processing circuit through an MIPI bus.
In one possible implementation manner, the data reading circuit includes a first transistor, a gate of the first transistor is coupled to the read control terminal, a first pole of the first transistor is coupled to the corresponding analog-to-digital conversion circuit, and a second pole of the first transistor is coupled to the gate of the driving transistor.
In a second aspect, an embodiment of the present invention provides a driving method of a display device as described in any one of the above, including:
reading, by the data reading circuit, a gate potential of each driving transistor in at least a part of pixel circuits of each of the plurality of display panels;
and processing the grid potential through the signal processor, determining compensation data of other display panels except for the reference display panel in the plurality of display panels, compensating the data signals of the other display panels according to the compensation data, and obtaining compensated data signals so that the other display panels display according to the compensated data signals.
In one possible implementation manner, the determining, by the signal processor, compensation data for display panels other than the reference display panel among the plurality of display panels by processing the gate potential includes:
determining the threshold voltage of the driving transistor corresponding to at least part of the pixel circuits in each display panel according to the grid potential;
determining an average value of the threshold voltages of the driving transistors corresponding to at least part of the pixel circuits, and taking the average value as the corresponding threshold voltage of the display panel;
determining a threshold voltage of a reference display panel among the plurality of display panels, a data signal to be input to the reference display panel, and threshold voltages of other display panels except the reference display panel;
and determining compensation data for compensating the other display panels according to the threshold voltage of the reference display panel, the data signal and the threshold voltages of the other display panels.
In one possible implementation manner, the determining compensation data for compensating the other display panel according to the threshold voltage of the reference display panel, the data signal, and the threshold voltage of the other display panel includes:
determining a ratio between transconductance of the reference display panel and transconductance of any display panel to be tested in the other display panels according to the threshold voltage of the reference display panel and the threshold voltages of the other display panels;
and determining compensation data for compensating the display panel to be detected according to the ratio and the data signal.
In a possible implementation manner, when each of the driving transistors operates in a linear region, a ratio between a transconductance of the reference display panel and a transconductance of any one of the other display panels to be tested is determined by using the following formula:
V th1 representing the threshold voltage, V, of the reference display panel th2 Representing the threshold voltage, g, of the display panel under test m1 Representing the transconductance, g, of the reference display panel m2 Representing the transconductance, V, of the display panel under test DD Indicating a constant potential.
In one possible implementation manner, when each driving transistor operates in a saturation region, the following formula is used to determine compensation data for compensating the display panel to be tested:
wherein Δ V represents compensation data for compensating the display panel to be measured.
The invention has the following beneficial effects:
the embodiment of the invention provides a display device and a driving method, wherein the display device comprises a plurality of display panels spliced together, each display panel comprises a plurality of pixel circuits arranged in an array and a signal processor coupled with the pixel circuits, each pixel circuit comprises a driving transistor and a data reading circuit coupled with a grid electrode of the driving transistor, the grid electrode potential of the corresponding driving transistor can be read through the data reading circuit, as the grid electrode potential comprises the threshold voltage of the driving transistor and a data writing signal, the signal processor can determine compensation data of other display panels except a reference display panel in the display panels according to the grid electrode potential, and thus, the data signals of the other display panels can be compensated according to the determined compensation data, thereby obtaining the compensated data signal, and the other display panels can display according to the compensated data signal. That is, the data reading circuit is added in the display panel spliced with a plurality of display panels to read the grid potential of the driving transistor in the pixel circuit, and the compensation data of other display panels except the reference display panel is determined according to the grid potential, so that the data signals of other display panels can be compensated until the difference value between the data signals of the other display panels and the data signals of the reference display panel is within a reasonable range, when each display panel displays according to the compensated data signals, the brightness difference between the display panels can be controlled within the reasonable range, the display uniformity of each display panel in the display device is further improved, and the display effect and the product yield are ensured.
Drawings
Fig. 1 is a schematic structural diagram of a display device provided in the related art;
fig. 2 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram illustrating a first arrangement manner of a signal processor in a display device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram illustrating a second arrangement manner of a signal processor in a display device according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a pixel circuit in a display device according to an embodiment of the present invention;
FIG. 7 is a timing diagram of the pixel circuit shown in FIG. 6;
fig. 8 is a flowchart illustrating a method of driving a display device according to an embodiment of the present invention;
FIG. 9 is a flowchart of one method for determining compensation data in step S102 of FIG. 8;
fig. 10 is a flowchart of the method of step S201 in fig. 9.
Description of the reference numerals:
1-a display panel; 2-a pixel circuit; 3-a signal processor; 4-a drive transistor; 5-a data reading circuit; 31-analog-to-digital conversion circuitry; 32-a digital processing circuit; 6-display driving chip; t1 — first transistor; t2 — second transistor; t3 — third transistor; t4 — fourth transistor; t5 — fifth transistor; t6 — sixth transistor; t7-seventh transistor; SEN-read control end; 21-a reset module; 22-a data write module; 23-a compensation module; 24-a first lighting control module; 25-a second lighting control module; c-capacitance; an L-light emitting device; RST-reset signal terminal; GAT-scanning signal terminal; ELVDD — first power supply terminal; ELVSS-second power supply terminal; EM-emission control terminal; vinit-initialization signal terminal; DAT-data signal terminal.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The use of the word "comprise" or "comprises", and the like, in the context of this application, is intended to mean that the elements or items listed before that word, in addition to those listed after that word, do not exclude other elements or items.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
In the prior art, in combination with the display device shown in fig. 1, the display device includes four splicing units, namely a splicing unit 1, a splicing unit 2, a splicing unit 3, and a splicing unit 4, each splicing unit may be from different production batches, and accordingly, the adopted process parameters may also be different, so that there may be a certain difference in the electrical parameters such as mobility μ, unit area Cox, and threshold voltage inside the pixel circuit, in combination with the OLED light-emitting current formula:
therefore, the difference of the electrical parameters of the pixel circuits causes the difference of the light-emitting currents of the OLEDs, so that the final display brightness of each splicing unit is different, and the screen display effect and the product yield are affected.
In view of this, embodiments of the present invention provide a display device and a driving method thereof, which are used to improve the display uniformity of each tiled panel and ensure the display effect and the product yield.
Fig. 2 is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device includes:
a plurality of display panels 1 spliced together, each of the display panels 1 including a plurality of pixel circuits 2 arranged in an array and a signal processor 3 coupled to the plurality of pixel circuits 2; wherein each of the pixel circuits 2 comprises a drive transistor 4 and a data read circuit 5 coupled to a gate of the drive transistor 4, wherein:
the data reading circuit 5 is configured to read a gate potential of the corresponding driving transistor 4, where the gate potential includes a threshold voltage of the driving transistor 4 and a data writing signal;
the signal processor 3 is configured to determine compensation data for the other display panels except the reference display panel in the plurality of display panels 1 according to the gate potential, compensate data signals of the other display panels according to the compensation data, and obtain compensated data signals, so that the other display panels display according to the compensated data signals.
In a specific implementation process, the display device may include a plurality of display panels 1, the number of the plurality of display panels 1 may be set according to a practical application requirement, which is not limited herein, and fig. 2 illustrates a case where the number of the plurality of display panels 1 is two. In addition, the display panels may be seamlessly spliced together, and the separation distance between the two display panels in fig. 2 does not represent an actual setting situation.
Each of the display panels 1 includes a plurality of pixel circuits 2 arranged in an array and a signal processor 3 coupled to the plurality of pixel circuits 2, where the plurality of pixel circuits 2 may be M rows by N columns of pixel circuits 2, where M and N are integers greater than 1, and the specific number of the pixel circuits 2 may be set according to the actual application requirement, which is not limited herein.
The data reading circuit 5 is configured to read the gate potential of the corresponding driving transistor 4, that is, the data reading circuit 5 added in each pixel circuit 2 can read the gate potential of the corresponding driving transistor 4. For example, there are 50 × 50 pixel circuits 2, and the gate potentials of the 50 × 50 driving transistors 4 can be read correspondingly by the data reading circuit 5 in the pixel circuits 2, but this is not limited thereto.
The signal processor 3 is configured to determine compensation data for the other display panels than the reference display panel among the plurality of display panels 1 based on the gate potential, compensation data for compensating the other display panel may be determined with reference to a data signal of the reference display panel, so that the data signals of the other display panels can be compensated according to the compensation data to obtain compensated data signals, so that the data signals of the other display panels can be compensated to have a difference with the data signal of the reference display panel within a reasonable range, and thus, when the display panels 1 display according to the compensated data signal, the brightness difference between the display panels 1 can be controlled within a reasonable range, and then the display uniformity of each display panel 1 in the display device is improved, and the display effect and the product yield are ensured.
In an embodiment of the present invention, as shown in fig. 3, the processor 3 includes an analog-to-digital conversion circuit 31 coupled to at least some of the pixel circuits 2 in the plurality of pixel circuits 2, and a digital processing circuit 32 coupled to the analog-to-digital conversion circuit 31, where the analog-to-digital conversion circuit 31 is configured to convert analog signals corresponding to gate potentials acquired from at least some of the pixel circuits 2 into digital signals, and the digital processing circuit 32 is configured to process the digital signals to determine compensation data of the corresponding display panel 1.
The Analog-to-Digital conversion circuit 31 may be disposed in an Analog-to-Digital converter (ADC), and the Analog-to-Digital conversion circuit 31 converts Analog signals corresponding to gate potentials acquired from at least some of the pixel circuits 2 into Digital signals, so that the Digital processing circuit 32 may perform corresponding processing on the converted Digital signals, thereby ensuring the processing efficiency of the Digital processing circuit 32. The digital processing circuit 32 may be disposed in an Application Processor (AP) or a Field Programmable Gate Array (FPGA), and is not limited herein.
In the embodiment of the present invention, each display panel 1 further includes a display driving chip 6 for controlling the corresponding display panel 1 to display, and the signal processor 3 may have the following two arrangements, but is not limited to the following two arrangements, which is not limited herein.
As shown in fig. 4, which is a schematic structural diagram corresponding to a first arrangement manner of the signal processor 3 in the display device, the analog-to-digital conversion circuit 31 and the digital processing circuit 32 are both integrated in the display driving chip 6, and the display driving chip 6 is configured to control the corresponding display panel 1 to display according to the compensated data signal. The analog-to-digital conversion circuit 31 and the digital processing circuit 32 are integrated in the display driving chip 6, on one hand, the integrated design of each display panel 1 is guaranteed, and on the other hand, the signal processor 3 occupies a larger space, so that the use performance of the display device is improved. In addition, limited by the area of the display driver chips 6 in each display panel 1, a multiplexing control circuit coupled to the corresponding display driver chip 6 is further disposed in each display panel 1, and by the multiplexing control circuit, while the narrow frame design of each display panel 1 is ensured, the display driver chip 6 integrated with the analog-to-digital conversion circuit 31 and the digital processing circuit 32 is ensured to read the gate potentials of the driver transistors 4 in the plurality of pixel circuits 2 in the corresponding display panel 1, thereby improving the usability of the display device.
As shown in fig. 5, which is a schematic structural diagram corresponding to a second arrangement manner of the signal Processor 3 in the display device, the analog-to-digital conversion circuit 31 and the digital processing circuit 32 are both independently arranged from the display driver chip 6, wherein the display driver chip 6 and the digital processing circuit 32 are coupled via a Mobile Industry Processor Interface (MIPI) bus.
The display driving chip 6 is coupled to the digital processing circuit 32 through an MIPI bus, so that after the digital processing circuit 32 determines the compensation data of the other display panels except the reference display panel in the plurality of display panels 1 according to the extracted gate potential, the compensation data can be transmitted to the display driving chip 6 of each display panel through the MIPI bus, and thus, the display driving chip 6 can display an image to be displayed according to the compensated data signal, thereby ensuring the display effect of the display device.
As shown in fig. 6, which is a schematic structural diagram of the pixel circuit 2 in the display device, the data reading circuit 5 includes a first transistor T1, a gate of the first transistor T1 is coupled to the read control terminal SEN, a first pole of the first transistor T1 is coupled to the corresponding analog-to-digital conversion circuit 31, and a second pole of the first transistor T1 is coupled to the gate of the driving transistor 4.
The gate of the first transistor T1 is coupled to the read control terminal SEN, and a read control signal can be applied to the first transistor T1 through the read control terminal SEN, so that the gate potential of the driving transistor 4 can be read by controlling the timing of the read control signal, and flexible control of data compensation in the display device is realized.
Still referring to fig. 6, taking the pixel circuit 2 as 7T1C as an example, each pixel circuit 2 in the display device further includes a reset module 21, a data writing module 22, a compensation module 23, a first light-emitting control module 24, a second light-emitting control module 25, a capacitor C, and a light-emitting device L, where:
the reset module 21 is respectively coupled to the gate of the driving transistor 4 and the first pole of the light emitting device L, and is configured to reset the gate of the driving transistor 4 and the first pole of the light emitting device L under the control of a reset control signal loaded by a reset signal terminal RST;
the data writing module 22 is coupled to the first pole of the driving transistor 4, and configured to load a data signal to the first pole of the driving transistor 4 under the control of a scan control signal loaded by a scan signal terminal GAT;
the compensation module 23 is coupled between the gate and the second pole of the driving transistor 4, and is used for writing the threshold voltage of the driving transistor 4 into the gate of the driving transistor 4 under the control of the scan control signal loaded by the scan signal terminal GAT;
the first light emitting control module 24 is coupled to the gate of the driving transistor 4 through the capacitor C, and is coupled between the first power terminal ELVDD and the first pole of the driving transistor 4, and configured to apply a first potential signal provided by the first power terminal ELVDD to the first pole of the driving transistor 4 under the control of an effective light emitting control signal applied by the light emitting control terminal EM;
the second light-emitting control module 25 is respectively coupled to a second pole of the driving transistor 4 and a first pole of the light-emitting device L, and is configured to apply the driving current provided by the driving transistor 4 to the first pole of the light-emitting device L under the control of the effective light-emitting control signal applied by the light-emitting control terminal EM, where the second pole of the light-emitting device L is coupled to the second power terminal ELVSS.
The reset module 21 includes a second transistor T2 and a third transistor T3, a gate of the second transistor T2 is coupled to the reset signal terminal RST, a first pole of the second transistor T2 is coupled to the gate of the driving transistor 4, a second pole of the second transistor T2 is coupled to an initialization signal terminal Vinit, a gate of the third transistor T3 is coupled to the scan signal terminal GAT, a first pole of the third transistor T3 is coupled to the first pole of the light emitting device L, and a second pole of the third transistor T3 is coupled to the initialization signal terminal Vinit.
The data write module 22 includes a fourth transistor T4, a gate of the fourth transistor T4 is coupled to the scan signal terminal GAT, a first pole of the fourth transistor T4 is coupled to the first pole of the driving transistor 4, and a second pole of the fourth transistor T4 is coupled to the data signal terminal DAT.
The compensation module 23 includes a fifth transistor T5, a gate of the fifth transistor T5 is coupled to the scan signal terminal GAT, a first pole of the fifth transistor T5 is coupled to the gate of the driving transistor 4, and a second pole of the fifth transistor T5 is coupled to the second pole of the driving transistor 4.
The first light emission control module 24 includes a sixth transistor T6, a gate of the sixth transistor T6 is coupled to the light emission control terminal EM, a first pole of the sixth transistor T6 is coupled to the first power source terminal ELVDD, and a second pole of the sixth transistor T6 is coupled to the first pole of the gate driving transistor 4; the second light emission control module 25 includes a seventh transistor T7, a gate of the seventh transistor T7 is coupled to the light emission control terminal EM, a first pole of the seventh transistor T7 is coupled to the second pole of the driving transistor 4, and a second pole of the seventh transistor T7 is coupled to the first pole of the light emitting device L.
It should be noted that all transistors mentioned in the embodiments of the present invention may be P-type transistors, or all transistors may be N-type transistors, where when all transistors of the same type are designed, the manufacturing process flow of the pixel circuit 2 is simplified. All the transistors may be Thin Film Transistors (TFTs) or Metal Oxide Semiconductor field effect transistors (MOS), and are not limited thereto. In addition, the functions of the first pole and the second pole of the transistors can be interchanged according to the type of the switching transistor and the signal of the signal terminal, wherein the first pole can be a source and the second pole can be a drain, or the first pole can be a drain and the second pole can be a source, and no specific distinction is made here.
The following describes the operation of the pixel circuit 2 according to the embodiment of the present invention by taking the pixel circuit 2 shown in fig. 6 and the timing sequence shown in fig. 7 as examples. The initialization signal terminal Vinit provides a low level signal, the first power supply terminal ELVDD provides a high level signal, the second power supply terminal ELVSS provides a low level signal, and all the transistors are P-type transistors.
In a reset phase corresponding to t1, the gate potential of the driving transistor 4 is Vinit; in the data writing phase corresponding to t2, the gate potential of the driving transistor 4 is (V) data -V th ) Wherein V is data A data signal V indicating writing of the data signal terminal DAT th Represents the threshold voltage of the drive transistor 4; in the light emitting period corresponding to t3, the light emitting current of the light emitting device L is
In a specific implementation process, the extraction of the gate potential of each display panel 1 may be performed on all the pixel circuits 2 in the display panel 1, or may be performed by selecting only some of the pixel circuits 2, for example, only the gate potentials corresponding to 50 × 50 pixel circuits 2 are extracted, and for example, only the gate potentials corresponding to 100 × 100 pixel circuits 2 are extracted, and the specific number of the extraction may be set according to actual application requirements, which is not limited herein.
Extracting a gate potential (V) corresponding to the N1 point through the first transistor T1 data -V th ) Wherein the data signal V written by the data signal terminal DAT data It is known that V can be calculated for each pixel position based on the extracted gate potential th The value is obtained. For any display panel 1 of the display device, all or part of the pixels V can be used th Is taken as the average value of V of the display panel 1 th The calculation of the display panel 1 in which the driving transistor 4 operates in the linear region is as follows:
wherein, the transconductance corresponding to the driving transistor 4
Taking the display device as an example that two display panels are spliced together, wherein the display panel 1 is a reference display panel and the display panel 2 is a display panel to be compensated, a process of determining compensation data of the display panel to be compensated by extracting a gate potential will be explained.
According to the calculation formula of the display panel in which the driving transistor 4 operates in the linear region:
working linearly on the display panel 1Current in time zone I D1 Current I in linear region with the display panel 2 D2 When the two signals are equal, the transconductance g of the display panel 1 is shown m1 Transconductance g corresponding to the display panel 2 m2 The ratio K between is:
due to V gs1 ＝V data -V th1 -V DD ，V gs2 ＝V data -V th2 -V DD ，V DD Represents a constant potential, V th1 Indicating the threshold voltage, V, of the reference display panel th2 Representing the threshold voltage, g, of the display panel under test m1 Representing the transconductance, g, of the reference display panel m2 The transconductance of the display panel under test is shown, and as can be seen,
in the light emitting stage, the driving transistor 4 in each pixel circuit 2 operates in the saturation region, and the current formula in the saturation region indicates that:
the transconductance ratio K is combined to compensate the data
If the reference write data signal of the display panel 1 is V data Accordingly, the compensated data of the display panel 2 is V data +ΔV。
Based on the same compensation principle, when the number of spliced display panels is three or more, data compensation of each display panel in the display device can be still realized, so that the display uniformity of the display device is improved, and the display effect and the product yield are ensured.
It should be noted that the display device provided in the embodiment of the present invention may be a mobile phone, and may also be any product or component having a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present invention.
Based on the same inventive concept, as shown in fig. 8, an embodiment of the present invention further provides a method flowchart of a driving method of a display device, where the driving method includes:
s101: reading, by the data reading circuit, a gate potential of each driving transistor in at least a part of pixel circuits of each of the plurality of display panels;
s102: and processing the grid potential through the signal processor, determining compensation data of other display panels except for the reference display panel in the plurality of display panels, compensating the data signals of the other display panels according to the compensation data, and obtaining compensated data signals so that the other display panels display according to the compensated data signals.
In a specific implementation, the gate potentials of the driving transistors 4 in at least some of the pixel circuits 2 in the respective display panels 1 can be read by the data reading circuit 5 as described above, the gate potential may represent an electrical parameter of each display panel 1, such that, after subsequent processing of the gate potential by the signal processor 3, compensation data for the other display panels than the reference display panel in the respective display panels 1 can be determined, the data signals of the other display panels may then be compensated based on the compensation data to obtain compensated data signals, which, when the other display panels display according to the compensated data signals, the display device can be ensured to have better display uniformity, and the display effect and the product yield of the display device are ensured.
For the specific structure of the display device in the driving method, reference may be made to the description of the foregoing section. In addition, since the technical problem to be solved by the driving method of the display device is the same as that of the display device, repeated descriptions are omitted.
As shown in fig. 9, the step S102 of determining compensation data for the display panels other than the reference display panel among the plurality of display panels 1 by processing the gate potential by the signal processor 3 includes:
s201: determining the threshold voltage of the driving transistor corresponding to at least part of the pixel circuits in each display panel according to the grid potential;
s202: determining an average value of the threshold voltages of the driving transistors corresponding to at least part of the pixel circuits, and taking the average value as the corresponding threshold voltage of the display panel;
s203: determining a threshold voltage of a reference display panel among the plurality of display panels, a data signal to be input to the reference display panel, and threshold voltages of other display panels except the reference display panel;
s204: and determining compensation data for compensating the other display panels according to the threshold voltage of the reference display panel, the data signal and the threshold voltages of the other display panels.
For the specific implementation process of step S201 to step S204, reference may be made to the description of the foregoing display device portion, which is not described herein again.
As shown in fig. 10, step S201: determining compensation data for compensating the other display panel according to the threshold voltage of the reference display panel, the data signal, and the threshold voltage of the other display panel, including:
s301: determining a ratio between transconductance of the reference display panel and transconductance of any display panel to be tested in the other display panels according to the threshold voltage of the reference display panel and the threshold voltages of the other display panels;
s302: and determining compensation data for compensating the display panel to be detected according to the ratio and the data signal.
For the specific implementation of step S301 to step S302, reference may be made to the description in the foregoing display device, and repeated descriptions are omitted.
In the embodiment of the present invention, when each of the driving transistors 4 operates in a linear region, a ratio between transconductance of the reference display panel and transconductance of any one of the other display panels to be tested is determined by using the following formula:
V th1 representing the threshold voltage, V, of the reference display panel th2 Representing the threshold voltage, g, of the display panel under test m1 Representing the transconductance, g, of the reference display panel m2 Representing the transconductance, V, of the display panel under test DD Representing a constant potential.
In the embodiment of the present invention, when each of the driving transistors 4 operates in the saturation region, the following formula is used to determine the compensation data for compensating the display panel to be tested:
wherein Δ V represents compensation data for compensating the display panel to be measured.
Accordingly, the specific implementation part is the same as the related description in the foregoing display device, and repeated descriptions are omitted.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (9)
1. A display device, comprising:
a plurality of display panels tiled together, each of the display panels including a plurality of pixel circuits arranged in an array and a signal processor coupled to the plurality of pixel circuits; wherein each of the pixel circuits includes a drive transistor and a data read circuit coupled to a gate of the drive transistor, wherein:
the data reading circuit is used for reading the grid potential of the corresponding driving transistor, and the grid potential comprises the threshold voltage and the data signal of the driving transistor;
the signal processor is used for determining compensation data of other display panels except for the reference display panel in the plurality of display panels according to the grid potential, compensating data signals of the other display panels according to the compensation data, and obtaining compensated data signals so that the other display panels display according to the compensated data signals;
wherein the signal processor is configured to:
determining a threshold voltage of the reference display panel, a data signal to be input to the reference display panel, and threshold voltages of the other display panels;
determining a ratio between transconductance of the reference display panel and transconductance of any display panel to be tested in the other display panels according to the threshold voltage of the reference display panel and the threshold voltages of the other display panels;
and determining compensation data for compensating the display panel to be detected according to the ratio and the data signal.
2. The display device according to claim 1, wherein the signal processor includes an analog-to-digital conversion circuit coupled to at least some of the plurality of pixel circuits, and a digital processing circuit coupled to the analog-to-digital conversion circuit, the analog-to-digital conversion circuit being configured to convert analog signals corresponding to the gate potentials obtained from the at least some of the pixel circuits into digital signals, and the digital processing circuit being configured to process the digital signals to determine the compensation data of the corresponding display panel.
3. The display device according to claim 2, wherein each of the display panels further comprises a display driver chip, the analog-to-digital conversion circuit and the digital processing circuit are integrated in the display driver chip, and the display driver chip is configured to control the corresponding display panel to display according to the compensated data signal.
4. The display device according to claim 2, wherein each of the display panels further includes a display driver chip, the analog-to-digital conversion circuit and the digital processing circuit are provided independently of the display driver chip, and wherein the display driver chip and the digital processing circuit are coupled by a MIPI bus.
5. The display device according to any one of claims 2-4, wherein the data reading circuit comprises a first transistor, a gate of the first transistor is coupled to a read control terminal, a first pole of the first transistor is coupled to the corresponding analog-to-digital conversion circuit, and a second pole of the first transistor is coupled to a gate of the driving transistor.
6. The method for driving a display device according to any one of claims 1 to 5, comprising:
reading, by the data reading circuit, a gate potential of each driving transistor in at least a part of pixel circuits of each of the plurality of display panels;
processing the grid potential through the signal processor, determining compensation data of other display panels except for a reference display panel in the plurality of display panels, and compensating data signals of the other display panels according to the compensation data to obtain compensated data signals so that the other display panels display according to the compensated data signals;
wherein the determining, by the signal processor, the compensation data for the other display panels of the plurality of display panels except the reference display panel includes:
determining a threshold voltage of the reference display panel, a data signal to be input to the reference display panel, and threshold voltages of the other display panels;
determining a ratio between transconductance of the reference display panel and transconductance of any display panel to be tested in the other display panels according to the threshold voltage of the reference display panel and the threshold voltages of the other display panels;
and determining compensation data for compensating the display panel to be detected according to the ratio and the data signal.
7. The driving method according to claim 6, wherein the determining compensation data for the other display panels of the plurality of display panels except for the reference display panel by processing the gate potential by the signal processor comprises:
determining the threshold voltage of the driving transistor corresponding to at least part of the pixel circuits in each display panel according to the grid potential;
and determining an average value of the threshold voltages of the driving transistors corresponding to at least part of the pixel circuits, and taking the average value as the threshold voltage of the corresponding display panel.
8. The driving method as claimed in claim 6, wherein when each of the driving transistors operates in a linear region, a ratio between the transconductance of the reference display panel and the transconductance of any one of the other display panels to be tested is determined using the following formula:
V th1 representing the threshold voltage, V, of the reference display panel th2 Representing the threshold voltage, g, of the display panel under test m1 Representing the transconductance, g, of the reference display panel m2 Representing the transconductance, V, of the display panel under test DD Representing a constant potential.
9. The driving method as claimed in claim 8, wherein when each of the driving transistors operates in a saturation region, the compensation data for compensating the display panel to be tested is determined using the following formula:
wherein Δ V represents compensation data for compensating the display panel to be measured.
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