CN113514991A

CN113514991A - Array substrate and liquid crystal display panel

Info

Publication number: CN113514991A
Application number: CN202110369121.3A
Authority: CN
Inventors: 唐汉庭
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-04-06
Filing date: 2021-04-06
Publication date: 2021-10-19
Anticipated expiration: 2041-04-06
Also published as: CN113514991B

Abstract

The application provides an array substrate and a liquid crystal display panel. The array substrate comprises a substrate, a metal electrode layer, an insulating layer and a pixel electrode. The metal electrode layer is arranged on the substrate. The metal electrode layer includes a protrusion. The insulating layer covers one surface of the metal electrode layer, which is far away from the substrate. A via hole is opened in the insulating layer. The via hole exposes the boss. The pixel electrode is arranged on one side of the insulating layer far away from the metal electrode layer. The pixel electrode extends into the through hole and is electrically connected with the bulge. The application provides an array substrate and liquid crystal display panel can eliminate twill mura.

Description

Array substrate and liquid crystal display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate and a liquid crystal display panel.

Background

A Liquid Crystal Display (LCD) is a flat panel Display having a wide range of applications. The liquid crystal display realizes picture display mainly by modulating the light field intensity of the backlight source through the liquid crystal switch. Generally, a via hole is formed in an array substrate of a liquid crystal display to electrically connect a pixel electrode and a metal electrode layer under the pixel electrode. Some liquid crystal displays have a diagonal brightness unevenness (mura) observed at a position near the via hole after lighting for 10 to 15 minutes.

Disclosure of Invention

In view of the above, the present disclosure is directed to an array substrate and a liquid crystal display panel capable of eliminating diagonal mura near vias.

The application provides an array substrate, it includes: a substrate; a metal electrode layer disposed on the substrate, the metal electrode layer including a protrusion; the insulating layer covers one surface, far away from the substrate, of the metal electrode layer, a through hole is formed in the insulating layer, and the through hole exposes out of the protruding portion; the pixel electrode is arranged on one side, far away from the metal electrode layer, of the insulating layer, and extends into the through hole to be electrically connected with the protruding portion.

In one embodiment, the metal electrode layer includes a source electrode and a drain electrode, the source electrode and the drain electrode are both disposed on the substrate, the drain electrode is connected to the protrusion, and the source electrode is located on a side of the drain electrode away from the protrusion.

In one embodiment, the array substrate further includes an alignment film, and the alignment film covers a surface of the pixel electrode away from the substrate and is filled in the via hole.

In one embodiment, the insulating layer includes a color film layer and a planarization layer, the color film layer is located on a side of the drain electrode away from the substrate, and the planarization layer is located on a side of the color film layer away from the drain electrode.

In one embodiment, the surface of the protrusion portion away from the substrate is higher than the surface of the color film layer close to the substrate, and is level with or lower than the surface of the color film layer away from the substrate.

In one embodiment, the surface of the protrusion portion away from the substrate is higher than the surface of the color film layer away from the substrate, and the surface of the protrusion portion away from the substrate is lower than the surface of the planarization layer away from the substrate.

In one embodiment, the array substrate further includes a bump located on one side of the metal electrode layer close to the substrate and located right below the protruding portion.

In one embodiment, the array substrate further includes an active layer located on a side of the metal electrode layer close to the substrate, and the bump is disposed on the same layer as the active layer.

In an embodiment, the array substrate further includes a gate, the gate is located on one side of the metal electrode layer close to the substrate, and the bump and the gate are disposed on the same layer.

In an embodiment, the array substrate further includes an active layer and a light-shielding layer, the active layer is located on one side of the metal electrode layer close to the substrate, the light-shielding layer is located on one side of the active layer close to the substrate, and the bump and the light-shielding layer are disposed on the same layer.

The application also provides a liquid crystal display panel, which comprises the array substrate.

The application provides an array substrate and a liquid crystal display panel. The array substrate comprises a substrate, a metal electrode layer, an insulating layer and a pixel electrode. The metal electrode layer is arranged on the substrate. The metal electrode layer includes a protrusion. The insulating layer covers one surface of the metal electrode layer, which is far away from the substrate. A via hole is opened in the insulating layer. The via hole exposes the boss. The pixel electrode is arranged on one side of the insulating layer far away from the metal electrode layer. The pixel electrode extends into the through hole and is electrically connected with the bulge.

The application provides an array substrate and liquid crystal display panel, through form the bellying on the metal electrode layer of being connected with the pixel electrode electricity, reduce the distance between pixel electrode and the metal electrode layer, thereby reduce the via hole degree of depth, reduce the taper angle of via hole department simultaneously, in forming the process to the orientation membrane, make to the orientation membrane can flow into the via hole smoothly, the rete below the pixel electrode is ageing because lighting a lamp, when the ion is appeared, the orientation membrane can play the barrier effect, prevent the ion gathering, eliminate twill mura.

Drawings

In order to more clearly illustrate the technical solutions in the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1(a) to 1(c) are schematic diagrams illustrating a diagonal mura generated near a via hole of a liquid crystal display panel in the prior art.

Fig. 2 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present application.

Fig. 3 is a partial cross-sectional view of the array substrate of the liquid crystal display panel of fig. 2.

Fig. 4 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to another embodiment of the present disclosure.

Fig. 5 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present application.

Fig. 6 is a schematic partial cross-sectional view of a liquid crystal display panel according to still another embodiment of the present application.

Fig. 7 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present application.

Fig. 8 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present application.

Fig. 9 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present application.

Detailed Description

The technical solution in the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application, are within the scope of protection of the present application.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being directly adjacent or may comprise the first and second features being not in direct contact but in contact with each other by means of further features between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The inventor researches the reason of the diagonal mura generated near the via hole of the liquid crystal display panel in the prior art. The research shows that: in these Thin Film Transistor Liquid Crystal displays (TFT-LCDs) in which diagonal mura occurs, there are cases where an alignment Film is not successfully applied at via holes electrically connecting a pixel electrode and a metal electrode layer under the pixel electrode. Referring to fig. 1(a) to 1(c), fig. 1(a) to 1(c) are schematic diagrams illustrating a diagonal mura generated near a via hole of a liquid crystal display panel in the prior art. As shown in fig. 1(a), the liquid crystal display panel 200 includes a color filter substrate 200a and an array substrate 200b disposed opposite to each other, and a liquid crystal 200c disposed between the color filter substrate 200a and the array substrate 200 b. The array substrate 200b includes a metal electrode layer 201, an insulating layer 202, a pixel electrode layer 203, and an alignment film 204. The insulating layer 202 covers the metal electrode layer 201. A VIA is opened in the insulating layer 202. The pixel electrode layer 203 covers the insulating layer 202 at a side away from the metal electrode layer 201, and extends into the VIA to be electrically connected to the metal electrode layer 201. The material of the pixel electrode layer 203 is typically Indium Tin Oxide (ITO). In the coating process of the alignment film 204 of the TFT-LCD, the alignment film material is difficult to enter the VIA hole VIA due to the large depth of the VIA hole VIA and the large taper angle (taper angle). After the liquid crystal display panel 200 is lit for a period of time, the film material under the ITO is aged and ions are precipitated. Since ITO has poor blocking capability, at the VIA not covered by the alignment film 204, the precipitated ions directly penetrate through the ITO layer and enter the liquid crystal 200c without being blocked by the alignment film 204. As shown in fig. 1(b), in the lighting process, among the ions separated out, positive ions are collected on the surface of the alignment film 204 around the VIA hole VIA of the color filter substrate 200a, and negative ions are collected on the surface of the alignment film 204 around the VIA hole VIA of the array substrate 200 b. As shown in fig. 1(c), after a period of time, a voltage difference is formed between the color filter substrate 200a and the array substrate 200b around the VIA hole VIA, and the liquid crystal 200c in this region is tilted by the voltage, and deviates from a predetermined tilt angle, thereby generating the twill mura.

To the above reason that produces twill mura, this application provides an array substrate and liquid crystal display panel. Referring to fig. 2, fig. 2 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present disclosure.

The liquid crystal display panel 100 provided by the present application can be used in electronic devices having a display function, such as a mobile phone, a tablet computer, a notebook computer, a game machine, a digital camera, a car navigation device, an electronic billboard, and an automatic teller machine.

In one embodiment, the lcd panel 100 may be a Polymer Stabilized Vertical Aligned (PSVA) type lcd panel. However, the present application does not limit the type of the liquid crystal display panel 100. The display type of the liquid crystal display panel 100 provided In the present application may be a horizontal electric Field type, such as Fringe Field Switching (FFS) type or In-Plane Switching (IPS) type, or a Vertical electric Field type, such as Twisted Nematic (TN) type or Multi-domain Vertical Alignment (MVA) type.

The liquid crystal display panel 100 includes an array substrate 10, an opposite substrate 20, and a liquid crystal layer 30. The array substrate 10 and the opposite substrate 20 are disposed opposite to each other. The liquid crystal layer 30 is disposed between the array substrate 10 and the opposite substrate 20. It is understood that the liquid crystal display panel 100 may further include other display components not mentioned, such as a frame sealing adhesive.

Referring to fig. 3, fig. 3 is a partial cross-sectional view of the array substrate of the liquid crystal display panel of fig. 2. In the present embodiment, the array substrate 10 is a coa (color Filter On array) type array substrate. The array substrate 10 includes: a first substrate 11, a metal electrode layer 12, an insulating layer 13, a pixel electrode 14, and an alignment film 15. A metal electrode layer 12, an insulating layer 13, a pixel electrode 14, and an alignment film 15 are sequentially stacked on the first substrate 11.

The first substrate 11 is used to support other display function layers on the array substrate 10. The material of the first substrate 11 may be glass or plastic, etc.

The metal electrode layer 12 is disposed on the first substrate 11. In one embodiment, the metal electrode layer 12 is a drain metal layer. That is, the metal electrode layer 12 includes the drain electrode DE. Specifically, the array substrate 10 includes a thin film transistor T. In this embodiment mode, the thin film transistor T is a bottom gate thin film transistor. The thin film transistor T includes a gate electrode GE, an active layer CL, a source electrode SE, and a drain electrode DE, which are sequentially stacked. Specifically, the gate electrode GE is disposed on the first substrate 11. The active layer CL is located on a side of the gate electrode GE away from the first substrate 11. The active layer CL is disposed corresponding to the gate electrode GE. The source electrode SE and the drain electrode DE are located on a side of the active layer CL away from the gate electrode GE, and are respectively connected to both ends of the active layer CL. It is understood that a gate insulating layer GI is further disposed between the gate electrode GE and the active layer CL. The structure of the thin film transistor is not limited in the present application, and the thin film transistor may be a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor.

The gate electrode GE, the source electrode SE, and the drain electrode DE may be made of tantalum, tungsten, molybdenum, aluminum, titanium, a copper-niobium alloy, or the like, or may be made of a stack of copper and molybdenum, a stack of copper and a molybdenum-titanium alloy, a stack of copper and titanium, a stack of aluminum and molybdenum, a stack of molybdenum and tantalum, a stack of molybdenum and tungsten, and a stack of molybdenum-aluminum-molybdenum.

The material of the active layer CL may be single crystal silicon, low temperature polysilicon, or an oxide semiconductor material. The oxide semiconductor material may be selected from one of Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Zinc Oxide (IZO), gallium indium oxide (IGO), Indium Gallium Tin Oxide (IGTO), Indium Zinc Tin Oxide (IZTO), indium tin oxide.

It is to be understood that the metal electrode layer 12 of the present application is not limited to the drain metal layer. In other embodiments of the present application, the metal electrode layer 12 may further include other components electrically connected to the pixel electrode 14 through the VIA. The technical scheme of the application can be used in the array substrate and the liquid crystal display panel which are not successfully coated with the alignment film material due to the formation of the VIA hole VIA.

The metal electrode layer 12 includes a convex portion 121. The projection 121 is used to electrically connect with the pixel electrode 14. In the present embodiment, the protrusion 121 is located on a side of the drain DE away from the source SE and connected to the drain DE. In one embodiment, the protrusion 121 and the drain electrode DE are formed in the same process through the same metal layer. Specifically, the same metal layer may be exposed using a half-tone mask or a gray-scale mask, and developed and etched to form the protrusion 121 and the drain electrode DE having different thicknesses. Specifically, the thickness of the protrusion 121 is greater than that of the drain electrode DE.

The insulating layer 13 covers a surface of the metal electrode layer 12 away from the first substrate 11. Specifically, the insulating layer 13 covers a side of the drain electrode DE away from the first substrate 11. A via 130a is opened in the insulating layer 13. The via hole 130a exposes the protrusion 121.

In one embodiment, the insulating layer 13 includes a color film layer 131 and a planarization layer 132. The color film layer 131 is located on the side of the drain electrode DE away from the first substrate 11. The planarization layer 132 is located on the side of the color film layer 131 away from the drain electrode DE. The planarization layer 132 may be an Array substrate side organic Film (PFA). The array substrate side organic film can change the flatness of the surface of the lower film and prevent electric fields from interfering with each other, so that the display Mura of the liquid crystal display device caused by topographic factors can be effectively improved, the parasitic capacitance is reduced, display abnormalities such as flicker caused by overlarge electric load (RC loading) are reduced, and the quality of the display device is improved. The material of the array substrate side organic film is an organic material. The color film layer 131 includes a plurality of color filters arranged in an array. The plurality of color filters may be a red filter, a blue filter, and a green filter.

In one embodiment, the surface of the protrusion 121 away from the first substrate 11 is higher than the surface of the color film layer 131 close to the first substrate 11, and is flush with the surface of the color film layer 131 away from the first substrate 11.

Referring to fig. 4, fig. 4 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to another embodiment of the present disclosure. In the embodiment of fig. 4, the surface of the protrusion portion 121 away from the first substrate 11 is higher than the surface of the color film layer 131 close to the first substrate 11, and is lower than the surface of the color film layer 131 away from the first substrate 11.

Referring to fig. 5, fig. 5 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present disclosure. In the embodiment of fig. 5, the surface of the protrusion portion 121 away from the first substrate 11 is higher than the surface of the color film layer 131 away from the first substrate 11 and lower than the surface of the planarization layer 132 away from the first substrate 11.

The array substrate 10 may further include a passivation layer PV. The passivation layer PV covers the surface of the drain electrode DE remote from the first substrate 11, and functions as a planarization layer. In one embodiment, the thickness of the pixel electrode 14 is about 0.06 micrometers, the thickness of the color-resisting layer 131 is in a range from 2.4 micrometers to 2.6 micrometers, the thickness of the planarization layer 132 is 1.3 micrometers, and the surface of the protrusion 121 away from the substrate 11 is at least higher than the surface of the passivation layer PV away from the substrate 11. Thereby, the depth of the via hole 121a, and the size of the taper angle are reduced, so that the alignment film material flows into the via hole 121 a.

The pixel electrode 14 is disposed on a side of the insulating layer 13 away from the metal electrode layer 12. The pixel electrode 14 extends into the via hole 130a to be electrically connected to the protrusion 121. The material of the pixel electrode 14 may be a transparent oxide material, such as indium tin oxide.

The alignment film 15 covers a surface of the pixel electrode 14 away from the substrate 11 and is filled in the via hole 130 a. The material of the alignment film 15 may be polyimide.

The opposite substrate 20 includes a second substrate and a black matrix layer (not shown). The black matrix layer is disposed on one side of the second substrate close to the array substrate 10. The black matrix layer includes a plurality of black matrices. Each black matrix is disposed corresponding to a gap between adjacent color filters.

Referring to fig. 6, fig. 6 is a schematic partial cross-sectional view of a liquid crystal display panel according to still another embodiment of the present disclosure. In the embodiment of the present invention, the protrusion 121 is formed on the metal electrode layer 12 connected to the pixel electrode 14, so that the distance between the pixel electrode 14 and the metal electrode layer 12 is reduced, thereby reducing the depth of the via hole 130a, and reducing the taper angle at the via hole 130a, so that the alignment film 15 can smoothly flow into the via hole 130a in the alignment film forming process, and when the film layer below the pixel electrode 14 is aged by lighting to precipitate ions, the alignment film 15 can play a role of blocking, thereby preventing the ion accumulation and eliminating the twill mura.

It is understood that, in other embodiments of the present disclosure, the opposite substrate 20 may also be a color film substrate, and the color film layer is located on the opposite substrate 20. The surface of the protrusion 121 away from the first substrate 11 is higher than the surface of the planarization layer 132 away from the first substrate 11 and lower than the surface of the planarization layer 132 away from the first substrate 11.

Referring to fig. 7, fig. 7 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present disclosure. The liquid crystal display panel 100 of the present embodiment is different from the liquid crystal display panel 100 of the embodiment shown in fig. 1 in that:

the array substrate 10 further includes bumps 17. The bump 17 is located on one side of the metal electrode layer 12 close to the first substrate 11 and is located right below the protrusion 121. The convex portion 121 may be formed by covering the metal electrode layer 12 on the bump 17.

In the present embodiment, the bump 17 is provided in the same layer as the active layer CL. That is, the bump 17 and the active layer CL are formed on the gate insulating layer GI. The bump 17 may be made of the same material as the active layer CL in the same process. The height of the bump 17 is greater than the height of the active layer CL. The bump 17 is in direct contact with the metal electrode layer 12. The metal electrode layer 12 covers the bump 17 and the active layer CL at the same time. Since the height of the bump 17 is greater than that of the active layer CL, the height of the metal electrode layer 12 covering the bump 17 with respect to the gate insulating layer GI is greater than that of the drain electrode DE covering the active layer CL and connected to the active layer CL, thereby forming the protrusion 121 of the metal electrode layer 12. This reduces the distance between the pixel electrode 14 and the metal electrode layer 12, thereby reducing the depth of the via hole 130a, and also reducing the taper angle at the via hole 130a, so that the alignment film 15 can smoothly flow into the via hole 130a in the alignment film forming process, and when the film layer below the pixel electrode 14 is aged by lighting and ions are precipitated, the alignment film 15 can play a role of blocking, thereby preventing the aggregation of ions and eliminating the twill mura.

Referring to fig. 8, fig. 8 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present disclosure. The liquid crystal display panel 100 of the present embodiment differs from the liquid crystal display panel 100 of the embodiment shown in fig. 7 in that:

the bump 17 is disposed on the same layer as the gate GE. That is, the bump 17 and the gate electrode GE are formed on the substrate 11. The bump 17 and the gate GE may be made of the same material and in the same process. The height of the bump 17 is greater than the sum of the height of the gate electrode GE and the height of the active layer CL. The side of the bump 17 close to the metal electrode layer 12 is covered with a passivation layer PV. The metal electrode layer covers the passivation layer PV, the bump 17, and the active layer CL at the same time. Since the height of the bump 17 is greater than the sum of the height of the gate electrode GE and the height of the active layer CL, the height of the metal electrode layer 12 covering the bump 17 with respect to the gate insulating layer GI is greater than the height of the drain electrode DE covering the active layer CL and connected to the active layer CL, thereby forming the protrusion 121 of the metal electrode layer 12. This reduces the distance between the pixel electrode 14 and the metal electrode layer 12, thereby reducing the depth of the via hole 130a, and also reducing the taper angle at the via hole 130a, so that the alignment film 15 can smoothly flow into the via hole 130a in the alignment film forming process, and when the film layer below the pixel electrode 14 is aged by lighting and ions are precipitated, the alignment film 15 can play a role of blocking, thereby preventing the aggregation of ions and eliminating the twill mura.

Referring to fig. 9, fig. 9 is a schematic partial cross-sectional view of an array substrate of a liquid crystal display panel according to still another embodiment of the present disclosure. The liquid crystal display panel 100 of the present embodiment differs from the liquid crystal display panel 100 of the embodiment shown in fig. 7 in that:

the array substrate 10 further includes a light-shielding layer SL. The light-shielding layer SL is located on the side of the active layer CL close to the substrate 11. The bump 17 is provided in the same layer as the light-shielding layer SL. That is, the bump 17 and the light-shielding layer SL are formed on the substrate 11. The bump 17 may be made of the same material as the light-shielding layer SL in the same process. The height of the bump 17 is greater than the sum of the height of the light-shielding layer SL, the height of the gate electrode GE and the height of the active layer CL. The side of the bump 17 near the gate GE is covered with a buffer layer BL. The side of the buffer layer BL adjacent to the metal electrode layer 12 is covered with a passivation layer PV. The metal electrode layer 12 covers the passivation layer PV, the bump 17, and the active layer CL at the same time. Since the height of the bump 17 is greater than the sum of the height of the light-shielding layer SL, the height of the gate electrode GE, and the height of the active layer CL, the height of the metal electrode layer 12 covering the bump 17 with respect to the gate insulating layer GI is greater than the height of the drain electrode DE covering the active layer CL and connected to the active layer CL, thereby forming the protrusion 121 of the metal electrode layer 12. This reduces the distance between the pixel electrode 14 and the metal electrode layer 12, thereby reducing the depth of the via hole 130a, and also reducing the taper angle at the via hole 130a, so that the alignment film 15 can smoothly flow into the via hole 130a in the alignment film forming process, and when the film layer below the pixel electrode 14 is aged by lighting and ions are precipitated, the alignment film 15 can play a role of blocking, thereby preventing the aggregation of ions and eliminating the twill mura.

The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, comprising:

a substrate;

a metal electrode layer disposed on the substrate, the metal electrode layer including a protrusion;

the insulating layer covers one surface, far away from the substrate, of the metal electrode layer, a through hole is formed in the insulating layer, and the through hole exposes out of the protruding portion;

the pixel electrode is arranged on one side, far away from the metal electrode layer, of the insulating layer, and extends into the through hole to be electrically connected with the protruding portion.

2. The array substrate of claim 1, wherein the metal electrode layer comprises a source electrode and a drain electrode, the source electrode and the drain electrode are both disposed on the substrate, the drain electrode is connected to the protrusion, and the source electrode is located on a side of the drain electrode away from the protrusion.

3. The array substrate of claim 2, further comprising an alignment film covering a side of the pixel electrode away from the substrate and filling the via hole.

4. The array substrate of claim 3, wherein the insulating layer comprises a color film layer and a planarization layer, the color film layer is located on the side of the drain electrode away from the substrate, and the planarization layer is located on the side of the color film layer away from the drain electrode.

5. The array substrate of claim 4, wherein the surface of the protrusion portion away from the substrate is higher than the surface of the color film layer close to the substrate, and is equal to or lower than the surface of the color film layer away from the substrate.

6. The array substrate of claim 4, wherein a surface of the protrusion portion away from the substrate is higher than a surface of the color film layer away from the substrate, and the surface of the protrusion portion away from the substrate is lower than a surface of the planarization layer away from the substrate.

7. The array substrate of claim 1, wherein the array substrate further comprises a bump, and the bump is located on one side of the metal electrode layer close to the substrate and is located right below the protruding portion.

8. The array substrate of claim 7, further comprising an active layer on a side of the metal electrode layer adjacent to the substrate, wherein the bump is disposed on a same layer as the active layer.

9. The array substrate of claim 7, further comprising a gate on a side of the metal electrode layer adjacent to the substrate, wherein the bump is disposed on a same layer as the gate.

10. The array substrate of claim 7, further comprising an active layer and a light-shielding layer, wherein the active layer is located on a side of the metal electrode layer close to the substrate, the light-shielding layer is located on a side of the active layer close to the substrate, and the bump and the light-shielding layer are disposed on the same layer.

11. A liquid crystal display panel comprising the array substrate according to any one of claims 1 to 10.