CN113507357B - Realization method and circuit module compatible with SM4 and AES algorithm S box - Google Patents
Realization method and circuit module compatible with SM4 and AES algorithm S box Download PDFInfo
- Publication number
- CN113507357B CN113507357B CN202110774994.2A CN202110774994A CN113507357B CN 113507357 B CN113507357 B CN 113507357B CN 202110774994 A CN202110774994 A CN 202110774994A CN 113507357 B CN113507357 B CN 113507357B
- Authority
- CN
- China
- Prior art keywords
- box
- aes
- linear transformation
- auxiliary
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention provides an implementation method and a circuit module of an S box compatible with SM4 and AES algorithm. It includes: designing an auxiliary S-box S for obtaining two algorithms to shareAssistance of(x)=A1•x‑1+a1(ii) a The input data x is divided into two paths: the first path of data x is firstly subjected to linear transformation TSM4(x) = A.x + a, followed by TSM4(x) Performing an auxiliary S-box operation SSM4(x)=SAssistance of(x)TSM4(x) Thereby obtaining S box SSM4(x)=A1(A•x+a)‑1+a1(ii) a The second path of data x is directly subjected to auxiliary S box operation SAES assistance(x)=A1•x‑1+a1Then subsequently adding SAES assistance(x) Performing a linear transformation TAES(x) = Bx + b, thereby obtaining S-box SAES(x)=B1 x‑1+b1Wherein B is1=BA1，b1=Ba1。
Description
Technical Field
The invention relates to the field of encryption algorithms, in particular to a realization method and a circuit module of an S box compatible with SM4 and AES algorithm.
Background
In the cryptology community, AES was designed by the belgium cryptologists Joan Daemen and Vincent Rijmen, and was soon used worldwide instead of DES as an advanced encryption standard. The SM4 algorithm is determined as a national password industry standard by the national commercial password administration in 2012, and also has an important position in the password industry in China. Therefore, two mainstream block encryption algorithms are simultaneously required and supported by most cipher safety application manufacturers in the cipher industry at the present stage, while the S box is used as the only nonlinear operation of the block encryption, which determines the safety of the algorithm to a great extent, and simultaneously, because the expressions of the S boxes of the two block algorithms are completely different, the expression of the S box of the AES is SAES(x)＝B1·x-1+b1The S-box expression of SM4 is SSM4(x)＝A2(A·x+b2)-1+b2How to realize different S boxes uniformly to avoid repeated logic and achieve better time sequence and performance requirements becomesThe key and the difficulty in realizing the password security chip are realized.
Disclosure of Invention
In order to solve the technical problem, the invention finds a mode that only two linear transformations and one auxiliary S box are needed by starting from the structural characteristics of two S box expressions (both based on finite field inverse operation and linear operation), through application implementation and final simulation verification, so that the S boxes of AES and SM4 are obtained simultaneously, and the requirement that two different S boxes are used simultaneously in the implementation of simultaneously supporting AES and SM4 encryption is replaced, thereby greatly reducing the cost of chip implementation.
Specifically, the technical scheme of the invention discloses a realization method of an S box compatible with SM4 and AES algorithm, which comprises the following steps:
designing to obtain an auxiliary S-box S for SM4 and AES algorithm sharingAssistance of(x)＝A1·x-1+a1；
The input data x is divided into two paths: a first path of input data x and a second path of input data x, wherein,
the first path of input data x is firstly subjected to linear transformation TSM4(x) A x + a, and then linearly transforming the data TSM4(x) Performing an auxiliary S-box operation SSM4(x)＝SAssistance of(x)TSM4(x) Thus obtaining the S-box S of SM4SM4(x)＝A1(A·x+a)-1+a1，
Directly carrying out auxiliary S box operation S on the second path of input data xAES assistance(x)＝A1·x-1+a1Subsequently the data S subjected to the auxiliary S-box operationAES assistance(x) Performing a linear transformation TAES(x) Bx + b, to obtain the S-box S of AESAES(x)＝B1x-1+b1Wherein B is1＝BA1，b1＝Ba1。
In a further aspect, the auxiliary S-box is a 256 byte lookup table.
In a further aspect, the auxiliary S-box is defined as a look-up table as follows:
in a further embodiment, T is linearly transformedSM4(x) The matrix a and the constant matrix a are defined as:
linear transformation TAES(x) The matrix B and the constant matrix B are defined as:
in a further aspect, the linearly transformed data T is selected as desiredSM4(x) Or the second path of input data x is used for carrying out auxiliary S box operation, and the S box S is selected according to the requirementSM4(x)＝A1(A·x+a)-1+a1Or S box SAES(x)＝B1x-1+b1S-boxes as final outputs.
In a further aspect, the linearly transformed data T is selected when an S-box of SM4 needs to be obtainedSM4(x) Performing an auxiliary S-box operation SSM4(x)＝SAssistance of(x)TSM4(x) And select S box SSM4(x)＝A1(A·x+a)-1+a1S-boxes as final outputs; when an S box of the AES needs to be obtained, selecting the second path of input data x to perform auxiliary S box operation SAES assistance(x)＝A1·x-1+a1And select S box SAES(x)＝B1x-1+b1S-boxes as final outputs.
The invention also discloses a circuit module compatible with the SM4 and the AES algorithm S box, which is used for realizing the method.
The invention also discloses a circuit module compatible with the SM4 and AES algorithm S box, which comprises: a first linear transformation unit, a first selector, an auxiliary S box operation unit, a second linear transformation unit, a second selector and a data input port, wherein the first linear transformation unit is used for realizing linear transformation TSM4(x) A second linear transformation unit for implementing a linear transformation TAES(x) -Bx + b, said auxiliary S-box arithmetic unit for implementing an operation SAssistance of(x)＝A1·x-1+a1The data input port is connected to the input port of the first linear transformation unit and one input end of the first selector, the output port of the first linear transformation unit is connected to the other input end of the first selector, the output port of the first selector is connected to the input port of the auxiliary S-box arithmetic unit, the output port of the auxiliary S-box arithmetic unit is connected to the input port of the second linear transformation unit and one input end of the second selector, and the output port of the second linear transformation unit is connected to the other input end of the second selector.
In a further technical solution, the first linear transformation unit and the second linear transformation unit are both operation array units composed of exclusive or gates and not gates.
In a further technical solution, the auxiliary S-box unit includes a lookup table of 256 bytes and a decoder, where the decoder has access to the lookup table, an output of the first selector is connected to an input of the decoder, and an output of the decoder is connected to an input port of the second linear transform and an input of the second selector, respectively.
The invention provides a hardware implementation mode of the S box which can be compatible with AES and SM4 simultaneously, namely the S boxes of AES and SM4 can be obtained simultaneously only by two linear transformations and one auxiliary S box, so that the area for realizing the chip is greatly saved, and the hardware implementation mode is simpler than other unified implementation modes and has better time sequence and performance.
Drawings
Fig. 1 is a schematic diagram of an implementation of the compatible SM4 and AES algorithm S-box of the present invention;
FIG. 2 is a schematic diagram of the structure of the circuit module compatible with SM4 and the S-box of the AES algorithm of the present invention;
fig. 3 is a hardware configuration diagram of a circuit block compatible with SM4 and the AES algorithm S-box of the present invention.
Detailed Description
The technical solution of the present invention will be further described with reference to the following specific examples, but the present invention is not limited to these examples.
Before explaining the technical scheme of the present invention, the following explanation is made on the related nouns or operation symbols.
(1) Noun interpretation
Aes (advanced Encryption standard): advanced encryption standard, a block encryption algorithm;
SM 4: a block encryption algorithm used in the china wireless standard;
and S, box: a block cipher look-up table constructed using a non-linear transformation;
(2) mathematical operations and definitions:
x-1: finite field F2 8The multiplication inversion operation of (1);
A、B、A1、B1: 8 × 8 2-ary matrix;
A、b、a1、b1: 8 x 1 binary matrix.
In the invention, an implementation mode of the S box which is compatible with AES and SM4 simultaneously is provided through mathematical derivation and application implementation, so that the S boxes of AES and SM4 can be obtained simultaneously only by two linear transformations and one auxiliary S box, the chip cost is greatly reduced, and the performance of an encryption algorithm is improved.
The mathematical derivation process:
the expression of S-box for SM4 is:
SSM4(x)＝A1(A·x+a)-1+a1，
definition of assumptions
SAssistance of(x)＝A1·x-1+a1，
Wherein A is1Is a reversible matrix, SAssistance of(x) For a linear operation and a finite field inversion, then
SSM4(x)＝SAssistance of(A·x+a)； (1)
The expression of the S-box of AES is
SAES(x)＝B1·x-1+b1,
Then
SAES(x)＝B1A1 -1(A1·x-1+a-a)+b1
＝B1A1 -1SAssistance of(x)+(b1-B1A2 -1a)；
Let B be B1A1 -1，b＝(b1-B1A1 -1a) Then, there are:
SAES(x)＝BSassistance of(x)+b。 (2)
It can be seen from the above formula derivation that in expressions (1) and (2) of S-boxes of SM4 and AES, by introducing an auxiliary S-box SAssistance of(x)＝A1·x-1+a1And the S boxes of the SM4 and the AES can share the auxiliary S box, so that only two linear transformation units and one auxiliary S box operation unit are needed when hardware is implemented, the chip cost is greatly reduced, and the performance of an encryption algorithm is improved.
In the specific implementation of the present invention, referring to fig. 1, an implementation method of an S-box compatible with SM4 and AES algorithm is disclosed, which includes the following steps:
designing to obtain an auxiliary S-box S for SM4 and AES algorithm sharingAssistance of(x)＝A1·x-1+a1；
The input data x (an 8 x 1 matrix) is divided into two paths: a first path of input data x and a second path of input data x, wherein,
the first path of input data x is firstly subjected to linear transformation TSM4(x) A x + a, and then linearly transforming the data TSM4(x) Performing an auxiliary S-box operation SSM4(x)＝SAssistance of(x)TSM4(x) Thus obtaining the S-box S of SM4SM4(x)＝A1(A·x+a)-1+a1，
Directly carrying out auxiliary S box operation S on the second path of input data xAES assistance(x)＝A1·x-1+a1Subsequently the data S subjected to the auxiliary S-box operationAES assistance(x) Performing a linear transformation TAES(x) Bx + b, to obtain the S-box S of AESAES(x)＝B1x-1+b1Wherein B is1＝BA1，b1＝Ba1。
In the above embodiment of the present invention, the auxiliary S-box S is introducedSM4(x)＝SAssistance of(x)TSM4(x) So that only two linear transforms and one auxiliary S-box are needed to implement the S-boxes of SM4 and AES simultaneously.
Regarding how the auxiliary S-box is implemented, the inversion operation and the linear transformation therein can be implemented in the form of hardware circuits, respectively, and in the present invention, in order to further simplify the hardware structure of the chip and reduce the implementation cost of the chip, the auxiliary S-box can be implemented by a 256-byte (i.e., 16 × 16) lookup table.
Therefore, the invention calculates the lookup table corresponding to the auxiliary S box as follows:
by implementing the auxiliary S-box with the help of the lookup table, the chip hardware structure and the chip cost in specific implementation are reduced.
Further, the above linear transformation T of the present inventionSM4(x) The matrix a and the constant matrix a are defined as:
linear transformation TAES(x) The matrix B and the constant matrix B are defined as:
in a further aspect, the linearly transformed data T may be selected as desiredSM4(x) Or the second path of input data x is used for carrying out auxiliary S box operation, and the S box S is selected according to the requirementSM4(x)＝A1(A·x+a)-1+a1Or S box SAES(x)＝B1x-1+b1S-boxes as final outputs.
In particular, the linearly transformed data T is selected when it is desired to obtain the S-box of SM4SM4(x) Performing an auxiliary S-box operation SSM4(x)＝SAssistance of(x)TSM4(x) And select S box SSM4(x)＝A1(A·x+a)-1+a1S-boxes as final outputs; when an S box of the AES needs to be obtained, selecting the second path of input data x to perform auxiliary S box operation SAES assistance(x)＝A1·x-1+a1And select S box SAES(x)＝B1x-1+b1S-boxes as final outputs.
In other embodiments of the present invention, a circuit module compatible with the SM4 and the AES algorithm S-box is also disclosed, which is used to implement the method as described above.
In other embodiments of the present invention, a circuit module compatible with SM4 and AES algorithm S-box is disclosed additionally, see fig. 2, which shows a corresponding schematic structural diagram, the circuit module comprising: a first linear transformation unit, a first selector, an auxiliary S box operation unit, a second linear transformation unit, a second selector and a data input port, wherein the first linear transformation unit is used for realizing linear transformation TSM4(x) A second linear transformation unit for implementing a linear transformation TAES(x) -Bx + b, said auxiliary S-box arithmetic unit for implementing an operation SAssistance of(x)＝A1·x-1+a1Wherein, in the step (A),
the data input port is connected with the input port of the first linear transformation unit and one input end of the first selector respectively, the output port of the first linear transformation unit is connected with the other input end of the first selector, the output end of the first selector is connected with the input port of the auxiliary S-box arithmetic unit, the output port of the auxiliary S-box arithmetic unit is connected with the input port of the second linear transformation and one input end of the second selector respectively, and the output port of the second linear transformation is connected with the other input end of the second selector.
In a specific embodiment, the first linear transformation unit and the second linear transformation unit can be respectively implemented by corresponding multipliers and adders, but preferably, in an embodiment of the present invention, for example, referring to fig. 3, the first linear transformation unit and the second linear transformation unit can be implemented by an operation array unit composed of an exclusive or gate and a not gate, thereby further simplifying a hardware structure of the circuit module and reducing the cost of the chip.
As mentioned above, the auxiliary S-box operation unit is preferably implemented in the form of a lookup table, and specifically, as shown in fig. 3, the auxiliary S-box operation unit may include a 256-byte lookup table and a decoder, wherein the decoder has access to the lookup table, an output terminal of the first selector is connected to an input terminal of the decoder, and an output terminal of the decoder is connected to an input terminal of the second linear transform and an input terminal of the second selector, respectively. It should be noted that the decoder herein is used to output the corresponding data of the lookup table, and the implementation manner is not particularly limited.
Fig. 3 is a specific hardware structure diagram of the structure shown in fig. 2, where a (0:7), B (0:7), C (0:7), and C (0) -C (7) in fig. 3 are only for convenience of showing the connection relationship of the corresponding lines, and have no actual physical meaning, and X (0) -X (7) represent eight-bit dataInputs, Y (0:7) represents data outputs, "Alg _ flg" and "non-Alg _ flg" represent control signals for the first and second selectors, respectively, "Assist SBOX"denotes a 256-byte (16 × 16) lookup table, which is specifically defined as follows:
in addition, in a specific example, the first selector and the second selector may be either selectors.
In a further embodiment of the present invention, there is also provided a chip including the circuit module as described above.
The invention has the beneficial technical effects that:
1. a hardware implementation mode of an S box which can be compatible with AES and SM4 is provided, namely the S boxes of AES and SM4 can be obtained simultaneously only by two linear transformations and one auxiliary S box, so that the area for realizing the chip is greatly saved, and the hardware implementation mode is simpler than other unified implementation modes and has better time sequence and performance;
the invention directly provides the lookup table of the auxiliary S box, and the lookup table can be directly applied to table lookup in specific application implementation and can be directly used similarly to the definitions of the S boxes of AES and SM 4.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (8)
1. An implementation method compatible with SM4 and AES algorithm S box is characterized by comprising the following steps:
designed to obtain sharing for SM4 and AES algorithmsAuxiliary S box SAssistance of(x)＝A1·x-1+a1；
The input data x is divided into two paths: a first path of input data x and a second path of input data x, wherein,
the first path of input data x is firstly subjected to linear transformation TSM4(x) A x + a, and then linearly transforming the data TSM4(x) Performing an auxiliary S-box operation SSM4(x)＝SAssistance of(x)TSM4(x) Thus obtaining the S-box S of SM4SM4(x)＝A1(A·x+a)-1+a1，
Directly carrying out auxiliary S box operation S on the second path of input data xAES assistance(x)＝A1·x-1+a1Subsequently the data S subjected to the auxiliary S-box operationAES assistance(x) Performing a linear transformation TAES(x) Bx + b, to obtain the S-box S of AESAES(x)＝B1x-1+b1Wherein B is1＝BA1，b1＝Ba1Wherein, in the step (A),
linear transformation TSM4(x) The matrix a and the constant matrix a are defined as:
linear transformation TAES(x) The matrix B and the constant matrix B are defined as:
2. the method of claim 1, wherein the auxiliary S-box is a 256 byte lookup table.
3. The method of claim 2, wherein the auxiliary S-box is defined as a look-up table as follows:
4. method according to claim 1, characterized in that said linearly transformed data T are selected as requiredSM4(x) Or the second path of input data x is used for carrying out auxiliary S box operation, and the S box S is selected according to the requirementSM4(x)＝A1(A·x+a)-1+a1Or S box SAES(x)＝B1x-1+b1S-boxes as final outputs.
5. The method of claim 4,
selecting the linearly transformed data T when it is desired to obtain an S-box of SM4SM4(x) Performing an auxiliary S-box operation SSM4(x)＝SAssistance of(x)TSM4(x) And select S box SSM4(x)＝A1(A·x+a)-1+a1S-boxes as final outputs;
when an S box of the AES needs to be obtained, selecting the second path of input data x to perform auxiliary S box operation SAES assistance(x)＝A1·x-1+a1And select S box SAES(x)＝B1x-1+b1S-boxes as final outputs.
6. A circuit module compatible with SM4 and AES algorithm S-box, for implementing the method of any of claims 1-5, the circuit module comprising: a first linear transformation unit, a first selector, an auxiliary S box operation unit, a second linear transformation unit, a second selector and a data input port, wherein the first linear transformation unit is used for realizing linear transformation TSM4(x) The second linear transformation unit is used for realizing Ax + aNow linear transformation TAES(x) -Bx + b, said auxiliary S-box arithmetic unit for implementing an operation SAssistance of(x)＝A1·x-1+a1Wherein, in the step (A),
the data input port is connected with the input port of the first linear transformation unit and one input end of the first selector respectively, the output port of the first linear transformation unit is connected with the other input end of the first selector, the output end of the first selector is connected with the input port of the auxiliary S-box arithmetic unit, the output port of the auxiliary S-box arithmetic unit is connected with the input port of the second linear transformation and one input end of the second selector respectively, and the output port of the second linear transformation is connected with the other input end of the second selector.
7. The circuit module according to claim 6, wherein the first linear transformation unit and the second linear transformation unit are each an operation array unit composed of an exclusive-or gate and a not gate.
8. The circuit module of claim 6, wherein the auxiliary S-box arithmetic unit comprises a 256-byte lookup table and a decoder, wherein the decoder has access to the lookup table, wherein an output of the first selector is connected to an input of the decoder, and wherein an output of the decoder is connected to an input port of the second linear transformation and an input of the second selector, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110774994.2A CN113507357B (en) | 2021-07-08 | 2021-07-08 | Realization method and circuit module compatible with SM4 and AES algorithm S box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110774994.2A CN113507357B (en) | 2021-07-08 | 2021-07-08 | Realization method and circuit module compatible with SM4 and AES algorithm S box |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113507357A CN113507357A (en) | 2021-10-15 |
| CN113507357B true CN113507357B (en) | 2022-03-11 |
Family
ID=78012272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110774994.2A Active CN113507357B (en) | 2021-07-08 | 2021-07-08 | Realization method and circuit module compatible with SM4 and AES algorithm S box |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113507357B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106921487A (en) * | 2017-03-01 | 2017-07-04 | 芜湖职业技术学院 | Reconfigurable S-box circuit structure |
| CN107181586A (en) * | 2017-05-22 | 2017-09-19 | 芜湖职业技术学院 | reconfigurable S-box circuit structure |
| CN107959565A (en) * | 2017-11-02 | 2018-04-24 | 北京中电华大电子设计有限责任公司 | A kind of implementation method of unified AES and SM4 S boxes |
| CN108650072A (en) * | 2018-03-28 | 2018-10-12 | 杭州朔天科技有限公司 | It is a kind of to support a variety of symmetric cryptographic algorithm chips and its anti-attack circuit implementation method |
| CN109417468A (en) * | 2017-04-12 | 2019-03-01 | 北京炼石网络技术有限公司 | The method and apparatus that safe and efficient block cipher is realized |
| EP3531401A1 (en) * | 2018-02-26 | 2019-08-28 | Stmicroelectronics (Rousset) Sas | Method and circuit for performing a substitution operation |
| CN111526003A (en) * | 2020-04-09 | 2020-08-11 | 北京理工大学 | Data encryption method and device, storage medium and electronic equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992852B (en) * | 2017-05-08 | 2023-09-15 | 芜湖职业技术学院 | Reconfigurable S-box circuit structure applied to AES and Camellia cryptographic algorithm |
| CN110474761A (en) * | 2019-07-11 | 2019-11-19 | 北京电子科技学院 | One kind 16 takes turns SM4-256 whitepack password implementation method |
| US11569980B2 (en) * | 2019-11-20 | 2023-01-31 | International Business Machines Corporation | Combined SBox and inverse SBox cryptography |
-
2021
- 2021-07-08 CN CN202110774994.2A patent/CN113507357B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106921487A (en) * | 2017-03-01 | 2017-07-04 | 芜湖职业技术学院 | Reconfigurable S-box circuit structure |
| CN109417468A (en) * | 2017-04-12 | 2019-03-01 | 北京炼石网络技术有限公司 | The method and apparatus that safe and efficient block cipher is realized |
| CN107181586A (en) * | 2017-05-22 | 2017-09-19 | 芜湖职业技术学院 | reconfigurable S-box circuit structure |
| CN107959565A (en) * | 2017-11-02 | 2018-04-24 | 北京中电华大电子设计有限责任公司 | A kind of implementation method of unified AES and SM4 S boxes |
| EP3531401A1 (en) * | 2018-02-26 | 2019-08-28 | Stmicroelectronics (Rousset) Sas | Method and circuit for performing a substitution operation |
| CN108650072A (en) * | 2018-03-28 | 2018-10-12 | 杭州朔天科技有限公司 | It is a kind of to support a variety of symmetric cryptographic algorithm chips and its anti-attack circuit implementation method |
| CN111526003A (en) * | 2020-04-09 | 2020-08-11 | 北京理工大学 | Data encryption method and device, storage medium and electronic equipment |
Non-Patent Citations (3)
| Title |
|---|
| A new compact hardware architecture of S-Box for block ciphers AES and SM4;Yaoping Liu等;《IEICE Electronics Express》;20170515;全文 * |
| Design of a Masked S-box for SM4 Based on Composite Field;Hao Liang等;《2014 Tenth International Conference on Computational Intelligence and Security》;20150122;全文 * |
| 基于高性能密码实现的大数据安全方案;杨国强等;《计算机研究与发展》;20191031;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113507357A (en) | 2021-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10050778B2 (en) | Method and apparatus for efficiently implementing the advanced encryption standard | |
| US7688974B2 (en) | Rijndael block cipher apparatus and encryption/decryption method thereof | |
| US7760870B2 (en) | Block cipher apparatus using auxiliary transformation | |
| US20060093136A1 (en) | Implementation of a switch-box using a subfield method | |
| CN107257279B (en) | Plaintext data encryption method and device | |
| CN104639314A (en) | Device based on AES (advanced encryption standard) encryption/decryption algorithm and pipelining control method | |
| CN102035641A (en) | Device and method for implementing AES encryption and decryption | |
| CN113078997B (en) | Terminal protection method based on lightweight cryptographic algorithm | |
| CN109033892B (en) | Round conversion multiplexing circuit based on synthetic matrix and AES decryption circuit | |
| CN112564890B (en) | Method, device, processor and electronic equipment for accelerating SM4 algorithm | |
| Arrag et al. | Design and Implementation A different Architectures of mixcolumn in FPGA | |
| CN113507357B (en) | Realization method and circuit module compatible with SM4 and AES algorithm S box | |
| CN114826558B (en) | Method and system for quickly encrypting mass data | |
| CN114826560B (en) | Lightweight block cipher CREF implementation method and system | |
| JP2006510067A (en) | Realization of small hardware for line doll sub-byte functions | |
| CN106452726B (en) | S-shaped box and construction method thereof | |
| EP4248433A1 (en) | High-speed circuit combining aes and sm4 encryption and decryption | |
| JP2005534973A (en) | Method and apparatus for manipulating data within a finite body | |
| US11750369B2 (en) | Circuit module of single round advanced encryption standard | |
| James et al. | An Optimized Parallel Mix column and Sub bytes’ design in Lightweight Advanced Encryption Standard | |
| JP7244060B2 (en) | Block cipher device, block cipher method and program | |
| CN112134691B (en) | NLCS block cipher realization method, device and medium with repeatable components | |
| KR100316024B1 (en) | Encryption device using data encryption standard algorithm | |
| Farmani et al. | A high performance hardware implementation image encryption with AES algorithm | |
| CN113922948B (en) | SM4 data encryption method and system based on composite domain round function |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |