CN113506802B - Direct band gap GeSn CMOS device and preparation method thereof - Google Patents

Direct band gap GeSn CMOS device and preparation method thereof Download PDF

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CN113506802B
CN113506802B CN202110722554.2A CN202110722554A CN113506802B CN 113506802 B CN113506802 B CN 113506802B CN 202110722554 A CN202110722554 A CN 202110722554A CN 113506802 B CN113506802 B CN 113506802B
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ternary alloy
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CN113506802A (en
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刘伟峰
张士琦
宋建军
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Wuhu Research Institute of Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8256—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252 and H01L21/8254

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Abstract

The invention discloses a direct band gap GeSn CMOS device, which comprises: the semiconductor device comprises a substrate layer, a Ge virtual substrate, a first P-type Ge layer, an isolation region, an N well, a second P-type Ge layer, an intrinsic Ge isolation layer, a channel layer, a first intrinsic ternary alloy heterogeneous cap layer, a PMOS gate, a PMOS source drain region, an N-type Ge layer, a second intrinsic ternary alloy heterogeneous cap layer, an NMOS gate, an NMOS source drain region, a dielectric layer, a source drain electrode and a passivation layer; the material of the first intrinsic ternary alloy heterogeneous cap layer is Si xGe1‑x‑ ySny; wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07; the material of the second intrinsic ternary alloy heterogeneous cap layer is Si xGe1‑x‑ySny; wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1; the channel layer is an intrinsic DR-Ge 1‑zSnz layer; wherein z ranges from 0.12 to 0.18. According to the invention, the DR-GeSn CMOS structure formed by the single-side high barrier quantum confinement NMOS and the quantum well PMOS can be beneficial to starting the channel of the NMOS device, the materials of all layers of the whole device are the same, and the NMOS and PMOS structures have better process compatibility. The invention also provides a preparation method of the direct band gap GeSn CMOS device.

Description

Direct band gap GeSn CMOS device and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a direct band gap GeSn CMOS device and a preparation method thereof.
Background
Microelectronics technology development has been following moore's law, but continuing moore's law is increasingly difficult as Si MOS device feature sizes continue to shrink. In this context, a series of new technologies such as strain technology, fin-gate FinFet, SOI, etc. are endless. However, even with these new technologies, si MOS device feature sizes have almost reached a limit (channel of only a few nanometers) and integrated circuits are approaching their physical and process limits. Therefore, instead of Si materials, developing and adopting new channel materials for MOS compatible with Si processes has become an important technological approach to continue moore's law.
Ge semiconductors, as well as modified Ge semiconductors (including strain-induced modified strained Ge, sn-alloyed modified direct bandgap GeSn) have significantly higher carrier mobility than Si semiconductors (where the direct bandgap GeSn electron mobility is about 4 times that of Si semiconductors, the former hole mobility is about twice that of the latter), and which can be epitaxially fabricated on Si substrates, compatible with Si processes, are ideal MOS channel materials. The Si material is replaced by the material, and the material is applied to a channel material of a MOS device, so that the Moore's law can be expected to be continued continuously, and the physical limit of the Si process is broken.
However, no matter the Ge semiconductor is used or the direct band gap GeSn (i.e., DR-GeSn) is used to make the channel material of the enhanced surface channel nMOS device, the fermi pinning effect caused by the interface state causes that the Ge-based enhanced surface channel nMOS device cannot be turned on inversely due to the poor interface characteristic between the gate dielectric and the P-type Ge-based semiconductor, and the compatible structure with the Ge-based PMOS cannot be considered, so that the performance of the Ge-based CMOS device is greatly limited.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a direct band gap GeSn CMOS device and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
A first aspect of an embodiment of the present invention provides a direct bandgap GeSn CMOS device comprising: the semiconductor device comprises a substrate layer, a Ge virtual substrate, a first P-type Ge layer, an isolation region, an N well, a second P-type Ge layer, an intrinsic Ge isolation layer, a channel layer, a first intrinsic ternary alloy heterogeneous cap layer, a PMOS gate electrode, a PMOS source drain region, an N-type Ge layer, a second intrinsic ternary alloy heterogeneous cap layer, an NMOS gate electrode, an NMOS source drain region, a dielectric layer, a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode and a passivation layer;
The substrate layer, the Ge virtual substrate and the first P-type Ge layer are sequentially arranged from bottom to top;
The N-type Ge layer and the second P-type Ge layer are both positioned on the upper layer of the first P-type Ge layer;
the N well is positioned in the first P-type Ge layer and below the second P-type Ge layer;
the intrinsic Ge isolation layer is positioned on the upper layers of the N-type Ge layer and the second P-type Ge layer;
The channel layer is positioned on the upper layer of the intrinsic Ge isolating layer;
the first intrinsic ternary alloy heterogeneous cap layer and the second intrinsic ternary alloy heterogeneous cap layer are both positioned on the upper layer of the channel layer;
The isolation region extends upwards from the first P-type Ge layer through the intrinsic Ge isolation layer and the channel layer to above the first and second intrinsic ternary alloy heterogeneous cap layers;
The N well, the second P-type Ge layer and the first intrinsic ternary alloy heterogeneous cap layer are positioned on one side of the isolation region;
the N-type Ge layer and the second intrinsic ternary alloy heterogeneous cap layer are positioned on the other side of the isolation region;
The PMOS source/drain region is positioned in the first intrinsic ternary alloy heterogeneous cap layer, the channel layer and the intrinsic Ge isolating layer;
The NMOS source/drain region is positioned in the second intrinsic ternary alloy heterogeneous cap layer, the channel layer and the intrinsic Ge isolating layer;
the PMOS grid electrode is positioned on the upper layer of the first intrinsic ternary alloy heterogeneous cap layer;
The NMOS grid electrode is positioned on the upper layer of the second intrinsic ternary alloy heterogeneous cap layer;
dielectric layers are covered on the PMOS grid electrode and the NMOS grid electrode;
The PMOS source electrode and the PMOS drain electrode are positioned on the dielectric layer and on one side of the isolation region and on two sides of the PMOS grid electrode respectively;
The NMOS source electrode and the NMOS drain electrode are positioned on the dielectric layer and on the other side of the isolation region and on the two sides of the NMOS grid electrode;
the medium layer, the PMOS source electrode, the PMOS drain electrode, the NMOS source electrode and the NMOS drain electrode are covered with the passivation layer;
The first intrinsic ternary alloy heterogeneous cap layer is made of Si xGe1-x-ySny; wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07;
The second intrinsic ternary alloy heterogeneous cap layer is made of Si xGe1-x-ySny; wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1;
The channel layer is an intrinsic DR-Ge 1-zSnz layer; wherein z ranges from 0.12 to 0.18.
A second aspect of the embodiments of the present invention provides a method for manufacturing a direct bandgap GeSn CMOS device, including the steps of:
Step 101, selecting a substrate: selecting single crystal Si as a substrate layer;
102, preparing a Ge virtual substrate by using a laser recrystallization method;
Step 103, depositing a first P-type Ge layer on the surface of the Ge virtual substrate;
Step 104, coating photoresist on the surface of the first P-type Ge layer, exposing the photoresist on one side area, and injecting P ions into the exposed area by utilizing an ion implantation process to form an N well;
step 105, removing the residual photoresist, and manufacturing an N-type Ge layer and a second P-type Ge layer on the surface;
Step 106, depositing an intrinsic Ge isolating layer on the surfaces of the N-type Ge layer and the second P-type Ge layer;
Step 107, growing an intrinsic DR-Ge 1-zSnz with the thickness of 15-20 nm on the intrinsic Ge isolating layer to generate a channel layer, wherein the range of z is 0.12-0.18;
Step 108, manufacturing an isolation region, a first intrinsic ternary alloy heterogeneous cap layer and a second intrinsic ternary alloy heterogeneous cap layer of the device manufactured in step 107; the first intrinsic ternary alloy heterogeneous cap layer is made of Si xGe1-x-ySny; wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07;
The second intrinsic ternary alloy heterogeneous cap layer is made of Si xGe1-x-ySny; wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1;
109, manufacturing a PMOS grid electrode on the first intrinsic ternary alloy heterogeneous cap layer, and manufacturing an NMOS grid electrode on the second intrinsic ternary alloy heterogeneous cap layer;
step 110, manufacturing a PMOS source drain region and an NMOS source drain region on the device manufactured in the step 109;
Step 111, depositing a dielectric layer on the surface of the device prepared in step 110;
112, manufacturing a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode and an NMOS drain electrode on the dielectric layer;
and 113, depositing a passivation layer on the surface of the device manufactured in the step 112.
The invention has the beneficial effects that:
1. The existence of the intrinsic ternary alloy heterogeneous cap layer avoids the direct contact between the gate region and the channel layer on one hand, so that the Fermi pinning effect of the channel region caused by interface states is eliminated, and the channel of the nMOS device is opened; on the other hand, under the field induction action of the gate voltage and the single-side high barrier blocking action formed by the band offset of the intrinsic ternary alloy heterogeneous cap layer and the deep delta EC conduction band of the channel layer, electrons from the N-type Ge layer are limited to the channel region and accumulated to form an open channel, so that the Ge-based enhanced nMOS device is realized.
2. When electrons are transported through the nMOS channel layer of the device, the mobility of electrons in the channel is further improved due to no surface roughness scattering (the channel layer is not in direct contact with a gate dielectric) and ionized impurity scattering (the non-movable charges of the ionized impurities are in the N-type Ge layer), and the performance of the device is correspondingly enhanced; the intrinsic ternary alloy heterogeneous cap layer is a ternary alloy with high Ge component, and the Fermi pinning effect enables the layer to be incapable of forming a parasitic channel, so that the subsequent circuit application is facilitated; the whole device is realized on a Si substrate, is compatible with a Si process, and is beneficial to integration and cost control.
3. The pMOS part is of a double heterojunction three-layer quantum well structure with energy band width-narrow-width-deep delta E V valence band bias, when the device works, the quantum well structure enables holes to be transported only in a quantum well channel, no surface roughness scattering (without direct contact with a gate medium) and no ionized impurity scattering (an ionized impurity non-movable charge is located in a second P-type Ge layer), and the channel high hole mobility ensures the excellent performance of the PMOS.
4. The two layers immediately below the channel layer are respectively an intrinsic Ge isolation layer, a second P-type Ge layer and an N-type Ge layer, the materials of all layers of the whole device are the same, only the partial regions are doped and the ternary alloy components of the intrinsic ternary alloy heterogeneous cap layer are different, and the Ge-based NMOS and Ge-based PMOS structures and the process compatibility are good.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1-37 are process diagrams of a direct bandgap GeSn CMOS device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 37, a first aspect of the embodiment of the present invention provides a direct bandgap GeSn CMOS device, comprising: the semiconductor device comprises a substrate layer 1, a Ge virtual substrate 4, a first P-type Ge layer 5, an isolation region 17, an N well 7, a second P-type Ge layer 11, an intrinsic Ge isolation layer 12, a channel layer 13, a first intrinsic ternary alloy heterogeneous cap layer 16, a PMOS gate electrode, a PMOS source drain region 25, an N-type Ge layer 8, a second intrinsic ternary alloy heterogeneous cap layer 20, an NMOS gate electrode, an NMOS source drain region 27, a dielectric layer 28, a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode and a passivation layer 30.
The substrate layer 1, the Ge virtual substrate 4 and the first P-type Ge layer 5 are sequentially arranged from bottom to top. The N-type Ge layer 8 and the second P-type Ge layer 11 are both located on top of the first P-type Ge layer 5.
The N-well 7 is located within the first P-type Ge layer 5 and below the second P-type Ge layer 11.
An intrinsic Ge isolation layer 12 is located on top of the N-type Ge layer 8 and the second P-type Ge layer 11.
The channel layer 13 is located on top of the intrinsic Ge isolation layer 12.
The first intrinsic ternary alloy heterogeneous cap layer 16 and the second intrinsic ternary alloy heterogeneous cap layer 20 are both located on top of the channel layer 13.
The isolation region 17 extends from the first P-type Ge layer 5 up through the intrinsic Ge isolation layer 12 and the channel layer 13 to above the first and second intrinsic ternary alloy heterocap layers 16 and 20. The N-well 7, the second P-type Ge layer 11 and the first intrinsic ternary alloy hetero-cap layer 16 are located on one side of the isolation region 17. An N-type Ge layer 8 and a second intrinsic ternary alloy hetero-cap layer 20 are located on the other side of the isolation region 17.
PMOS source drain regions 25 are located within the first intrinsic ternary alloy hetero-cap layer 16, channel layer 13 and intrinsic Ge isolation layer 12. The NMOS source drain region 27 is located within the second intrinsic ternary alloy hetero-cap layer 20, the channel layer 13 and the intrinsic Ge isolation layer 12.
The PMOS gate is located on top of the first intrinsic ternary alloy hetero-cap layer 16. The NMOS gate is located on top of the second intrinsic ternary alloy hetero-cap layer 20. The PMOS gate and NMOS gate are covered with a dielectric layer 28.
The PMOS source electrode and the PMOS drain electrode are located on the dielectric layer 28 and on one side of the isolation region 17, and are located on two sides of the PMOS gate respectively. The NMOS source electrode and the NMOS drain electrode are located on the dielectric layer 28 and on the other side of the isolation region 17, and on both sides of the NMOS gate. The dielectric layer 28, PMOS source electrode, PMOS drain electrode, NMOS source electrode, NMOS drain electrode are covered with a passivation layer 30.
The channel layer 13 is an intrinsic DR-Ge 1-zSnz layer; wherein z ranges from 0.12 to 0.18.
The material of the first intrinsic ternary alloy heterogeneous cap layer 16 is Si xGe1-x-ySny; wherein x ranges from 0.1 to 0.15 and y ranges from 0.05 to 0.07. In this embodiment, the first intrinsic ternary alloy heterojunction cap layer 16 has a forbidden bandwidth larger than that of DR-GeSn, and forms a deep Δe V valence band bias heterojunction with the channel layer 13. The PMOS part is of a band width-narrow-width-depth delta E V valence band bias double heterojunction three-layer quantum well structure, when the device works, the quantum well structure enables holes to be transported only in a quantum well channel, no surface roughness scattering (without direct contact with a gate medium) and no ionized impurity scattering (an ionized impurity non-movable charge is positioned on the second P-type Ge layer 11), and the channel high hole mobility ensures the excellent performance of the PMOS.
The material of the second intrinsic ternary alloy heterogeneous cap layer 20 is Si xGe1-x-ySny; wherein x ranges from 0.1 to 0.15 and y ranges from 0.08 to 0.1. In this embodiment, the second intrinsic ternary alloy heterojunction cap layer 20 has a forbidden bandwidth larger than that of DR-GeSn, and forms a deep Δe C band bias heterojunction with the channel layer 13. When the NMOS device applies gate voltage to work, the existence of the intrinsic ternary alloy heterogeneous cap layer prevents the gate region from being in direct contact with the channel layer 13, so that the Fermi pinning effect of the channel region caused by interface states is eliminated, and the channel of the NMOS device is opened; on the other hand, under the field induction action of the gate voltage and the single-side high barrier blocking action formed by the deep delta EC conduction band offset of the intrinsic ternary alloy heterogeneous cap layer and the channel layer 13, electrons from the N-type Ge layer 8 are limited to the channel region and accumulated to form an open channel, so that the Ge-based enhanced nMOS device is realized.
In addition, when electrons of the channel layer 13 are transported, the channel electron mobility is further improved, and the device performance is correspondingly enhanced due to no surface roughness scattering (the channel layer 13 is not in direct contact with the gate dielectric) and ionized impurity scattering (the ionized impurity non-movable electric energy is in the N-type Ge layer 8); the intrinsic ternary alloy heterogeneous cap layer is a ternary alloy with high Ge component, and the Fermi pinning effect enables the layer to be incapable of forming a parasitic channel, so that the subsequent circuit application is facilitated; the whole device is realized on a Si substrate, is compatible with a Si process, and is beneficial to integration and cost control.
In the embodiment, the materials of all layers of the whole CMOS device are the same, only partial regions are doped and the ternary alloy components are different, and the Ge-based NMOS and Ge-based PMOS structures and the process compatibility are good. The DR-GeSn CMOS structure formed by the unilateral high barrier quantum confinement NMOS and the quantum well PMOS has high channel carrier mobility and excellent performance indexes such as device driving capability.
Further, the doping concentration of the first P-type Ge layer 5 is 1×10 16～1×1017cm-3; the doping concentration of the second P-type Ge layer 11 is 1×10 16～1×1019cm-3; the doping concentration of the N-type Ge layer 8 is 1×10 16～1×1019cm-3.
Further, the thickness of the channel layer 13 is 15 to 20nm.
Further, the thickness of the first intrinsic ternary alloy heterogeneous cap layer 16 is 5-10 nm; the thickness of the second intrinsic ternary alloy heterogeneous cap layer 20 is 5-10 nm.
Further, the substrate layer 1 employs single crystal Si. The whole device is realized on a Si substrate, is compatible with a Si process, and is beneficial to integration and cost control.
Example two
A second aspect of the embodiments of the present invention provides a method for manufacturing a direct bandgap GeSn CMOS device, including the steps of:
step 101, selecting a substrate: single crystal Si was selected as the substrate layer 1 as shown in fig. 1.
Step 102, preparing the Ge virtual substrate 4 by using a laser recrystallization method. The specific steps of step 102 include:
Step 1021, cleaning the substrate layer 1 by using an RCA method, and then cleaning by using 10% hydrofluoric acid to remove the Si surface oxide layer.
Step 1022, sputtering and depositing the intrinsic Ge target material with the purity of 99.999% on the substrate layer 1 at the process pressure of 1.5X10-3 mb and the deposition rate of 5nm/min by adopting a magnetron sputtering method at the temperature of 400-500 ℃ to form the Ge epitaxial layer film 2, wherein the deposition thickness is 300-400 nm, as shown in figure 2.
Step 1023, depositing a first silicon dioxide protection layer 3: a first protective layer 3 of silicon dioxide having a thickness of 100nm is deposited on the Ge epilayer film 2 using a CVD process, as shown in fig. 3.
And 1024, heating the material prepared in the step 1023 to 600-650 ℃, then continuously scanning by laser, wherein the laser wavelength is 808nm, the laser power density is 2.1kW/cm < 2 >, the laser spot size is 10mm multiplied by 1mm, the laser moving speed is 20mm/s, and then naturally cooling the material. The continuous laser irradiation causes melting and recrystallization after cooling of the Ge epilayer film 2, which greatly reduces the dislocation density of the epilayer.
The laser physical parameters (laser power, scanning speed, etc.) of the laser are precisely controlled to recrystallize the high-Ge epitaxial layer film, and the initial temperature and epitaxial layer thickness of the Ge epitaxial layer film 2 are required to be precisely controlled. For the setting of the laser power, the laser energy is required to make the temperature of the Ge epitaxial layer film 2 at least reach the melting point, and as high as possible without exceeding the ablation point. Such a heat treatment process can significantly improve the crystal quality of the Ge epitaxial layer. Meanwhile, the initial temperature parameter of Ge epitaxy is also considered, and the Ge epitaxy is preheated before laser recrystallization, so that the threshold laser power required by laser recrystallization can be obviously reduced. The Si substrate and the Ge epitaxial layer film 2 have thermal mismatch, and the preheating of the system can also effectively prevent the cracking phenomenon of the material caused by the instantaneous and great temperature rise during laser irradiation.
Step 1025, naturally cooling the material prepared in step 1024, and etching the first silicon dioxide protective layer 3 by using a dry etching process to obtain a Ge virtual substrate 4, as shown in fig. 4.
Step 103, depositing a first P-type Ge layer 5 with the thickness of 700-750 nm on the surface of the Ge virtual substrate 4 by utilizing a molecular beam epitaxy process at the temperature of 500-600 ℃, wherein the doping concentration is 1 multiplied by 10 16～1×1017cm-3, as shown in figure 5.
Step 104, coating photoresist 6 on the surface of the first P-type Ge layer 5, exposing the photoresist in one side region, and implanting P ions into the exposed region by using an ion implantation process to form an N-well 7, as shown in fig. 6.
Step 105, removing the residual photoresist 6, and manufacturing an N-type Ge layer 8 and a second P-type Ge layer 11 on the surface. The specific steps of step 105 include:
Step 1051, the remaining photoresist 6 is removed, as shown in fig. 7.
Step 1052, the surface of the device manufactured in step 1501 is deposited with an N-type Ge layer 8 having a thickness of 5-10 nm by Molecular Beam Epitaxy (MBE) process, and the doping concentration is 1×10 16～1×1019cm-3, as shown in fig. 8.
In step 1053, a first SiO 2 layer 9 with a thickness of 20nm is deposited on the surface of the N-type Ge layer 8, as shown in fig. 9.
Step 1054, depositing a first Si 3N4 layer 10 with a thickness of 20-30 nm on the first SiO 2 layer 9, as shown in FIG. 10.
Step 1055 etches away the first SiO 2 layer 9 and the first Si 3N4 layer 10 at corresponding locations over the N-well 7, as shown in fig. 11.
In step 1056, ion compensation is performed on the unmasked N-type Ge layer 8 above the N-well 7 to form a second P-type Ge layer 11, with a doping concentration of 1×10 16～1×1019cm-3, as shown in fig. 12.
Step 1057, removing the first SiO 2 layer 9 and the first Si 3N4 layer 10 on the N-type Ge layer 8 by wet etching, as shown in fig. 13.
And 106, depositing an intrinsic Ge isolation layer 12 with the thickness of 15-20 nm on the surfaces of the N-type Ge layer 8 and the second P-type Ge layer 11 by utilizing a molecular beam epitaxy process at the temperature of 500-600 ℃, as shown in fig. 14.
Step 107, growing an intrinsic DR-Ge 1-zSnz with a thickness of 15-20 nm on the intrinsic Ge isolating layer 12 by utilizing a molecular beam epitaxy process at a temperature of 500-600 ℃ to generate a channel layer 13, wherein z ranges from 0.12 to 0.18, as shown in fig. 15.
Step 108, manufacturing an isolation region 17, a first intrinsic ternary alloy heterogeneous cap layer 16 and a second intrinsic ternary alloy heterogeneous cap layer 20 of the device manufactured in step 107; wherein the material of the first intrinsic ternary alloy heterogeneous cap layer 16 is Si xGe1-x- ySny; wherein x ranges from 0.1 to 0.15 and y ranges from 0.05 to 0.07.
The material of the second intrinsic ternary alloy heterogeneous cap layer 20 is Si xGe1-x-ySny; wherein x ranges from 0.1 to 0.15 and y ranges from 0.08 to 0.1. The specific steps of step 108 include:
step 1081, etching isolation grooves with a depth of 100-150 nm on the device prepared in step 107 by using a dry etching process, as shown in fig. 16.
Step 1082, depositing a second SiO 2 material 14 on the surface of the device at 680-730 ℃ by using a CVD process, and filling the isolation groove, as shown in FIG. 17.
Step 1083, depositing a second Si 3N4 layer 15 with a thickness of 20-30 nm on the surface of the second SiO 2 material 14 by using a CVD process, as shown in FIG. 18.
Step 1084 etches away the second SiO 2 material 14 and the second Si 3N4 layer 15 on the surface of the channel layer 13 over the N-well 7, as shown in fig. 19.
Step 1085, depositing intrinsic Si xGe1-x-ySny with a thickness of 5-10 nm on the surface of the channel layer 13 by using a molecular beam epitaxy process to form a first intrinsic ternary alloy heterogeneous cap layer 16, wherein x ranges from 0.1 to 0.15 and y ranges from 0.05 to 0.07, as shown in fig. 20.
Step 1086, etching to remove the remaining second Si 3N4 layer 15 and a portion of the second SiO 2 material 14 on the device surface, forming isolation regions 17, as shown in fig. 21.
Step 1087, using a CVD process, continues to deposit a third SiO 2 material 18 and a third Si 3N4 layer 19 at 20-30 nm on the device surface fabricated at step 1086, as shown in fig. 22.
Step 1088, etching to remove the third SiO 2 material 18 and the third Si 3N4 layer 19 on the surface of the channel layer 13 on the other side of the isolation region 17, as shown in fig. 23.
Step 1089, depositing intrinsic Si xGe1-x-ySny with a thickness of 5-10 nm on the surface of the channel layer 13 by using a molecular beam epitaxy process to form a second intrinsic ternary alloy heterogeneous cap layer 20, wherein x ranges from 0.1 to 0.15 and y ranges from 0.08 to 0.10, as shown in FIG. 24. The remaining third SiO 2 material 18 and third Si 3N4 layer 19 are then etched away, as shown in fig. 25.
Step 109, a PMOS gate is fabricated on the first intrinsic ternary alloy hetero-cap layer 16 and an NMOS gate is fabricated on the second intrinsic ternary alloy hetero-cap layer 20. The specific steps of step 109 include:
Step 1091, depositing a layer 21 of HfO 2 with a thickness of 5-10 nm by atomic layer deposition, as shown in FIG. 26.
Step 1092, depositing a TaN layer 22 with a thickness of 70nm on the surface of the HfO 2 layer 21 by CVD at a temperature of 750-850 ℃, as shown in fig. 27.
Step 1093, etching portions of the TaN layer 22 and the HfO 2 layer 21 using a selective etching process to form a PMOS gate on the first intrinsic ternary alloy heterostructure cap layer 16 and an NMOS gate on the second intrinsic ternary alloy heterostructure cap layer 20, as shown in fig. 28.
Step 110, manufacturing a PMOS source drain region 25 and an NMOS source drain region 27 on the device manufactured in step 109. The specific steps of step 110 include:
In step 1101, a fourth SiO 2 material 23 is deposited on the surface of the device fabricated in step 109 by using a CVD process, and regions other than the NMOS gate and the PMOS gate are etched by using a selective etching process, as shown in fig. 29.
In step 1102, the NMOS region on the other side of the isolation region 17 is covered with the photoresist 24, and BF 2 + is performed on the PMOS active region in the N-well 7 by using an ion implantation process to form a PMOS source drain region 25, as shown in fig. 30. The photoresist 24 is then removed.
In step 1103, the PMOS region on one side of the isolation region 17 is covered with the photoresist 26, and the NMOS source drain region 27 is formed by performing As ion implantation on the NMOS active region by using an ion implantation process, as shown in fig. 31. Photoresist 26 is then removed.
Step 1104, removing the fourth SiO 2 material 23 on the NMOS gate and PMOS gate surfaces, as shown in fig. 32.
Step 111, BPSG with a thickness of 30-50 nm is deposited on the surface of the device prepared in step 110 by using a CVD process to form the dielectric layer 28, as shown in FIG. 33.
Step 112, a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, and an NMOS drain electrode are fabricated on dielectric layer 28. Specifically, the NMOS source drain contact hole and the PMOS source drain contact hole are formed by etching BPSG with nitric acid and hydrofluoric acid, as shown in fig. 34.
Then, tungsten metal 29 with a thickness of 20nm is deposited on the surface of the device by using an electron beam evaporation process to form source-drain contacts, as shown in fig. 35. Thereafter, the metal tungsten 29 of the designated area is etched by a selective etching process, and a planarization process is performed by a CMP process, as shown in fig. 36.
Step 113, depositing the surface of the device manufactured in step 112. SiN material with the thickness of 20-30 nm is deposited on the whole substrate surface by using a CVD process for passivating the dielectric, forming a passivation layer 30, and finally forming the direct band gap GeSn CMOS device, as shown in figure 37.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (9)

1. A direct bandgap GeSn CMOS device, comprising: the semiconductor device comprises a substrate layer (1), a Ge virtual substrate (4), a first P-type Ge layer (5), an isolation region (17), an N-well (7), a second P-type Ge layer (11), an intrinsic Ge isolation layer (12), a channel layer (13), a first intrinsic ternary alloy heterogeneous cap layer (16), a PMOS gate electrode, a PMOS source drain region (25), an N-type Ge layer (8), a second intrinsic ternary alloy heterogeneous cap layer (20), an NMOS gate electrode, an NMOS source drain region (27), a dielectric layer (28), a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode and a passivation layer (30);
The substrate layer (1), the Ge virtual substrate (4) and the first P-type Ge layer (5) are sequentially arranged from bottom to top;
the N-type Ge layer (8) and the second P-type Ge layer (11) are both positioned on the upper layer of the first P-type Ge layer (5);
The N well (7) is positioned in the first P-type Ge layer (5) and below the second P-type Ge layer (11);
The intrinsic Ge isolation layer (12) is positioned on the upper layers of the N-type Ge layer (8) and the second P-type Ge layer (11);
the channel layer (13) is positioned on the upper layer of the intrinsic Ge isolating layer (12);
the first intrinsic ternary alloy heterogeneous cap layer (16) and the second intrinsic ternary alloy heterogeneous cap layer (20) are both positioned on the upper layer of the channel layer (13);
the isolation region (17) extends from the first P-type Ge layer (5) up through the intrinsic Ge isolation layer (12) and the channel layer (13) to above the first and second intrinsic ternary alloy hetero-cap layers (16, 20);
The N well (7), the second P-type Ge layer (11) and the first intrinsic ternary alloy heterogeneous cap layer (16) are positioned on one side of the isolation region (17);
The N-type Ge layer (8) and the second intrinsic ternary alloy heterogeneous cap layer (20) are positioned on the other side of the isolation region (17);
The PMOS source/drain region (25) is positioned in the first intrinsic ternary alloy heterogeneous cap layer (16), the channel layer (13) and the intrinsic Ge isolating layer (12);
The NMOS source-drain region (27) is positioned in the second intrinsic ternary alloy heterogeneous cap layer (20), the channel layer (13) and the intrinsic Ge isolating layer (12);
the PMOS grid electrode is positioned on the upper layer of the first intrinsic ternary alloy heterogeneous cap layer (16);
the NMOS grid electrode is positioned on the upper layer of the second intrinsic ternary alloy heterogeneous cap layer (20);
a dielectric layer (28) is covered on the PMOS gate and the NMOS gate;
The PMOS source electrode and the PMOS drain electrode are positioned on the dielectric layer (28) and on one side of the isolation region (17) and on two sides of the PMOS grid electrode respectively;
the NMOS source electrode and the NMOS drain electrode are positioned on the dielectric layer (28) and on the other side of the isolation region (17) and on the two sides of the NMOS grid electrode;
The medium layer (28), the PMOS source electrode, the PMOS drain electrode, the NMOS source electrode and the NMOS drain electrode are covered with the passivation layer (30);
The material of the first intrinsic ternary alloy heterogeneous cap layer (16) is Si xGe1-x-ySny; wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07;
The second intrinsic ternary alloy heterogeneous cap layer (20) is made of Si xGe1-x-ySny; wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1;
the channel layer (13) is an intrinsic DR-Ge 1-zSnz layer; wherein z ranges from 0.12 to 0.18.
2. A direct bandgap GeSn CMOS device according to claim 1, wherein the doping concentration of the first P-type Ge layer (5) is 1 x 10 16～1×1017cm-3; the doping concentration of the second P-type Ge layer (11) is 1 multiplied by 10 16～1×1019cm-3; the doping concentration of the N-type Ge layer (8) is 1 multiplied by 10 16～1×1019cm-3.
3. A direct bandgap GeSn CMOS device according to claim 1, wherein the channel layer (13) has a thickness of 15-20nm.
4. A direct bandgap GeSn CMOS device as claimed in claim 1, wherein the thickness of the first intrinsic ternary alloy hetero-cap layer (16) is 5-10 nm; the thickness of the second intrinsic ternary alloy heterogeneous cap layer (20) is 5-10 nm.
5. A direct bandgap GeSn CMOS device according to claim 1, wherein the substrate layer (1) is of single crystal Si.
6. The preparation method of the direct band gap GeSn CMOS device is characterized by comprising the following steps of:
step 101, selecting a substrate: selecting single crystal Si as a substrate layer (1);
102, preparing a Ge virtual substrate (4) by using a laser recrystallization method;
Step 103, depositing a first P-type Ge layer (5) on the surface of the Ge virtual substrate (4);
Step 104, coating photoresist on the surface of the first P-type Ge layer (5), exposing the photoresist on one side area, and injecting P ions into the exposed area by utilizing an ion implantation process to form an N well (7);
Step 105, removing the residual photoresist, and manufacturing an N-type Ge layer (8) and a second P-type Ge layer (11) on the surface;
step 106, depositing an intrinsic Ge isolating layer (12) on the surfaces of the N-type Ge layer (8) and the second P-type Ge layer (11);
Step 107, growing an intrinsic DR-Ge 1-zSnz with the thickness of 15-20 nm on the intrinsic Ge isolating layer (12) to generate a channel layer (13), wherein z ranges from 0.12 to 0.18;
Step 108, manufacturing an isolation region (17), a first intrinsic ternary alloy heterogeneous cap layer (16) and a second intrinsic ternary alloy heterogeneous cap layer (20) by the device manufactured in step 107; wherein the material of the first intrinsic ternary alloy heterogeneous cap layer (16) is Si xGe1-x-ySny; wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07; the isolation region (17) extends from the first P-type Ge layer (5) up through the intrinsic Ge isolation layer (12) and the channel layer (13) to above the first and second intrinsic ternary alloy hetero-cap layers (16, 20); the first intrinsic ternary alloy heterogeneous cap layer (16) is located on one side of the isolation region (17);
The second intrinsic ternary alloy heterogeneous cap layer (20) is made of Si xGe1-x-ySny; wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1;
Step 109, manufacturing a PMOS grid on the first intrinsic ternary alloy heterogeneous cap layer (16), and manufacturing an NMOS grid on the second intrinsic ternary alloy heterogeneous cap layer (20);
Step 110, manufacturing a PMOS source drain region (25) and an NMOS source drain region (27) on the device manufactured in the step 109;
Step 111, depositing a dielectric layer (28) on the surface of the device prepared in step 110;
112, manufacturing a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode and an NMOS drain electrode on the dielectric layer (28);
Step 113, depositing a passivation layer (30) on the surface of the device manufactured in step 112.
7. The method for fabricating a direct bandgap GeSn CMOS device of claim 6, wherein said step 105 comprises the specific steps of:
step 1051, removing the residual photoresist;
step 1052, depositing an N-type Ge layer (8) with the thickness of 5-10 nm on the surface of the device manufactured in step 1501, wherein the doping concentration is 1 multiplied by 10 16～1×1019cm-3;
Step 1053, depositing a first SiO 2 layer (9) with the thickness of 20nm on the surface of the N-type Ge layer (8);
Step 1054, depositing a first Si 3N4 layer (10) with the thickness of 20-30 nm on the first SiO 2 layer (9);
Step 1055, etching to remove the first SiO 2 layer (9) and the first Si 3N4 layer (10) at the corresponding positions above the N well (7);
Step 1056, performing ion compensation on the N-type Ge layer (8) above the N-well (7) to form a second P-type Ge layer (11), wherein the doping concentration is 1×10 16～1×1019cm-3;
And 1057, removing the first SiO 2 layer (9) and the first Si 3N4 layer (10) on the N-type Ge layer (8) by adopting a wet etching method.
8. The method of manufacturing a direct bandgap GeSn CMOS device of claim 6, wherein said step 108 comprises the specific steps of:
Step 1081, etching an isolation groove with the depth of 100-150 nm on the device prepared in step 107 by using a dry etching process;
Step 1082, depositing a second SiO 2 material (14) on the surface of the device, and filling the isolation groove;
Step 1083, depositing a second Si 3N4 layer (15) with the thickness of 20-30 nm on the surface of the second SiO 2 material (14);
step 1084, etching to remove the second SiO 2 material (14) and the second Si 3N4 layer (15) on the surface of the channel layer (13) above the N well (7);
step 1085, depositing intrinsic Si xGe1-x-ySny with the thickness of 5-10 nm on the surface of the channel layer (13) to form a first intrinsic ternary alloy heterogeneous cap layer (16), wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07;
Step 1086, etching to remove the second Si 3N4 layer (15) and part of the second SiO 2 material (14) remained on the surface of the device, so as to form an isolation region (17);
Step 1087, depositing a third SiO 2 material (18) and a third Si 3N4 layer (19) with the thickness of 20-30 nm on the surface of the device manufactured in step 1086;
Step 1088, etching to remove the third SiO 2 material (18) and the third Si 3N4 layer (19) on the surface of the channel layer (13) on the other side of the isolation region (17);
Step 1089, depositing intrinsic Si xGe1-x-ySny with the thickness of 5-10 nm on the surface of the channel layer (13) to form a second intrinsic ternary alloy heterogeneous cap layer (20), wherein x ranges from 0.1 to 0.15, and y ranges from 0.08 to 0.10; the remaining third SiO 2 material (18) and third Si 3N4 layer (19) are then etched away.
9. The method of fabricating a direct bandgap GeSn CMOS device of claim 6, wherein the specific steps of step 110 include:
Step 1101, depositing a fourth SiO 2 material (23) on the surface of the device prepared in step 109, and etching out the areas except the NMOS grid and the PMOS grid;
Step 1102, covering an NMOS region at the other side of the isolation region (17) by using photoresist, and performing BF 2 + implantation on a PMOS active region in the N well (7) by adopting an ion implantation process to form a PMOS source drain region (25);
Step 1103, covering a PMOS region at one side of the isolation region (17) by photoresist, and performing As ion implantation on the NMOS active region by adopting an ion implantation process to form an NMOS source drain region (27); step 1104, removing the fourth SiO 2 material (23) on the surfaces of the NMOS gate and the PMOS gate.
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