CN113505401A - Hybrid PUF circuit capable of extracting physical fingerprints of chip and circuit board and extraction method - Google Patents
Hybrid PUF circuit capable of extracting physical fingerprints of chip and circuit board and extraction method Download PDFInfo
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- CN113505401A CN113505401A CN202110788634.8A CN202110788634A CN113505401A CN 113505401 A CN113505401 A CN 113505401A CN 202110788634 A CN202110788634 A CN 202110788634A CN 113505401 A CN113505401 A CN 113505401A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
Abstract
The invention relates to a hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board and an extraction method. The circuit comprises an Arbiter PUF circuit: the system comprises an N-level switch delay module and an arbiter module, wherein the N-level switch delay module can generate two paths of in-chip delay signals; delay circuit outside the chip: the chip comprises an off-chip symmetrical delay module capable of generating two paths of off-chip delay signals, and an arbiter module which inputs two paths of total delay signals obtained by superposing the off-chip delay signals and the on-chip delay signals into the chip; the invention only needs 4 Pad pins and 2 external delay generation modules, and 2 can be generatedNAnd the consumption of external pins and resources is small for each excitation response pair. Because two paths of delay signals of the external delay module are difficult to detect and cannot be forged even if the two paths of delay signals are detected, and any attempt of changing the physical environment of the external circuit board can cause the output result to be permanently invalid and cannot be reconstructed, the anti-falsification and anti-counterfeiting effect is good.
Description
Technical Field
The invention relates to the technical field of communication and the field of information security, in particular to a hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board and an extraction method.
Background
A Physical Unclonable Function (PUF) is a function that inputs a stimulus to a chip and outputs an unpredictable response using the random process variations that are inevitable during the chip manufacturing process. The response of the PUF circuit output in each chip is unique and irreproducible, even by the chip designer and manufacturer, due to irreversible errors in the chip manufacturing process. The above characteristics of the PUF circuit have very important applications in the fields of communication technology and information security, for example, the output of the PUF circuit can be used as a unique Identification (ID) number of a chip, as a fingerprint or a secret key of the chip to further implement identity authentication of the chip, and can also be used for Intellectual Property (IP) protection, and can also be used as a true random number generator.
At present, an SRAM PUF, a ring oscillator PUF, an Arbiter PUF, an SRPUF and the like are PUF circuits implemented inside a chip, most of PUF circuits generate unpredictable and uncopyable output variables only by using process deviations inside the chip, but cannot extract changes of physical characteristics (such as an external circuit, packaging and welding of the chip and the like) of a circuit board, that is, the integrity of a chip external circuit or the packaging and welding of the chip is damaged, output values of the PUF circuits inside the chip do not change synchronously, and we can understand that the state output of the PUF circuits and the integrity of the chip external circuit or the packaging and welding of the chip do not establish tight coupling and corresponding relation. When a chip with a PUF circuit is used for security authentication, the PUF circuit does not have the ability to extract physical features of the circuit board, and thus, a security hole may be generated in the authentication system.
If the chip with the PUF circuit is bound with the PCB, the identification and the anti-counterfeiting authentication of the electronic product can be realized. Particularly, if the PUF circuit integrated with the chip can extract different fine physical characteristics (such as external circuit characteristics, packaging, welding and the like) of the circuit board, and an irreproducible and irreparable stimulus-response corresponding relationship is generated, the corresponding relationship can be bound with an electronic product to serve as the unique irreproducible digital identity of the electronic product, so that article circulation management and anti-counterfeiting traceability are effectively realized, and the method plays an important role in preventing fake and counterfeit commodities from entering the market. However, the conventional techniques have many problems, for example, the number of generated key bits is insufficient, the resource consumption is too large, and the like, and thus the conventional techniques have not been widely used.
Disclosure of Invention
Aiming at the problem that the existing PUF can only generate response through process deviation in a chip and cannot be applied to anti-counterfeiting of a circuit board outside the chip, the invention provides a hybrid PUF circuit capable of extracting physical fingerprints of the chip and the circuit board, aiming at coupling physical characteristics of the circuit board outside the chip into an internal PUF response generation flow, and destroying the connection between the chip and the PCB board by any attempt of chip disassembly or external circuit damage or the like for counterfeiting so as to cause permanent failure of the output of the PUF.
In order to achieve the purpose, the invention provides a hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board, which can generate a digital key with a large number of digits under the condition of extremely little consumption of external resources (pins, connecting wires and the like), can effectively prevent physical detection, tampering and counterfeiting, and can provide a high-safety low-cost solution for anti-counterfeiting traceability of electronic products.
A hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board is characterized by comprising
Arbiter PUF circuit: the system comprises an N-level switch delay module and an arbiter module, wherein the N-level switch delay module can generate two paths of in-chip delay signals;
delay circuit outside the chip: the chip comprises an off-chip symmetrical delay module capable of generating two paths of off-chip delay signals, and an arbiter module which inputs two paths of total delay signals obtained by superposing the off-chip delay signals and the on-chip delay signals into the chip; the arbiter module generates digital responses according to the sequence of the two paths of total delay signals reaching the input port of the arbiter;
preferably, the N-stage switching delay module includes N cascaded two-out-of-two multi-way switching stages, the N cascaded multi-way switches form two delay paths including a first delay path and a second delay path under the control of the N-bit excitation signal C, and N is a positive integer greater than or equal to 1.
Preferably, the off-chip symmetric delay module is two paths, and includes a first symmetric delay module and a second symmetric delay module, when the N multi-way switches are greater than or equal to 1, the first delay path and the second delay path are outputs of the nth multi-way switch, one end of the first symmetric delay module and one end of the second symmetric delay module are respectively connected to the first delay path and the second delay path, and the other end of the first symmetric delay module and the other end of the second symmetric delay module are respectively connected to two paths of inputs of the arbiter module.
Preferably, the off-chip symmetric delay module is two paths, and includes a first symmetric delay module and a second symmetric delay module, when N multi-way switches are greater than or equal to 2, the first delay path and the second delay path are outputs of the jth multi-way switch, where J is a positive integer, and 0< J < N, and at this time, one end of the first symmetric delay module and one end of the second symmetric delay module are respectively connected to the first delay path and the second delay path, the other end of the first symmetric delay module and one end of the second symmetric delay module are connected to inputs of the J +1 th multi-way switch, and two outputs of the nth multi-way switch are respectively connected to two inputs of the arbiter module.
Preferably, two ends of the first symmetric delay module and the second symmetric delay module are both connected in series between the N-stage switch delay module and the arbiter module through Pad pins; n-stage switch delay module passes through chip pin Pad1And Pad2Connected with an external delay module, the delay module outside the chip is connected with the external delay module through a chip pin Pad3And Pad4Connected to the arbiter module.
Preferably, two ends of the first symmetric delay module and the second symmetric delay module are both connected in series between the J-th stage switch delay module and the J + 1-th stage switch delay module through Pad pins; n-stage switch delay module passes through chip pin Pad1、Pad2、Pad3And Pad4UConnected to the off-chip symmetric delay module.
A method for extracting a hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board is characterized by comprising the following steps:
Step 2, the output of the two paths of delay paths passes through a chip pin Pad1And Pad2And the two paths of total delay paths, namely the first total delay path and the second total delay path, are formed by the way. The same input signal is simultaneously input into the two paths of total delay paths, two paths of different total delay signals can be generated under the working condition, and the two paths of different total delay signals pass through a chip pin Pad3And Pad4Input to an arbiter module inside the chip,
step 3, the arbiter module generates digital responses 0 or 1 according to the sequence of the total delay signals on the two delay paths reaching the input port, thereby generating 2NAnd each excitation response pair.
As another scheme, a method for extracting a hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board, includes:
Step 2, the output of the J-th multi-way switch of the N-stage switch delay module in the chip passes through a chip pin Pad1And Pad2Connected to external first and second symmetric delay blocks. The outputs of the external first and second symmetric delay modules pass through chip pins Pad3And Pad4And the two outputs of the Nth multi-way switch are respectively connected with the two inputs of the arbiter module. Two total delay paths, namely a first total delay path and a second total delay path, are formed in the above mode. The same input signal is simultaneously input into the two paths of total delay paths, two paths of different total delay signals can be generated under the working condition,
step 3, the arbiter module generates a digital response 0 or 1 according to the sequence of the total delay signals reaching the input port of the arbiter, thereby generating 2NAnd each excitation response pair.
Compared with the prior art, the invention has the following advantages: the invention only needs 4 Pad pins and 2 external delay generation modules, and 2 can be generatedNAnd the consumption of external pins and resources is small for each excitation response pair. Because two paths of delay signals of the external delay module are difficult to detect and cannot be forged even if the two paths of delay signals are detected, and any attempt of changing the physical environment of the external circuit board can cause the output result to be permanently invalid and cannot be reconstructed, the anti-falsification and anti-counterfeiting effect is good.
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Fig. 1 shows a specific circuit configuration of an embodiment of the present invention.
Fig. 2 shows a specific circuit structure of another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail in order to make the objects, technical solutions and advantages of the present invention more apparent.
The invention provides a hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board, which comprises an Arbiter PUF circuit inside the chip and a delay circuit outside the chip, and is shown in figure 1. The Arbiter PUF circuit in the chip is composed of an N-level switch delay module and an Arbiter module; the delay circuit outside the chip is composed of two paths of symmetrical delay modules and is connected between the N-level switch delay module and the Arbiter module of the Arbiter PUF inside the chip in series through Pad pins. The strong PUF circuit structure capable of simultaneously extracting the physical characteristics of the chip and the circuit board can couple the physical characteristics of an external PCB circuit board into the PUF circuit, so that a corresponding relation of excitation response related to the PCB circuit board is generated, and any attempt of changing the physical environment of the circuit board can cause the output result to be permanently invalid and incapable of being reconstructed.
The N-stage switch delay module may be, but is not limited to, formed by N (N is a positive integer greater than 1) two-by-two multi-way switches, where the N multi-way switches form two delay paths under the control of the N excitation signals C, and the two delay paths include a first delay path and a second delay path. Because the chip has inevitable process difference in the manufacturing process, the two delay paths can generate different on-chip delay signals under the control of the excitation signal.
The two symmetrical delay modules in the off-chip delay circuit can be realized by but not limited to two symmetrical wires on a PCB, and are respectively connected into a first delay path and a second delay path in the chip through chip pins. Due to the random process difference of the circuit board in the manufacturing process, two off-chip delay chains which are completely the same in design also have difference after the manufacturing is finished, so that two different off-chip delay signals can be generated. The off-chip delay signal and the on-chip delay signal are superposed and then input into an arbiter module in the chip. The arbiter module then generates a digital response of 0 or 1 based on the magnitude of the total delay signal on the two delay paths.
N-stage switch delay module inside chip through chip pin Pad1And Pad2Connected with an external delay module, the delay module outside the chip is connected with the external delay module through a chip pin Pad3And Pad4Connected to the arbiter module in the chip, so that a close coupling of the chip to the PCB can be established, thereby creating a unique stimulus-response correspondence.
The specific principle is as follows: due to the random process difference in the manufacturing process of the PCB, two off-chip delay lines which are identical in design will also be different after manufacturing, so some slight deviation will be introduced to cause the parameters to change. The change of the parameters can cause the time delay of the off-chip line to change, and the off-chip line is connected between the N-level switch delay module and the Arbiter module of the Arbiter PUF in the chip in series, so that the time delay information can be introduced into the PUF response generation flow, and the PUF response value related to the physical characteristics of the circuit board is generated. Since these slight deviations can be stably maintained after the response is generated, any action of detaching the chip or changing the physical environment of the circuit board changes the corresponding parameters, and further changes the delay of the line, resulting in the change of the response output of the PUF. Since the generation of these subtle differences is completely random in the manufacturing process, the reconstruction of the physical environment is not possible. Therefore, the invention can realize the unique correspondence between the PCB and the PUF output, and can generate the irreproducible and untrustworthy excitation-response correspondence.
The specific working process is as follows: as shown in fig. 1, when the N-bit excitation signal C is input, the N multi-way switches form two delay paths, i.e., a first delay path and a second delay path, under the control of the N-bit excitation signal C. Because the chip has inevitable process deviation in the manufacturing process, delay signals generated by two delay paths which should be symmetrical in an ideal state under the working condition have certain deviation, and thus two paths of different in-chip delay signals are generated. N-stage switch delay module inside chip through chip pin Pad1And Pad2And is connected with the external two-path delay module. Due to the random process difference of the circuit board in the manufacturing process, two completely same off-chip delay modules in design also have difference after manufacturing, so that two paths of different off-chip delay signals can be generated, the off-chip delay signals are superposed on the on-chip delay signals, and finally, the two paths of different off-chip delay signals pass through a chip pin Pad3And Pad4And the arbiter module is connected with the arbiter module in the chip and inputs the total delay signal into the arbiter module in the chip, and the arbiter module generates a digital response 0 or 1 according to the magnitude of the total delay signal on the two delay paths. Only 4 Pad pins and 2 external delay lines are needed to generate 2NAnd the consumption of external pins and resources is small for each excitation response pair.
The PUF response generated by the invention is closely related to the PCB, and if the chip is detached and replaced to other places or welding pins and PCB lines are changed, the output result of the PUF is changed. Meanwhile, each time the Pad pin is soldered and the time delay generated by each PCB is unique, any attempt to change the physical environment of the PCB can cause the output result to be permanently invalid and can not be rebuilt.
As another embodiment, as shown in fig. 2, the Arbiter PUF circuit inside the chip is composed of an N-stage switch delay module and an Arbiter module; the delay circuit outside the chip is composed of two paths of symmetrical delay modules and is connected between any two switch delay modules in the N-stage switch delay module of the Arbiter PUF inside the chip in series through Pad pins. The strong PUF circuit structure capable of simultaneously extracting the physical characteristics of the chip and the circuit board can couple the physical characteristics of an external PCB circuit board into the PUF circuit, so that a corresponding relation of excitation response related to the PCB circuit board is generated, and any attempt of changing the physical environment of the circuit board can cause the output result to be permanently invalid and incapable of being reconstructed.
The specific working process is as follows: as shown in fig. 2, when the N-bit excitation signal C is input, the J multi-way switches form two delay paths, a first delay path and a second delay path, under the control of the excitation signal C.
The output of the J-th multi-way switch of the N-stage switch delay module in the chip passes through a chip pin Pad1And Pad2Connected to external first and second symmetric delay blocks. The outputs of the external first and second symmetric delay modules pass through chip pins Pad3And Pad4And the two outputs of the Nth multi-way switch are respectively connected with the two inputs of the arbiter module. Two total delay paths, namely a first total delay path and a second total delay path, are formed in the above mode. The same input signal is simultaneously input into the two paths of total delay paths, two paths of different total delay signals can be generated under the working condition,
the arbiter module generates a digital response of 0 or 1 based on the order of arrival of the total delay signals at the arbiter input port, thereby generating 2NAnd each excitation response pair.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (8)
1. A hybrid PUF circuit capable of extracting physical fingerprints of a chip and a circuit board is characterized by comprising
The Arbiter PUF circuit inside the chip: the system comprises an N-level switch delay module and an arbiter module, wherein the N-level switch delay module can generate two paths of in-chip delay signals;
delay circuit outside the chip: the chip comprises an off-chip symmetrical delay module capable of generating two paths of off-chip delay signals, and an arbiter module which inputs two paths of total delay signals obtained by superposing the off-chip delay signals and the on-chip delay signals into the chip; the arbiter module generates digital responses according to the sequence of the two paths of total delay signals arriving at the input port of the arbiter.
2. The hybrid PUF circuit capable of extracting the physical fingerprints of the chip and the circuit board as claimed in claim 1, wherein the N-stage switching delay module comprises N cascaded two-out-of-two multi-way switching stages, the N cascaded multi-way switches form two delay paths including a first delay path and a second delay path under the control of an N-bit excitation signal C, and N is a positive integer greater than or equal to 1.
3. The hybrid PUF circuit capable of extracting physical fingerprints of chips and circuit boards as claimed in claim 2, wherein the off-chip symmetric delay modules are two-way, and include a first symmetric delay module and a second symmetric delay module, when N multi-way switches are greater than or equal to 1, the first delay path and the second delay path are outputs of the Nth multi-way switch, one end of the first symmetric delay module and one end of the second symmetric delay module are respectively connected to the first delay path and the second delay path, and the other end of the first symmetric delay module and the other end of the second symmetric delay module are respectively connected to two-way inputs of the arbiter module.
4. The hybrid PUF circuit capable of extracting physical fingerprints of chips and circuit boards as claimed in claim 2, wherein the off-chip symmetric delay modules are two-way, and include a first symmetric delay module and a second symmetric delay module, when N multi-way switches are greater than or equal to 2, the first delay path and the second delay path are outputs of a J-th multi-way switch, where J is a positive integer and 0< J < N, and when one end of the first symmetric delay module and one end of the second symmetric delay module are connected to the first delay path and the second delay path respectively, and the other end of the first symmetric delay module and the other end of the second symmetric delay module are connected to inputs of a J + 1-th multi-way switch, and two-way outputs of the N-th multi-way switch are connected to two-way inputs of the arbiter module respectively.
5. The hybrid PUF circuit capable of extracting the physical fingerprints of the chip and the circuit board according to claim 3, wherein two ends of the first symmetric delay module and the second symmetric delay module are connected in series between the N-stage switch delay module and the arbiter module through Pad pins; n-stage switch delay module passes through chip pin Pad1And Pad2Connected with an external delay module, the delay module outside the chip is connected with the external delay module through a chip pin Pad3And Pad4Connected to the arbiter module.
6. The hybrid PUF circuit capable of extracting the physical fingerprints of the chip and the circuit board as claimed in claim 4, wherein two ends of the first symmetric delay module and the second symmetric delay module are both connected in series between the J-th stage switch delay module and the J + 1-th stage switch delay module through Pad pins; n-stage switch delay module passes through chip pin Pad1、Pad2、Pad3And Pad4UConnected to the off-chip symmetric delay module.
7. A method for extracting a hybrid PUF circuit for extracting physical fingerprints of chips and circuit boards according to claim 3, comprising:
step 1, when an N-bit binary excitation signal C is input, N multi-way switches in an N-stage switch delay module inside a chip form two delay paths, namely a first delay path and a second delay path, under the control of the N-bit excitation signal C.
Step 2, the output of the two paths of delay paths passes through a chip pin Pad1And Pad2And the two paths of total delay paths, namely the first total delay path and the second total delay path, are formed by the way. The same input signal is simultaneously input into the two paths of total delay paths, two paths of different total delay signals can be generated under the working condition, and the two paths of different total delay signals pass through a chip pin Pad3And Pad4Input to an arbiter module inside the chip,
step 3, the arbiter module generates digital responses 0 or 1 according to the sequence of the total delay signals on the two delay paths reaching the input port, thereby generating 2NAnd each excitation response pair.
8. The method for extracting the hybrid PUF circuit capable of extracting the physical fingerprints of the chip and the circuit board according to claim 4, comprising the following steps:
step 1, when an N-bit excitation signal C is input, the J multi-way switches form two delay paths, namely a first delay path and a second delay path, under the control of the excitation signal C.
Step 2, the output of the J-th multi-way switch of the N-stage switch delay module in the chip passes through a chip pin Pad1And Pad2Connected to external first and second symmetric delay blocks. The outputs of the external first and second symmetric delay modules pass through chip pins Pad3And Pad4And the two outputs of the Nth multi-way switch are respectively connected with the two inputs of the arbiter module. Two total delay paths, namely a first total delay path and a second total delay path, are formed in the above mode. The same input signal is simultaneously input into the two paths of total delay paths, two paths of different total delay signals can be generated under the working condition,
step 3, the arbiter module generates a digital response 0 or 1 according to the sequence of the total delay signals reaching the input port of the arbiter, thereby generating 2NAnd each excitation response pair.
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| CN114679277A (en) * | 2022-02-22 | 2022-06-28 | 湖北工业大学 | SR PUF-based reliability self-checking and reliable response depolarization method |
| CN115630408A (en) * | 2022-12-21 | 2023-01-20 | 湖北工业大学 | Safe extraction structure of PCB-chip mixed fingerprint |
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| CN115630408A (en) * | 2022-12-21 | 2023-01-20 | 湖北工业大学 | Safe extraction structure of PCB-chip mixed fingerprint |
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