CN113497634A - UWB (ultra wide band) technology wireless signal receiving circuit - Google Patents
UWB (ultra wide band) technology wireless signal receiving circuit Download PDFInfo
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- CN113497634A CN113497634A CN202010193590.XA CN202010193590A CN113497634A CN 113497634 A CN113497634 A CN 113497634A CN 202010193590 A CN202010193590 A CN 202010193590A CN 113497634 A CN113497634 A CN 113497634A
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- mos tube
- circuit
- uwb
- wireless signal
- signal receiving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides a UWB (ultra-wideband) technology wireless signal receiving circuit, which comprises an antenna, a low-noise amplifier, a sample-and-hold circuit, an integrating circuit and an analog-to-digital conversion circuit which are sequentially connected; the antenna is connected with the input end of the low noise amplifier; the sampling hold circuit comprises a first MOS tube, a sampling capacitor and a second MOS tube which are connected in sequence; the output end of the low-noise amplifier is connected with the drain electrode of the first MOS tube; the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube; the sampling capacitor is simultaneously connected with the source electrode of the first MOS tube and the drain electrode of the second MOS tube; the source electrode of the second MOS tube is connected with the integrator; the output end of the integrator is connected with the analog-to-digital converter, and the wireless signal receiving circuit is simple in structure and easy to integrate.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a wireless communication signal receiving circuit.
Background
The UWB technology has great advantages in the application field of high-speed short-distance communication, and has narrow pulse signals, small energy and large information capacity. Because the pulse signal duration is in picosecond level, a sampling circuit is needed to maintain the signal during signal receiving and facilitate subsequent processing. The present invention provides a sampling circuit with simple structure, which can be applied to a UWB receiving circuit.
Disclosure of Invention
The invention provides a UWB ultra wide band technology wireless signal receiving circuit for achieving the purpose of simplifying the circuit structure, which is characterized by comprising an antenna, a low noise amplifier, a sampling hold circuit, an integrating circuit and an analog-to-digital conversion circuit which are connected in sequence;
the antenna is connected with the input end of the low noise amplifier;
the sampling hold circuit comprises a first MOS tube, a sampling capacitor and a second MOS tube which are connected in sequence;
the output end of the low-noise amplifier is connected with the drain electrode of the first MOS tube;
the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube;
the sampling capacitor is simultaneously connected with the source electrode of the first MOS tube and the drain electrode of the second MOS tube;
the source electrode of the second MOS tube is connected with the integrator;
and the output end of the integrator is connected with the analog-to-digital converter.
In a preferred real-time scheme, the first MOS transistor and the second MOS transistor are PMOS transistors.
In a preferred real-time scheme, the output end of the analog-to-digital converter is connected with a baseband processor.
In a preferred real-time scheme, the integrator comprises a power amplifier and an integrating capacitor connected in parallel between the inverting input and the output of the power amplifier.
According to the scheme, the first MOS tube, the second MOS tube and the capacitor are arranged as a sampling circuit, signals enter the capacitor through the low-noise amplifier, the first MOS tube and the second MOS tube are controlled through the time sequence control circuit, the first MOS tube is switched on and the second MOS tube is switched off at the received time sequence, the first MOS tube is switched off and the second MOS tube is switched on outside the received time sequence, meanwhile, the integrator outputs an integration signal to the analog-to-digital converter, and the output end of the analog-to-digital converter transmits the digital signal to the baseband processor. Compared with the prior art, the scheme has a simple structure and is easy to integrate.
Drawings
Fig. 1 is a schematic diagram of a prior art UWB transceiver circuit topology.
Fig. 2 is a schematic diagram of a structure of a UWB ultra-wideband wireless signal receiving circuit.
Detailed Description
Referring to fig. 1, a schematic diagram of a topology of a UWB wireless signal transceiver circuit in the prior art is shown, and the present invention improves a receiving circuit in the topology. The circuit topology structure comprises an antenna, wherein the output end of the antenna is connected with a low-noise amplifier, and the output end of the low-noise amplifier is connected with a plurality of digital-to-analog converters. The output end of the digital-to-analog converter is connected with a digital correlator, the output end of the digital correlator is used as a receiving circuit, and the output signal of the digital correlator is used as the signal input source of the modem. The demodulated signal serves as a signal output terminal that serves as an input terminal of the baseband processor.
The power amplifier also comprises a transmitting circuit, wherein the transmitting circuit comprises a signal data input end which can also come from the baseband processor, the input signal enters the modulation module, and the output end of the modulation module is connected with the output end of the power amplifier and is connected with the antenna. Clock and codeword generation circuitry is also included.
Wherein the UWB correlation receiver is responsible for correlating the received signal with the desired impulse signal. The signal is first sampled directly, requiring a plurality of analog-to-digital (a/D) converters, each with a different offset in time, at a lower resolution and pulse repetition rate.
Referring to fig. 2, the present invention reduces the use of the AD converter using an integrator front end, and a sample-and-hold circuit is provided at the front end of the integrator to hold the pulse signal for subsequent processing.
Specifically, the UWB ultra-wideband wireless signal receiving circuit includes an antenna 102, a low noise amplifier 104, a sample-and-hold circuit (including devices 106, 108, and 110), an integrating circuit, and an analog-to-digital conversion circuit, which are connected in this order;
the antenna 102 is connected with the input end of the low noise amplifier 104;
the sampling hold circuit comprises a first MOS tube 106, a sampling capacitor 108 and a second MOS tube 110 which are connected in sequence;
the output end of the low noise amplifier is connected with the drain electrode of the first MOS tube 106;
the source electrode of the first MOS transistor 106 is connected to the drain electrode of the second MOS transistor 110;
the sampling capacitor is simultaneously connected with the source electrode of the first MOS tube 106 and the drain electrode of the second MOS tube 110;
the source electrode of the second MOS transistor 110 is connected with an integrator;
the output of the integrator is connected to an analog-to-digital converter 116.
According to the scheme, the first MOS tube 106, the second MOS tube 110 and the capacitor 108 are arranged to serve as sampling circuits, signals enter the capacitor 108 through the low noise amplifier, the first MOS tube 106 and the second MOS tube 108 are controlled through the timing control circuit, the first MOS tube 106 is connected and the second MOS tube 108 is disconnected in a receiving timing sequence, the first MOS tube 106 is disconnected and the second MOS tube 110 is closed outside the receiving timing sequence, meanwhile, the integrator outputs integration signals to the analog-to-digital converter 116, and the output end of the analog-to-digital converter transmits digital signals to the baseband processor. Compared with the prior art, the scheme has a simple structure and is easy to integrate.
In a preferred embodiment, the first MOS transistor 106 and the second MOS transistor 110 are PMOS transistors. It is obvious to those skilled in the art that an NMOS transistor may be used instead of the PMOS transistor, and the source of the first NMOS transistor is connected to the output terminal of the low noise amplifier, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor. The drain electrode of the second NMOS tube is connected with the source electrode of the first MOS tube, and the drain electrode of the second MOS tube is connected with the reverse input end of the integrator.
In a preferred embodiment, the output of the analog-to-digital converter 116 is connected to a baseband processor (not shown). The output end of the analog-to-digital converter is used as the input end of the baseband processor, and the baseband processor is used as the receiving end of communication data.
In a preferred embodiment, the integrator 114 includes a power amplifier and an integrating capacitor 112 connected in parallel between the inverting input terminal and the output terminal of the power amplifier.
When the receiving circuit works, a signal enters the low-noise amplifier 104 through the antenna, the low-noise amplifier has lower bottom noise 104, the low-noise amplifier amplifies the pulse wave, then the amplified pulse wave passes through the conducted first MOS tube and is stored in the capacitor 108, and the amplified pulse wave enters the integrator after being repeated for multiple times. In the subsequent timing, the first MOS transistor is turned off 106, and the second MOS transistor is turned on 110, and the signals are processed by the integrator and enter the analog-to-digital converter, that is, before analog-to-digital conversion, correlation is performed on N pulses, and the resolution can be increased to about log 2N.
Claims (4)
1. A UWB ultra-wideband technology wireless signal receiving circuit is characterized by comprising an antenna, a low-noise amplifier, a sample-and-hold circuit, an integrating circuit and an analog-to-digital conversion circuit which are connected in sequence;
the antenna is connected with the input end of the low noise amplifier;
the sampling hold circuit comprises a first MOS tube, a sampling capacitor and a second MOS tube which are connected in sequence;
the output end of the low-noise amplifier is connected with the drain electrode of the first MOS tube;
the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube;
the sampling capacitor is simultaneously connected with the source electrode of the first MOS tube and the drain electrode of the second MOS tube;
the source electrode of the second MOS tube is connected with the integrator;
and the output end of the integrator is connected with the analog-to-digital converter.
2. The UWB (UWB) wireless signal receiving circuit of claim 1 wherein the first MOS transistor and the second MOS transistor are PMOS transistors.
3. The UWB ultra wide band wireless signal receiving circuit of claim 2, wherein an output of the analog-to-digital converter is connected to the baseband processor.
4. The UWB ultra wide band wireless signal receiving circuit of claim 1, wherein the integrator comprises a power amplifier and an integrating capacitor connected in parallel between an inverting input terminal and an output terminal of the power amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010193590.XA CN113497634A (en) | 2020-03-18 | 2020-03-18 | UWB (ultra wide band) technology wireless signal receiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010193590.XA CN113497634A (en) | 2020-03-18 | 2020-03-18 | UWB (ultra wide band) technology wireless signal receiving circuit |
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| Publication Number | Publication Date |
|---|---|
| CN113497634A true CN113497634A (en) | 2021-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010193590.XA Withdrawn CN113497634A (en) | 2020-03-18 | 2020-03-18 | UWB (ultra wide band) technology wireless signal receiving circuit |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1669285A (en) * | 2002-10-01 | 2005-09-14 | 英特尔公司 | Method and apparatus to detect and decode information |
| CN1720672A (en) * | 2002-10-02 | 2006-01-11 | 阿蒂密有限公司 | Communication methods and apparatus |
| CN101079647A (en) * | 2006-05-27 | 2007-11-28 | 中国科学技术大学 | An ultra-wide frequency receiving method of pulse peak detection wave and its receiver |
| US20080266161A1 (en) * | 2007-04-30 | 2008-10-30 | Josef Zipper | Analog-to-digital converter, receiver arrangement, filter arrangement and signal processing method |
| CN101610096A (en) * | 2009-07-21 | 2009-12-23 | 江苏北方湖光光电有限公司 | A kind of simple ultra-broadband receiver circuit |
| US20180248575A1 (en) * | 2016-09-29 | 2018-08-30 | University Of Massachusetts | Wideband receiver architecture tolerant to in-band interference |
-
2020
- 2020-03-18 CN CN202010193590.XA patent/CN113497634A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1669285A (en) * | 2002-10-01 | 2005-09-14 | 英特尔公司 | Method and apparatus to detect and decode information |
| CN1720672A (en) * | 2002-10-02 | 2006-01-11 | 阿蒂密有限公司 | Communication methods and apparatus |
| CN101079647A (en) * | 2006-05-27 | 2007-11-28 | 中国科学技术大学 | An ultra-wide frequency receiving method of pulse peak detection wave and its receiver |
| US20080266161A1 (en) * | 2007-04-30 | 2008-10-30 | Josef Zipper | Analog-to-digital converter, receiver arrangement, filter arrangement and signal processing method |
| CN101610096A (en) * | 2009-07-21 | 2009-12-23 | 江苏北方湖光光电有限公司 | A kind of simple ultra-broadband receiver circuit |
| US20180248575A1 (en) * | 2016-09-29 | 2018-08-30 | University Of Massachusetts | Wideband receiver architecture tolerant to in-band interference |
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Application publication date: 20211012 |