CN113497590A - Circuit for reducing noise of amplifier and negative impedance circuit - Google Patents
Circuit for reducing noise of amplifier and negative impedance circuit Download PDFInfo
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- CN113497590A CN113497590A CN202110363126.5A CN202110363126A CN113497590A CN 113497590 A CN113497590 A CN 113497590A CN 202110363126 A CN202110363126 A CN 202110363126A CN 113497590 A CN113497590 A CN 113497590A
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- transistor
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- operational amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
Abstract
The present invention provides a circuit comprising: a first operational amplifier having an inverting input and a non-inverting input; and a negative resistance circuit connected to an inverting input of the operational amplifier. The negative resistance circuit includes a second operational amplifier, a current source controlled by the second operational amplifier, and a cross-coupled transistor circuit having at least one transistor biased by a current generated by the current source. By using the technical scheme, the internal noise of the operational amplifier can be reduced, and the instability of the circuit can not be caused.
Description
Technical Field
The technology described herein relates generally to negative resistance circuits for reducing noise in operational amplifiers, for example, in audio applications.
Background
An operational amplifier (op-amp) is a widely used amplifier circuit. The operational amplifier has an "inverting (inverting) input" indicated by the symbol "-" and a non-inverting (non-inverting) input indicated by the symbol "+". The input of the operational amplifier has a high input impedance. The output of the operational amplifier has a low output impedance. One or more components may be connected between the input and the output. The operational amplifier uses feedback to drive the inverting and non-inverting inputs to the same voltage, also referred to as a virtual short.
Disclosure of Invention
The present invention provides a circuit comprising a first operational amplifier having an inverting input and a non-inverting input, and a negative resistance circuit connected to the inverting input of the first operational amplifier, the negative resistance circuit comprising: a second operational amplifier, a current source controlled by the second operational amplifier, and a cross-coupled transistor circuit having at least one transistor biased by a current generated by the current source.
Wherein at least one transistor has a source connected to the non-inverting input of the second operational amplifier.
The cross-coupled transistor circuit may include a first transistor and a second transistor. The gate of the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the drain of the first transistor.
The source of the first transistor and the source of the second transistor may be connected to a non-inverting input of the second operational amplifier.
The drain of the first transistor is connected to the inverting input of the first operational amplifier and the drain of the second transistor is connected to ground or a differential input.
The circuit may further include a second cross-coupled transistor circuit having at least one transistor biased by a current generated by a second current source controlled by a second operational amplifier.
The second cross-coupled transistor circuit may include a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to a drain of the fourth transistor and a gate of the fourth transistor is connected to a drain of the third transistor.
A source of the third transistor and a source of the fourth transistor may be connected to a non-inverting input of the second operational amplifier.
The circuit may further include a first impedance coupled between the third transistor and ground, and a second impedance coupled between the fourth transistor and ground.
The circuit may further include a first transistor and a second transistor, a source of the first transistor being connected to the inverting input of the second operational amplifier. The source of the second transistor is connected to the non-inverting input of the second operational amplifier. The gate of each of the first and second transistors is connected to a respective drain.
The circuit may further include a third current source controlled by the second operational amplifier and biasing the first transistor, and a fourth current source controlled by the second operational amplifier and biasing the second transistor.
The circuit may further include an impedance coupled between the first transistor and ground.
Wherein the drain of the second transistor is connected to ground.
The circuit may have an impedance connected between the source of the first transistor and the source of the second transistor.
The invention provides a negative resistance circuit, which can comprise an operational amplifier, a current source controlled by the operational amplifier and a cross-coupled transistor circuit; wherein the cross-coupled transistor circuit has at least one transistor biased by a current generated by a current source.
Wherein the source of the at least one transistor may be connected to the non-inverting input of the operational amplifier.
Wherein the cross-coupled transistor circuit may comprise a first transistor and a second transistor. A gate of the first transistor may be connected to a drain of the second transistor, and a gate of the second transistor may be connected to a drain of the first transistor.
Wherein the source of the first transistor and the source of the second transistor may be connected to a non-inverting input of the operational amplifier.
Wherein the negative resistance circuit may further include a first transistor and a second transistor, a source of the first transistor being connected to an inverting input of the operational amplifier. The source of the second transistor is connected to the non-inverting input of the operational amplifier. The gate of each of the first and second transistors is connected to a respective drain.
Wherein the negative resistance circuit may further include a third current source controlled by the operational amplifier and biasing the first transistor and a fourth current source. The fourth current source is controlled by the operational amplifier and biases the second transistor.
The foregoing summary is provided by way of example and is not intended to be limiting.
The circuit provided by the embodiment of the invention can reduce the internal noise of the operational amplifier.
Drawings
In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating various aspects of the techniques and apparatus described herein.
Fig. 1 shows that the internal noise of an operational amplifier can be modeled as a voltage source in series with the inverting input.
Fig. 2 shows the feedback factor β (beta) over a range of values of R3 normalized absolute values.
Fig. 3 illustrates an example of a negative resistance (negative resistance) circuit in accordance with some embodiments.
Fig. 4 illustrates an example of a negative resistance circuit using diode-connected transistors, according to some embodiments.
Fig. 5 illustrates an example of a complementary PMOS circuit according to some embodiments.
Fig. 6 illustrates an example of a negative resistance circuit using a diode-connected transistor and an explicit impedance (explicit impedance) Z, according to some embodiments.
Detailed Description
Internal noise of the operational amplifier (Op-amp) may appear in the output signal. Although operational amplifiers may be designed with reduced internal noise, doing so may increase power consumption. It is therefore desirable to use different techniques to reduce the internal noise present in the output signal.
Has already recognizedIt is appreciated that the shunt (shunt) negative resistance value between the inverting input and ground may at least partially cancel the operational amplifier's internal noise. FIG. 1 shows that internal noise can be modeled as a voltage source V in series with an inverting inputNI. The shunt negative resistance (-R3) produces a current of appropriate polarity that flows through resistor R2 to the output and at least partially cancels external noise.
One challenge with this approach is that the optimum value of the negative resistance for canceling the internal noise of the operational amplifier can cause the circuit to become unstable. Fig. 2 illustrates that the optimal normalized value of R3 is 0.5 and the feedback factor (β) becomes infinite (infinity) or negative infinity on either side of 0.5, indicating that the circuit is unstable when R3|, 0.5. Therefore, it is desirable to make the negative resistance value close to but not equal to the optimum value for eliminating the internal noise. One challenge in setting the negative resistance value close to a value that causes the circuit to be unstable is that variations in component values (PVT variations) due to process voltage or temperature (PVT) may cause the negative resistance value to drift to a value at which the circuit becomes unstable. Therefore, it is desirable that the negative resistance circuit is insensitive to PVT variations.
The circuit described herein produces small signal negative resistance values and is insensitive to PVT variations. In some embodiments, a constant-Gm cross-coupled transistor biased with either strong inversion (strong inversion) or weak inversion (weak inversion) may be included, where Gm represents transconductance.
Fig. 3 illustrates an example of a negative resistance circuit 100 according to some embodiments. Negative resistance circuit 100 includes a first cross-coupled transistor circuit 110, a second cross-coupled transistor circuit 120, an operational amplifier 130, and a current source circuit 140.
The first cross-coupled transistor circuit 110 may be connected to an inverting input of the operational amplifier of fig. 1, also referred to as a summing node Vs. The first cross-coupled transistor circuit 110 may be at a terminal VX0To the non-inverting input of operational amplifier 130. The first cross-coupled transistor circuit 110 includes a transistor 111, a source of the transistor 111 being connected to the terminal VX0And a drain connected to a summing node Vs. First crossThe coupled transistor circuit 110 further includes a transistor 112, a source of the transistor 112 being connected to the terminal VX0And the drain is connected to ground. Transistors 111 and 112 have a channel width W and a length L, with a ratio W/L. As shown in fig. 3, transistors 111 and 112 are cross-coupled, with the gate of one transistor connected to the drain of the other transistor. More specifically, the gate of the transistor 111 is connected to the drain of the transistor 112, and the gate of the transistor 112 is connected to the drain of the transistor 111. A current source 141 provides a bias current to the first cross-coupled transistor circuit 110, the current source 141 being controlled by the output of the operational amplifier 130. In some embodiments, the first cross-coupled transistor circuit 110 may be biased using a constant-Gm bias. The first cross-coupled transistor circuit 110 may be biased in either strong inversion (strong inversion) or weak inversion (weak inversion).
The second cross-coupled transistor circuit 120 may be at terminal VX1To the inverting input of operational amplifier 130. The second cross-coupled transistor circuit 120 includes a transistor 121, a source of the transistor 121 being connected to the terminal VX1And the drain is connected to impedance 123. The second cross-coupled transistor circuit 120 further includes a transistor 122, a source of the transistor 122 being connected to the terminal VX1And the drain connected to a resistance 124. The channel width to length ratio of transistors 121 and 122 is M times W/L. As shown in fig. 3, transistors 121 and 122 are cross-coupled, with the gate of one transistor connected to the drain of the other transistor. More specifically, the gate of the transistor 121 is connected to the drain of the transistor 122, and the gate of the transistor 122 is connected to the drain of the transistor 121. The current source 142 provides a bias current to the second cross-coupled transistor circuit 120, and the current source 142 is controlled by the output of the operational amplifier 130. In some embodiments, the second cross-coupled transistor circuit 120 may be biased using a constant-Gm bias. The second cross-coupled transistor circuit 120 may be biased in either strong or weak inversion.
The operational amplifier 130 converts VX1And VX0Maintained at the same voltage. The output of operational amplifier 130 controls current sources 142 and 141. Thus, the negative resistance circuit 100 maintains its (small signal) resistanceAnd is insensitive to PVT variations. In FIG. 3, IDMay be proportional to the difference between (Vgs-Vth) for the smaller NMOS and (Vgs-Vth) for the larger NMOS. Feedback loop makes IDHas this relationship with Vgs-Vth, so if this current I isDFor biasing the NMOS, then the NMOS Gm will remain constant, with the smaller NMOS comprising transistors 111 and 112 and the larger NMOS comprising transistors 121 and 122.
Although fig. 3 shows a single-ended version of the negative resistance circuit 100, a differential version of the negative resistance circuit may be used. For example, instead of connecting the drain of transistor 112 to ground, a differential signal may be provided between the drains of transistors 111 and 112.
Fig. 4 illustrates another example of a negative resistance circuit 200 according to some embodiments. An inverting input of operational amplifier 230 is connected to the source of transistor 221 and a non-inverting input of operational amplifier 230 is connected to the source of transistor 222. Each of the transistors 221 and 222 is diode-connected: their gates are connected to their drains. The width to length ratio of transistor 222 is W/L. The width to length ratio of transistor 221 is M times W/L. Operational amplifier 230 maintains the sources of transistors 221 and 222 at the same voltage. The transistor 221 is biased by a current source 241, the current source 241 being controlled by the output of the operational amplifier 230. Transistor 222 is biased by a current source 242, current source 242 being controlled by the output of operational amplifier 230. Transistor 221 is in series with impedance 225. Impedance 225 may be connected between the drain of transistor 221 and ground. The drain of transistor 222 may be coupled to ground. Transistors 221 and 222 may form a diode-connected (connected) replica (replacable) bias circuit that provides a constant-Gm bias. Such replica bias circuit may have the advantage of low power consumption. Another advance is that the feedback loop for constant-Gm bias can be isolated from the main feedback loop.
The cross-coupled transistor circuit 210 may be connected to the inverting input of the operational amplifier of fig. 1, also referred to as the summing node Vs. The cross-coupled transistor circuit 210 includes a transistor 211, the source of the transistor 211 being connected to a current source 243, and the drain being connected to a summing node Vs. The first cross-coupled transistor circuit 210 further includes a transistor 212, wherein a source of the transistor 212 is connected to the current source 243 and a drain of the transistor 212 is connected to the ground terminal. The channel width to length ratio of each of transistors 211 and 212 is K times W/L. As shown in fig. 4, transistors 211 and 212 are cross-coupled, with the gate of one transistor connected to the drain of the other transistor. More specifically, the gate of the transistor 211 is connected to the drain of the transistor 212, and the gate of the transistor 212 is connected to the drain of the transistor 211. A current source 243 provides bias current to the cross-coupled transistor circuit 210, the current source 243 being controlled by the output of the operational amplifier 230. In some embodiments, the cross-coupled transistor circuits 210 may be biased using a constant-Gm bias. The cross-coupled transistor circuit 210 may be biased in either strong or weak inversion.
An optional PMOS complementary circuit 250 may be included. Circuit 250 may enhance the overall (overall) Gm of cross-coupled transistors 211 and 212. The NMOS transistor may sink (sink) current and the PMOS transistor may push (push) current. If a PMOS device is also included, Gm will be doubled for the same current. Fig. 5 shows an example of a PMOS complementary circuit 250. If INN is grounded, INP sees an input impedance of-1/Gm, assuming that Gmp-Gmn-Gm. Points a, B, C and D in fig. 5 are connected to corresponding points in fig. 4 and 6.
Fig. 6 shows that alternatively an explicit impedance (Z) may be connected between the sources of the transistors 211 and 212 and/or between the sources of the transistors 221 and 222. If the sources of transistors 211 and 212 are separated by an impedance Z, the current source 243 may be split into two separate current sources 243a and 243b to bias transistors 211 and 212, respectively. As shown in fig. 6, the channel width to length ratio of transistor 222 is W/L, the channel width to length ratio of transistor 221 is M times W/L, and the channel width to length ratios of transistors 211 and 212 are K times W/L.
Other aspects
Various aspects of the devices and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description, and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.
Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the order in which a method is performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name.
The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Claims (20)
1. A circuit, comprising:
a first operational amplifier having an inverting input and a non-inverting input;
a negative resistance circuit connected to an inverting input of the first operational amplifier, the negative resistance circuit comprising:
a second operational amplifier;
a current source controlled by the second operational amplifier; and
a cross-coupled transistor circuit having at least one transistor biased by a current generated by the current source.
2. The circuit of claim 1, wherein a source of the at least one transistor is connected to a non-inverting input of the second operational amplifier.
3. The circuit of claim 1, wherein the cross-coupled transistor circuit comprises:
a first transistor; and
second transistor
Wherein a gate of the first transistor is connected to a drain of the second transistor, and a gate of the second transistor is connected to a drain of the first transistor.
4. The circuit of claim 3, wherein the source of the first transistor and the source of the second transistor are connected to a non-inverting input of the second operational amplifier.
5. The circuit of claim 4, wherein the drain of the first transistor is connected to the inverting input of the first operational amplifier, and wherein the drain of the second transistor is connected to ground or a differential input.
6. The circuit of claim 1 or 5, further comprising a second cross-coupled transistor circuit having at least one transistor biased by a current generated by a second current source controlled by the second operational amplifier.
7. The circuit of claim 6, wherein the second cross-coupled transistor circuit comprises:
a third transistor; and
a fourth transistor for controlling the output voltage of the first transistor,
wherein a gate of the third transistor is connected to a drain of the fourth transistor, and a gate of the fourth transistor is connected to a drain of the third transistor.
8. The circuit of claim 7, wherein a source of the third transistor and a source of the fourth transistor are connected to an inverting input of the second operational amplifier.
9. The circuit of claim 8, further comprising: a first impedance coupled between the third transistor and ground, and a second impedance coupled between the fourth transistor and ground.
10. The circuit of claim 1, wherein the negative resistance circuit further comprises:
a first transistor, wherein the source of the first transistor is connected with the inverting input of the second operational amplifier; and
a second transistor, a source of the first transistor being connected to a non-inverting input of the second operational amplifier,
wherein a gate of each of the first transistor and the second transistor is connected to a respective drain.
11. The circuit of claim 10, further comprising:
a third current source controlled by the second operational amplifier and biasing the first transistor; and
a fourth current source controlled by the second operational amplifier and biasing the second transistor.
12. The circuit of claim 11, further comprising: an impedance coupled between the first transistor and ground.
13. The circuit of claim 12, wherein the drain of the second transistor is connected to ground.
14. The circuit of claim 13, having an impedance connected between the source of the first transistor and the source of the second transistor.
15. A negative resistance circuit, comprising:
an operational amplifier;
a current source controlled by the operational amplifier; and
a cross-coupled transistor circuit having at least one transistor biased by a current generated by the current source.
16. The negative-resistance circuit of claim 15, wherein a source of the at least one transistor is connected to a non-inverting input of the operational amplifier.
17. The negative-resistance circuit of claim 15, wherein the cross-coupled transistor circuit comprises:
a first transistor; and
second transistor
Wherein the grid electrode of the first transistor is connected with the drain electrode of the second transistor, and the grid electrode of the second transistor is connected with the drain electrode of the first transistor.
18. The negative-resistance circuit of claim 17, wherein the source of the first transistor and the source of the second transistor are connected to a non-inverting input of the operational amplifier.
19. The negative-resistance circuit of claim 15, further comprising:
a first transistor, the source of which is connected with the inverting input of the operational amplifier; and
a second transistor having a source connected to a non-inverting input of the operational amplifier,
wherein a gate of each of the first transistor and the second transistor is connected to a respective drain.
20. The negative-resistance circuit of claim 19, further comprising:
a third current source controlled by the operational amplifier and biasing the first transistor; and
a fourth current source controlled by the operational amplifier and biasing the second transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/840,537 US11228283B2 (en) | 2019-04-08 | 2020-04-06 | Negative impedance circuit for reducing amplifier noise |
| US16/840,537 | 2020-04-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113497590A true CN113497590A (en) | 2021-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110363126.5A Pending CN113497590A (en) | 2020-04-06 | 2021-04-02 | Circuit for reducing noise of amplifier and negative impedance circuit |
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| CN (1) | CN113497590A (en) |
| TW (1) | TWI758155B (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4001735A (en) * | 1975-11-20 | 1977-01-04 | Northern Electric Company Limited | Single amplifier immittance network |
| FR2739936B1 (en) * | 1995-10-11 | 1997-11-14 | Snecma | DIFFERENTIAL CHARGE AMPLIFIER FOR PIEZOELECTRIC SENSOR |
| WO2003017487A1 (en) * | 2001-08-16 | 2003-02-27 | Koninklijke Philips Electronics N.V. | Ring oscillator stage |
| TW544995B (en) * | 2002-08-09 | 2003-08-01 | Advanic Technologies Inc | Flash A/D converter with new autozeroing and interpolation possessing negative impedance compensation |
| TWI305976B (en) * | 2005-12-30 | 2009-02-01 | Ind Tech Res Inst | Transimpedance amplifier using negative impedance compensation |
| KR100866705B1 (en) * | 2007-07-04 | 2008-11-03 | 주식회사 하이닉스반도체 | Semiconductor memory device with ferroelectric device |
| US9263997B2 (en) * | 2013-03-14 | 2016-02-16 | Quantance, Inc. | Self setting power supply using negative output impedance |
| US8963641B1 (en) * | 2013-03-15 | 2015-02-24 | Maxim Integrated Products, Inc. | Source-series terminated differential line driver circuit |
| WO2018076173A1 (en) * | 2016-10-25 | 2018-05-03 | 深圳市汇顶科技股份有限公司 | Amplitude-limit oscillation circuit |
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2021
- 2021-04-02 CN CN202110363126.5A patent/CN113497590A/en active Pending
- 2021-04-06 TW TW110112319A patent/TWI758155B/en active
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| Publication number | Publication date |
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| TWI758155B (en) | 2022-03-11 |
| TW202139591A (en) | 2021-10-16 |
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