CN113497454B - Fault ride-through control method for MMC-HVDC inner loop current controller - Google Patents
Fault ride-through control method for MMC-HVDC inner loop current controller Download PDFInfo
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- H—ELECTRICITY
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
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Abstract
The invention discloses a fault ride-through control method of an inner loop current controller of MMC-HVDC, which comprises the following steps: the SICC switches between the switch controller and the proportional-integral control loop according to a switching strategy related to the state; BBFC adopts a three-value bang-bang control signal, comprises the maximum positive and negative voltage output of MMC, and utilizes the maximum control energy of MMC; when MMC-HVDC is subjected to external disturbance so that the output current of the MMC-HVDC deviates from the original balance point, the control method is switched into a switch controller; the controller switches to a conventional continuous excitation controller when the MMC converter output current returns to near the original balance point. The invention fully develops the potential of the MMC converter control system in the early stage of transient oscillation of the power system, so that the output current of the MMC converter converges to the vicinity of the balance point at the highest speed, and then the power system is gradually stabilized at the original balance point through the traditional linear controller.
Description
Technical Field
The invention relates to the technical field of power automation control, in particular to a fault ride-through control method of an inner loop current controller of MMC-HVDC.
Background
MMC-HVDC transmission is the most advantageous compensation for HVDC transmission based on line commutated converters, MMC is a voltage source converter, which can provide frequency and voltage support for the external grid, and its fault ride through capability is crucial for robust and stable operation of the MMC-HVDC transmission system. The controller of the MMC can be divided into a linear controller and a nonlinear controller from the mathematical model. The VC-based fault ride-through strategy is designed based on linear control theory, where a tradeoff between response speed and overshoot of the controller must be considered, and thus the VC controller cannot utilize the full control capability of the MMC early in the fault. The nonlinear control technology is designed in modes of output feedback linearization, state feedback linearization and the like, and nonlinear dynamics of MMC are considered. However, the performance of such controllers is highly dependent on the accuracy of the system model, which is required for the design process or final control laws of the nonlinear controllers; at the same time, these nonlinear controllers often have complex structures, which prevent their widespread use.
The traditional switch control method obtains the control law by analyzing the maximum value of the derivative of the performance function, and the switch control law is obtained by calculating the state variable of the system, but the switch control method can furthest exert the performance of the controller to ensure that the dynamic state of the controlled system shows time optimality. For traditional switch control, when the order of a controlled system is very high, the Hamiltonian function of the system is very complex, and the switch controller is very difficult to obtain by solving the regular equation of the Hamiltonian function. At the same time, the conventional switch control does not break the switching behavior, which may adversely affect the system stability.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the invention provides a fault ride-through control method of an inner loop current controller of an MMC-HVDC, which fully develops the potential of an MMC converter control system in the early stage of transient oscillation of a power system, enables the output current of the MMC converter to converge to the vicinity of a balance point at the fastest speed, and then enables the power system to be asymptotically stabilized at the original balance point through a traditional linear controller.
A second object of the present invention is to provide a computer-readable storage medium.
It is a third object of the present invention to provide a computing device.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the invention provides a fault ride-through control method of an inner loop current controller of MMC-HVDC, which comprises the following steps:
setting a plurality of SICC controllers to control inner loop currents of a rectifier side MMC and an inverter side MMC in an MMC-HVDC power transmission system, wherein in each SICC controller, a BBFC controller operates in a switching mode with a PI inner loop current controller according to a switching rule related to a state;
operating the MMC-HVDC power transmission system in a normal working state, and setting external disturbance to the system to obtain real-time tracking errors of MMC output current and a reference value thereof;
the disturbance indicator judges whether the absolute value of the real-time tracking error of the MMC output current exceeds a set error threshold value or not, and judges whether the duration of exceeding the threshold value is larger than a set time threshold value or not;
when the absolute value of the real-time tracking error of the MMC output current is judged to be larger than a set first error threshold value, and the duration time of the absolute value larger than the threshold value is larger than a set first time threshold value, the switching signal generator outputs a switching signal T=1, and the switching fault ride-through controller switches the inner ring current control method into BBFC control;
when the absolute value of the real-time tracking error of the MMC output current is smaller than a set first error threshold value or the duration time of the real-time tracking error of the MMC output current is larger than the threshold value is smaller than a set first time threshold value, the switching signal generator outputs a switching signal T=0, and the switching fault ride-through controller switches the inner loop current control method into continuous PI control;
when the SICC is switched to BBFC control, the output of BBFC control comprises the maximum positive voltage output and the minimum negative voltage output of MMC and a steady-state value obtained during system balance, and when the SICC is switched to continuous PI control, asymptotic convergence of system output is realized through a continuous controller;
under BBFC control, when the absolute value of the real-time tracking error of the MMC output current is smaller than a set second error threshold value and the duration of the real-time tracking error smaller than the threshold value is larger than the set second time threshold value, the switching signal generator outputs a switching signal T=0, and the switching fault ride-through controller switches the inner loop current control method from BBFC control to continuous PI control.
As a preferable technical solution, according to the value of the switching signal T output by the switching signal generator, the control signal generated by the SICC controller is:
u sicc ＝T*u bbfc (t)+(1-T)*u pi (t)
wherein ,ubbfc (t) represents the output of BBFC, u pi And (t) represents the output of a PI control loop in the SICC controller.
As a preferred technical solution, the construction of the BBFC controller includes the following steps:
modeling the MMC converter by adopting an average value model, wherein the specific calculation formula is as follows:
C armi ＝C/N
C′ di ＝C di +2MC/N
wherein, xi epsilon { r, i } represents the variable of the rectifying side MMC or the inverting side MMC,
indicating the circulating current +.>
Representing the inter-electrode DC bus voltage, +.>
Representing the input index of the upper bridge arm->
Representing the input index of the lower bridge arm->
Representing the total capacitance voltage of the upper bridge arm, +.>
Representing the total capacitance voltage of the lower bridge arm, R i Representing parasitic arm resistance, L i Representing arm inductance, C representing submodule capacitance, N representing the number of submodules per bridge arm,/for each bridge arm>
Representing the output current +.>
Represents direct current, R dc Representing the resistance of the DC transmission line, C di Representing the installed dc bus capacitance, M representing the number of phases, etc.>
Representing active power output of MMC, S rate Indicating rated power +.>
Represents d-axis output current, +.>
Represents q-axis output current, L pui Representing arm inductance +.>
Representing the d-axis controller output voltage, +.>
Representing the q-axis controller output voltage;
the average model has
and />
Representing the d-axis component of the node voltage, ">
Is the q-axis component of the node voltage, R pui Representing parasitic arm resistance, ω s Representing a synchronization speed;
output current deviation of MMC converter
For output variable e, MMC converter output voltage +.>
For an input variable, the relative order r=1 of the output variable to the input variable is obtained;
and constructing a first-order BBFC controller for the MMC converter.
As a preferable technical solution, the control logic output of the first-order BBFC controller is expressed as:
where q (t) is the output of the control logic of the first order BBFC, e=y-y * Is the tracking error of the output variable y, y * Is the reference value of y, q old A value of q (t) representing the previous sampling interval, e + Represents the upper limit of tracking error, e - Represents the lower limit of the tracking error, v represents the logical operation or, # represents the logical operation and.
As a preferable technical solution, the BBFC control signal of the d-axis output current of the rectifying side MMC is:
wherein ,
d-axis component of the output voltage of the rectifying side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of d-axis component of output voltage of rectifying side MMC, < >>
The minimum value of the d-axis component of the voltage is outputted for the rectifying side MMC.
As a preferable embodiment, the BBFC control signal of the q-axis output current of the rectifying side MMC is:
wherein ,
q-axis component of the output voltage of the rectifying side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of q-axis component of output voltage of rectifying side MMC, < >>
The minimum value of the q-axis component of the voltage is outputted for the rectifying side MMC.
As a preferable technical solution, the BBFC control signal of the d-axis output current of the inversion side MMC is:
wherein ,
d-axis component of output voltage of MMC at inversion side, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of d-axis component of output voltage of MMC at inversion side, < >>
The minimum value of the d-axis component of the voltage is outputted for the inversion side MMC.
As a preferable embodiment, the BBFC control signal of the q-axis output current of the inversion side MMC is:
wherein ,
q-axis component of output voltage for inversion side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of q-axis component of output voltage of inversion side MMC, < >>
The minimum value of the q-axis component of the voltage is outputted for the inversion side MMC.
In order to achieve the second object, the present invention adopts the following technical scheme:
a computer-readable storage medium storing a program which, when executed by a processor, implements the above-described method of controlling fault ride-through of an inner loop current controller of MMC-HVDC.
In order to achieve the third object, the present invention adopts the following technical scheme:
a computing device comprising a processor and a memory for storing a program executable by the processor, said processor implementing an inner loop current controller fault ride-through control method as described above for MMC-HVDC when executing the program stored by the memory.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) The SICC provided by the invention can not only utilize the maximum control energy of the MMC converter, but also provide asymptotic convergence performance for system output, and in the initial stage of transient oscillation of the power system, the BBFC can accelerate the rebalancing process between energy generation and consumption, so that the output current of the MMC converges to a certain critical area near the balance point at the highest speed; and then switching to a conventional vector controller, exerting the optimality of the conventional vector controller near a balance point, enabling the system to be asymptotically stabilized to an original balance point, solving the technical problem that the conventional vector controller is slow in response at the initial stage of transient oscillation of the power system, not only providing maximum support for the recovery of an external power system, but also providing ideal performance in the aspect of restraining an oscillation mode during balance.
(2) The design of the switch controller based on logic operation only needs the relative order information of the system, but does not need the accurate parameters and models of the system, solves the technical problem that the traditional switch control method realizes the control rule by depending on the state variable of the system, and achieves the technical effect that the designed switch controller shows strong robustness to the change of the running condition of the system.
(3) The switch controller provided by the invention only comprises logic operation, so that the phase lag between the output and the input of the switch controller is smaller than that of a conventional vector controller, therefore, the switch controller can respond to the oscillation of MMC-HVDC output current more quickly, and meanwhile, the output of the controller only has three values, thereby facilitating the transmission of control signals, solving the technical problem that the conventional vector controller needs to consider the compromise between the response speed and the overshoot of the controller, and achieving the technical effect of quick response to the system oscillation.
(4) The invention adopts the technical scheme of the switch controller with steady-state value output, solves the technical problem of the non-disconnection switch behavior of the traditional switch control, and achieves the technical effect that the switch control can operate under the steady-state condition of the system.
(5) The technical scheme of the switching rule related to disturbance influence is adopted, BBFC can be triggered under the condition of serious disturbance, and when the tracking error of current output is converged within a preset time interval, the PI current controller is opened, so that the technical problem of frequent switching between the two controllers is solved, and the technical effect of being beneficial to the robust and stable operation of MMC is achieved.
(6) The application of the invention in MMC-HVDC control can greatly improve the transient stability of the operation of a large-scale alternating-direct current series-parallel power system.
Drawings
Fig. 1 is a schematic diagram of an MMC-HVDC power transmission system controlled by a SICC controller in accordance with the present invention;
fig. 2 is a schematic diagram of a switching rule of SICC according to the present invention;
fig. 3 is a schematic layout of a single area power test system with an MMC-HVDC transmission system in accordance with the present invention;
FIG. 4 (a) is a dynamic comparison chart of the d-axis output voltage reference value of the rectifying side MMC according to the present invention;
FIG. 4 (b) is a dynamic comparison diagram of the q-axis output voltage reference value of the rectifying side MMC according to the present invention;
FIG. 4 (c) is a dynamic comparison chart of the d-axis output current deviation of the rectifying side MMC according to the present invention;
FIG. 4 (d) is a dynamic comparison chart of the current deviation of the rectifying side MMC q-axis output current in the present invention;
FIG. 4 (e) is a dynamic comparison chart of DC voltage deviation of the rectifying side MMC in the present invention;
FIG. 4 (f) is a dynamic comparison chart of voltage deviation of the rectifying side MMC AC terminal in the present invention;
FIG. 4 (g) is a dynamic comparison chart of the d-axis output voltage reference value of the inversion side MMC in the present invention;
FIG. 4 (h) is a dynamic comparison chart of the q-axis output voltage reference value of the inversion side MMC in the present invention;
FIG. 4 (i) is a dynamic comparison chart of the deviation of the d-axis output current of the inversion side MMC in the present invention;
FIG. 4 (j) is a dynamic comparison chart of the output current deviation of the q-axis of the inversion side MMC in the present invention;
FIG. 4 (k) is a dynamic comparison chart of the active power deviation outputted by the MMC on the inversion side in the present invention;
FIG. 4 (l) is a dynamic comparison chart of voltage deviation of the AC end of the inversion side MMC in the present invention;
fig. 5 is a schematic layout of a four-machine thirteen-bus power test system with an MMC-HVDC transmission system in accordance with the present invention;
FIG. 6 (a) is a dynamic comparison diagram of the DC voltage of the rectifying side MMC in the present invention;
FIG. 6 (b) is a dynamic comparison diagram of the voltage at the AC end of the rectifying side MMC according to the present invention;
FIG. 6 (c) is a dynamic comparison diagram of the d-axis output current of the rectifying side MMC according to the present invention;
FIG. 6 (d) is a graph showing the dynamic comparison of the output current of the rectifying side MMC q-axis according to the present invention;
FIG. 6 (e) is a dynamic comparison chart of the d-axis output voltage reference value of the rectifying side MMC according to the present invention;
FIG. 6 (f) is a dynamic comparison diagram of the q-axis output voltage reference value of the rectifying side MMC according to the present invention;
FIG. 7 (a) is a dynamic comparison diagram of the active power output by the inversion side MMC in the present invention;
FIG. 7 (b) is a dynamic comparison diagram of the voltage at the AC end of the inversion side MMC according to the present invention;
FIG. 7 (c) is a graph showing the dynamic comparison of the d-axis output current of the inversion side MMC according to the present invention;
FIG. 7 (d) is a graph showing the dynamic comparison of the q-axis output current of the inverter-side MMC according to the present invention;
FIG. 7 (e) is a dynamic comparison chart of the d-axis output voltage reference value of the inversion side MMC according to the present invention;
fig. 7 (f) is a dynamic comparison diagram of the q-axis output voltage reference value of the inversion side MMC in the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
The embodiment provides a fault ride-through control method of an inner loop current controller of MMC-HVDC, which comprises the following steps:
s1: as shown in fig. 1, the rectifying side MMC adopts direct current voltage control and alternating current voltage control, the inverting side MMC adopts active power control and alternating current voltage control, which are both double-loop control structures, the outer loop adopts conventional VC control, and the inner loop adopts SICC control;
adopting four SICC controllers to control inner loop current of a rectifier side MMC and an inverter side MMC in an MMC-HVDC power transmission system, wherein in each SICC, a BBFC controller operates in a switching mode with a PI inner loop current controller according to a switching rule related to a state;
s2: firstly, operating an MMC-HVDC power transmission system in a normal working state, and setting external disturbance to the system to obtain real-time tracking error of MMC output current and a reference value thereof
S3: as shown in FIG. 2, the disturbance indicator determines whether the absolute value of the MMC output current deviation exceeds τ 1y (τ 1y Is a threshold value, exceeding the threshold value indicates that a disturbance has occurred) and
whether or not the duration of (a) is greater than gamma 1y Second, wherein the second is;
s4: when the absolute value of the MMC output current deviation exceeds tau 1y And is also provided with
Duration of (a) is greater than gamma 1y In seconds, the switching signal generator outputs a switching signal t=1, and the switching failure ride-through controller (SICC) switches the inner loop current control method to BBFC control. When the absolute value of the MMC output current deviation does not exceed tau 1y or />
Duration of less than gamma 1y In seconds, the switching signal generator outputs a switching signal t=0, and the switching fault ride-through controller (SICC) switches the inner loop current control method to normalContinuous PI control is performed;
s5: when the SICC is switched to BBFC control, the BBFC control obtains a corresponding control signal according to the control logic, and the output of the BBFC control comprises three values, namely the maximum positive voltage output of the MMC
And minimum negative voltage output
And steady state values obtained at system equilibrium +.>
The positive maximum value and the negative minimum value represent the maximum control capacity of the MMC, and the BBFC controls the MMC to the maximum degree through the capacity, so that the output current of the MMC converges to a certain critical area near the balance point at the highest speed, and the BBFC control can also operate under the steady state condition of the system due to the steady state value output; when the SICC is switched into the conventional continuous PI control, the asymptotic convergence of the system output is realized through a continuous controller;
s6: under BBFC control, when the absolute value of the MMC output current deviation is smaller than tau 2y And is also provided with
Duration of (a) is greater than gamma 2y In seconds, the switching signal generator outputs a switching signal t=0, and the switching failure ride-through controller (SICC) switches the inner loop current control method from BBFC control to conventional continuous PI control.
Referring to fig. 2, a switching rule is generated in a disturbance indicator and a switching signal generator, wherein the upper half part of the diagram is a schematic diagram of the disturbance indicator, and the lower half part of the diagram is a schematic diagram of the switching signal generator;
in the disturbance indicator, |e| is the absolute value of the control target y tracking error, τ 1y Is a threshold value, exceeding which indicates the occurrence of disturbance, K y To adjust the gain value of BBFC trigger speed, τ 2y For a threshold below which the integrator clears port c=1, the integratorThe output is reset to zero, the comparator outputs a 1 when input a is greater than input B, DBlk is the blocking signal of MMC, and MMC is blocked when dblk=0. χ=1 means |e| > τ 1y Duration of (a) is greater than gamma 1y Second, wherein the second is;
in the switching signal generator, the JK flip-flop module generates a signal q=1 when the clearing port C senses the χ boost signal, and the initial value of Q is 0. When χ=1, the integrator is reset to 0, t=1. When χ decreases from 1 to 0, the output of the integrator begins to increase. Until the output of the integrator covers gamma 2y When t=0. The control signal generated by SICC is, depending on the value of T:
u sicc ＝T*u bbfc (t)+(1-T)*u pi (t)
wherein ubbfc (t) is the output of BBFC, u pi And (t) is the output of the PI control loop in the SICC.
In this embodiment, the design of the BBFC controller includes the steps of:
s1, modeling an MMC converter by adopting the following average value model:
where ζ ε { r, i } represents the variable of the rectifying side MMC or the inverting side MMC,
represents the circulating current in amperes, +.>
Representing the voltage of the direct current bus between poles in volts, < >>
Is the input index of the upper bridge arm->
Representing the input index of the lower bridge arm->
Representing the total capacitance voltage of the upper bridge arm in volts, < >>
Representing the total capacitance voltage of the lower bridge arm in volts, R i Represents parasitic arm resistance, with the unit of omega, L i Represents arm inductance, the unit is H, C armi C/N, C represents the submodule capacitance in F, N is the submodule number per bridge arm, +.>
Is the output current in amperes, +.>
Indicating the direct current in amperes, < >>
R dc Is the resistance of the direct current transmission line, and the unit is omega, C' di ＝C di +2MC/N，C di Representing the installed DC bus capacitance, M is the number of phases, ">
Representing active power output in MMC in p.u. units, S rate Is the rated power chosen for the whole system, +.>
Represents d-axis output current in p.u., is +.>
Represents q-axis output current in p.u., L pui Arm inductance in p.u., is +.>
Represents the d-axis controller output voltage in p.u., the +.>
Represents the q-axis controller output voltage in p.u., wherein the average model used here has +.>
and />
Is the d-axis component of the node voltage in p.u., is>
Is the q-axis component of the node voltage in p.u., R pui Represents parasitic arm resistance in p.u., and ω s The synchronization speed of the whole system in p.u. units is indicated. d-axis of dq rotation reference frame and node voltage vector implemented by phase-locked loop +.>
Aligned so that it has
and />
S2, outputting current deviation by using MMC converter
For output variable e, MMC converter output voltage +.>
For an input variable, the relative order r=1 of the output variable to the input variable is obtained;
s3, designing a first-order BBFC controller for the MMC converter.
In this embodiment, the first order logic switch controller generates a control signal based on a logic operation, and the control logic thereof is:
where q (t) is the output of the control logic of the first order BBFC, e=y-y * Is the tracking error of the output variable y, y * Is the reference value of y, q old A value of q (t) representing the previous sampling interval, e + Represents the upper limit of tracking error, e - Represents the lower limit of tracking error, v represents the logical operation "or", and Λ represents the logical operation "and".
In this embodiment, the BBFC control signal for controlling the d-axis output current of the rectifying side MMC is:
wherein 
D-axis component of the output voltage of the rectifying side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of d-axis component of output voltage of rectifying side MMC, < >>
The minimum value of the d-axis component of the voltage is outputted for the rectifying side MMC.
In this embodiment, the BBFC control signal that controls the q-axis output current of the rectifying side MMC is:
wherein 
Q-axis component of the output voltage of the rectifying side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of q-axis component of output voltage of rectifying side MMC, < >>
The minimum value of the q-axis component of the voltage is outputted for the rectifying side MMC.
In the present embodiment, the BBFC control signal that controls the d-axis output current of the inversion side MMC is as follows:
wherein 
D-axis component of output voltage of MMC at inversion side, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
outputting electricity for inversion side MMCMaximum value of d-axis component of pressure, +.>
The minimum value of the d-axis component of the voltage is outputted for the inversion side MMC.
In the present embodiment, the BBFC control signal that controls the q-axis output current of the inverter side MMC is as follows:
wherein 
Q-axis component of output voltage for inversion side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of q-axis component of output voltage of inversion side MMC, < >>
The minimum value of the q-axis component of the voltage is outputted for the inversion side MMC.
In order to test the performance of the proposed SICC, simulation studies were performed on a two-machine Power System (PSCAD) and a two-zone four-machine thirteen-bus power system (Matlab), respectively.
Case one: fault ride-through control of MMC-HVDC power transmission system in two-machine electric power test system
First, the performance of the proposed SICC was tested with a single area power system with MMC-HVDC transmission system. As shown in fig. 3, a layout of the test system is constructed, and ac power sources at two ends are interconnected through an MMC-HVDC dc path to form an ac-dc-ac circuit, wherein steady-state power flows and system parameters are marked. MMC-Parameters of the HVDC transmission system are selected as follows: f (f) n ＝60Hz，M＝3，N＝76，S rate ＝1000MVA，
C arm =2800 μf, r=0.005 Ω, l=50mh. For comparison, simulation results of a test system controlled by VC are given. The parameters of VC are selected as follows: alpha d ＝5，α id ＝4，K Pod ＝4，K Iod ＝20，K Poq ＝1，K Ioq ＝10，K Pid ＝0.65，K Iid ＝100，K Piq ＝0.65，K Iiq =100. The same parameters are also used for PI controllers in control systems with SICCs.
As shown in fig. 3, in the case that a three-phase ground fault of 0.1s occurs at t=2s in the node 1 of the test system, as shown in fig. 4 (a) -4 (f), simulation results of the system for obtaining SICC and VC control are shown in the following table 1, and parameters of four SICCs are selected.
TABLE 1SICC control parameters table (case one)
As for the rectifying side MMC, as shown in fig. 4 (e), a tracking error of the voltage of the DC transmission line is obtained, and it can be seen that the fluctuation and deviation are small in the system controlled by SICC. This is mainly because BBFC of SICC in the d-axis control loop is triggered and a switching control signal is generated to suppress the balance between input and output power of the rectifying side MMC, as shown in fig. 4 (a).
As shown in fig. 4 (f), in SICC and VC control, the voltage amplitude of node 1 has similar dynamic characteristics. As shown in figure 4 (b) of the drawings,
in the dynamic diagram of (1), BBFC of SICC in the q-axis control loop is not started. Errors of d-axis and q-axis output currents of the rectifying side MMC controlled by SICC and VC are shown in fig. 4 (c) and 4 (d), respectively. In SICC and VC control, current trackingThe errors are similar. As shown in fig. 4 (k), the superior performance of the dc voltage of the rectifying side MMC controlled by the SICC is also due to the better active power control of the inverting side MMC.
Since a large power is outputted by the switching control signal shown in fig. 4 (g) in the post-failure recovery process, the control capability of the inversion side MMC is fully explored, and the fluctuation obtained in the active power output of the inversion side MMC controlled by the SICC is small. In turn, it applies less interference to the dc voltage and the ac terminal voltage of node 2. As shown in fig. 4 (l), wherein the dotted line is equipped with only conventional VC, the solid line is the system dynamics employing the SICC switching control method, and the voltage of node 2 in the system controlled by VC shows oscillations of a larger magnitude than SICC control. As shown in fig. 4 (i) and 4 (j), in the system controlled by SICC, the tracking error of the d-axis and q-axis output currents of the inversion side MMC is smaller than that of the system controlled by VC. This is due to the co-action of the d-axis control loop and the q-axis control loop.
As shown in fig. 4 (h), the BBFC of the SICC in the q-axis control loop is not triggered during the post-failure recovery.
Case two: fault ride-through control of MMC-HVDC power transmission system in two-zone four-motor power test system
In addition to the two-machine test system, the present embodiment also evaluates the fault ride-through performance of an MMC-HVDC transmission system controlled by SICCs in a four-machine thirteen-bus power test system. As shown in fig. 5, a test system structure is constructed, the original model is an IEEE four-machine thirteen-bus power system, and an MMC-HVDC power transmission system is connected between a bus 5 and a bus 6 to replace an original alternating current line. In the figure, the device symbol G represents generators, each generator is connected into a system through a transformer, L represents a load, C represents a grounding capacitor, and the number represents the bus number connected with the device. Parameters of the MMC-HVDC transmission system are selected as follows: m=3, n=180, s rate ＝900MVA，
V smax ＝400kV，I smax ＝1kA，L pu ＝0.08p.u.，R pu ＝0.008p.u.，C arm ＝9.375μF，C' d ＝100μF，C＝0.0017F，R dc = 3.058 Ω. For comparison, the VC parameters of an MMC-HVDC transmission system were chosen as: alpha d ＝50，α id ＝25，K Pod ＝1，K Iod ＝5，K Poq ＝1，K Ioq ＝5，K Pid ＝4，K Iid ＝80，K Piq ＝4，K Iiq ＝80，R a =20. The same parameters are also used by PI controllers of control systems with SICCs. Parameters of SICC were obtained as shown in table 2 below.
TABLE 2SICC control parameters table (case two)
As shown in fig. 6 (a) -6 (f), for the three-phase ground fault occurring on the node 2 of the four-machine thirteen-bus power test system, simulation results obtained in the case of the 0.1s three-phase ground fault occurring at t=0.1s at the node 2 are shown. For the rectifying side MMC, control signals generated by SICC and VC are as shown in fig. 6 (e) and 6 (f). It can be seen that during a failure, BBFC in SICC will generate a switch control signal. As shown in fig. 6 (c), the deviation of the d-axis output current of the system controlled by SICC is smaller than that of the system controlled by VC. This corresponds to a small tracking error of the dc voltage of the rectifying side MMC controlled by SICC, as shown in fig. 6 (a). Meanwhile, as shown in fig. 6 (d), the magnitude of the q-axis output current controlled by SICC is larger than that of the q-axis output current controlled by VC during the fault. This provides more reactive power support for the external ac grid, the ac terminal voltage of node 5 showing a higher altitude in the SICC controlled system, as shown in fig. 6 (b).
As shown in fig. 7 (a) -7 (f), simulation results of a three-phase ground fault occurring at the node 4 at t=0.1 s are given for a three-phase ground fault occurring at the node 4 of the four-machine thirteen-bus power test system. As for the inversion side MMC, as shown in fig. 7 (e) and 7 (f), control signals given by SICC and VC. After failure, the SICC control triggers BBFC. As shown in fig. 7 (c), the d-axis output current of the inversion side MMC controlled by the SICC provides a higher amplitude during a fault due to the switching control signal of the SICC. This will cause the active power output of the inverter to be greater, as shown in fig. 7 (a). Further, as shown in fig. 7 (d), the q-axis output current of the inverter controlled by SICC is also higher in magnitude than the q-axis output current controlled by VC. This results in the ac-terminal voltage in the system controlled by SICC being slightly higher than the ac-terminal voltage controlled by VC during failure, as shown in fig. 7 (b), where the dashed line is equipped with only conventional VC and the solid line is the system dynamics with SICC switching control method.
Example 2
The present embodiment provides a computer readable storage medium, which may be a storage medium such as a ROM, a RAM, a magnetic disk, or an optical disk, and the storage medium stores one or more programs that, when executed by a processor, implement the fault ride-through control method of the inner loop current controller of the MMC-HVDC of embodiment 1.
Example 3
The present embodiment provides a computing device, which may be a desktop computer, a notebook computer, a smart phone, a PDA handheld terminal, a tablet computer, or other terminal devices with display functions, where the computing device includes a processor and a memory, where the memory stores one or more programs, and when the processor executes the programs stored in the memory, the fault ride-through control method of the inner loop current controller of the MMC-HVDC of embodiment 1 is implemented.
The above examples are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above examples, and any other changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principle of the present invention should be made in the equivalent manner, and the embodiments are included in the protection scope of the present invention.
Claims (10)
1. The fault ride-through control method of the inner loop current controller of the MMC-HVDC is characterized by comprising the following steps of:
setting a plurality of SICC controllers to control inner loop currents of a rectifier side MMC and an inverter side MMC in an MMC-HVDC power transmission system, wherein in each SICC controller, a BBFC controller operates in a switching mode with a PI inner loop current controller according to a switching rule related to a state;
operating the MMC-HVDC power transmission system in a normal working state, and setting external disturbance to the system to obtain real-time tracking errors of MMC output current and a reference value thereof;
the disturbance indicator judges whether the absolute value of the real-time tracking error of the MMC output current exceeds a set error threshold value or not, and judges whether the duration of exceeding the threshold value is larger than a set time threshold value or not;
when the absolute value of the real-time tracking error of the MMC output current is judged to be larger than a set first error threshold value, and the duration time of the absolute value larger than the threshold value is larger than a set first time threshold value, the switching signal generator outputs a switching signal T=1, and the switching fault ride-through controller switches the inner ring current control method into BBFC control;
when the absolute value of the real-time tracking error of the MMC output current is smaller than a set first error threshold value or the duration time of the real-time tracking error of the MMC output current is larger than the threshold value is smaller than a set first time threshold value, the switching signal generator outputs a switching signal T=0, and the switching fault ride-through controller switches the inner loop current control method into continuous PI control;
when the SICC is switched to BBFC control, the output of BBFC control comprises the maximum positive voltage output and the minimum negative voltage output of MMC and a steady-state value obtained during system balance, and when the SICC is switched to continuous PI control, asymptotic convergence of system output is realized through a continuous controller;
under BBFC control, when the absolute value of the real-time tracking error of the MMC output current is smaller than a set second error threshold value and the duration of the real-time tracking error smaller than the threshold value is larger than the set second time threshold value, the switching signal generator outputs a switching signal T=0, and the switching fault ride-through controller switches the inner loop current control method from BBFC control to continuous PI control.
2. The method for controlling fault ride-through of an inner loop current controller for MMC-HVDC according to claim 1, wherein the control signal generated by the SICC controller according to the value of the switching signal T output by the switching signal generator is:
u sicc ＝T*u bbfc (t)+(1-T)*u pi (t)
wherein ,ubbfc (t) represents the output of BBFC, u pi And (t) represents the output of a PI control loop in the SICC controller.
3. The MMC-HVDC inner loop current controller fault ride-through control method according to claim 1, wherein the construction of the BBFC controller comprises the steps of:
modeling the MMC converter by adopting an average value model, wherein the specific calculation formula is as follows:
C armi ＝C/N
C′ di ＝C di +2MC/N
wherein, xi epsilon { r, i } represents the variable of the rectifying side MMC or the inverting side MMC,
indicating the circulating current +.>
Representing the inter-electrode DC bus voltage, +.>
Representing the input index of the upper bridge arm->
Representing the input index of the lower bridge arm->
Representing the total capacitance voltage of the upper bridge arm, +.>
Representing the total capacitance voltage of the lower bridge arm, R i Representing parasitic arm resistance, L i Representing arm inductance, C representing submodule capacitance, N representing the number of submodules per bridge arm,/for each bridge arm>
Representing the output current +.>
Representing direct current, C di Representing the installed dc bus capacitance, M representing the number of phases, etc.>
Representing active power output of MMC, S rate Indicating rated power +.>
The d-axis output current is indicated,
represents q-axis output current, L pui Representing arm inductance +.>
Representing the d-axis controller output voltage, +.>
Representing the q-axis controller output voltage;
the average model has
and />
Representing the d-axis component of the node voltage, ">
Is the q-axis component of the node voltage, R pui Representing parasitic arm resistance, ω s Representing a synchronization speed;
output current deviation of MMC converter
For output variable e, MMC converter output voltage +.>
For an input variable, the relative order r=1 of the output variable to the input variable is obtained;
and constructing a first-order BBFC controller for the MMC converter.
4. A method of fault ride-through control of an inner loop current controller for MMC-HVDC according to claim 3, wherein the control logic output of the first order BBFC controller is expressed as:
where q (t) is the output of the control logic of the first order BBFC, e=y-y * Is the tracking error of the output variable y, y * Is the reference value of y, q old A value of q (t) representing the previous sampling interval, e + Represents the upper limit of tracking error, e - Represents the lower limit of the tracking error, v represents the logical operation or, # represents the logical operation and.
5. The MMC-HVDC inner loop current controller fault ride-through control method according to claim 1, wherein the BBFC control signal of the d-axis output current of the rectifying side MMC is:
wherein ,
d-axis component of the output voltage of the rectifying side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of d-axis component of output voltage of rectifying side MMC, < >>
The minimum value of the d-axis component of the voltage is outputted for the rectifying side MMC.
6. The MMC-HVDC inner loop current controller fault ride-through control method according to claim 1, wherein the BBFC control signal of the q-axis output current of the rectifying side MMC is:
wherein ,
q-axis component of the output voltage of the rectifying side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of q-axis component of output voltage of rectifying side MMC, < >>
The minimum value of the q-axis component of the voltage is outputted for the rectifying side MMC.
7. The MMC-HVDC inner loop current controller fault ride-through control method according to claim 1, wherein the BBFC control signal of the d-axis output current of the inverter side MMC is:
wherein ,
d-axis component of output voltage of MMC at inversion side, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of d-axis component of output voltage of MMC at inversion side, < >>
The minimum value of the d-axis component of the voltage is outputted for the inversion side MMC.
8. The MMC-HVDC inner loop current controller fault ride-through control method according to claim 1, wherein the BBFC control signal of the q-axis output current of the inverter side MMC is:
wherein ,
q-axis component of output voltage for inversion side MMC, < >>
Is obtained at equilibrium point->
Is set to a steady state value of (1),
maximum value of q-axis component of output voltage of inversion side MMC, < >>
The minimum value of the q-axis component of the voltage is outputted for the inversion side MMC.
9. A computer readable storage medium storing a program, wherein the program when executed by a processor implements an inner loop current controller fault ride-through control method of MMC-HVDC according to any of claims 1-8.
10. A computing device comprising a processor and a memory for storing a processor executable program, wherein the processor, when executing the program stored in the memory, implements the inner loop current controller fault ride-through control method of the MMC-HVDC of any of claims 1-8.
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