CN113496874A

CN113496874A - Semiconductor structure and method for forming semiconductor structure

Info

Publication number: CN113496874A
Application number: CN202010252120.6A
Authority: CN
Inventors: 甘露; 郑春生; 师兰芳; 张文广; 张华�
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-04-01
Filing date: 2020-04-01
Publication date: 2021-10-12
Anticipated expiration: 2040-04-01

Abstract

A semiconductor structure and a forming method of the semiconductor structure are provided, wherein the method comprises the following steps: providing a layer to be etched; forming an initial first flat layer on the layer to be etched, wherein the initial first flat layer has a first thickness; forming an initial first mask layer on the initial first flat layer, wherein the initial first mask layer has a second thickness, and the second thickness is smaller than the first thickness; and forming a second mask layer on the initial first mask layer, wherein the second mask layer exposes a part of the surface of the initial first mask layer, and the second mask layer has a third thickness which is smaller than the first thickness. Thus, the performance of the semiconductor device is improved.

Description

Semiconductor structure and method for forming semiconductor structure

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for forming the semiconductor structure.

Background

With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance is improved along with the progress of miniaturization of devices. In more and more advanced processes, it is required to realize as many devices as possible in as small an area as possible.

In the advanced lithography process, Extreme Ultraviolet (EUV) light can be used as a light source, and the wavelength of the EUV light is short, so that a lithography pattern with a smaller critical dimension can be formed, more devices can be realized in a smaller area, and the integration level of a semiconductor device is improved.

However, the performance of semiconductor devices still needs to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of a semiconductor device.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: etching the layer to be etched; an initial first planarization layer on the layer to be etched, the initial first planarization layer having a first thickness; an initial first mask layer on the initial first planarization layer, the initial first mask layer having a second thickness, the second thickness being less than the first thickness; and the second mask layer is positioned on the initial first mask layer, the second mask layer exposes a part of the surface of the initial first mask layer, and the second mask layer has a third thickness which is smaller than the first thickness.

Optionally, the material of the initial first planarization layer comprises a carbon-containing organic material.

Optionally, the material of the initial first mask layer includes a carbon-containing organic material.

Optionally, the first thickness ranges from 150 nm to 300 nm.

Optionally, the second thickness is in a range of 30 nm to 100 nm.

Optionally, the third thickness is above 12 nm.

Optionally, the method further includes: an initial first stop layer between the initial first planarization layer and the initial first mask layer.

Optionally, the initial first stop layer has a fourth thickness, and the fourth thickness is smaller than the second thickness.

Optionally, the material of the initial first stop layer comprises a metal oxide.

Optionally, the fourth thickness is in the range of

Optionally, the material of the initial first stop layer comprises amorphous silicon.

Optionally, the fourth thickness is in a range of 5 nm to 10 nm.

Optionally, the material of the second mask layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a layer to be etched; forming an initial first flat layer on the layer to be etched, wherein the initial first flat layer has a first thickness; forming an initial first mask layer on the initial first flat layer, wherein the initial first mask layer has a second thickness, and the second thickness is smaller than the first thickness; and forming a second mask layer on the initial first mask layer, wherein the second mask layer exposes a part of the surface of the initial first mask layer, and the second mask layer has a third thickness which is smaller than the first thickness.

Optionally, the process of forming the initial first mask layer includes a deposition process.

Optionally, the process of forming the initial first planarization layer includes a spin-on process.

Optionally, the spin coating process includes the following process parameters: the film forming temperature is 400 ℃ or lower.

Optionally, the method for forming the second mask layer includes: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein part of the surface of the second mask material layer is exposed out of the photoresist pattern layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer is exposed.

Optionally, the method further includes: and etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first flat layer is exposed to form a first mask layer.

Optionally, the method further includes: etching the initial first flat layer by taking the first mask layer as a mask until the surface of the layer to be etched is exposed to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

Optionally, the method further includes: and before the initial first mask layer is formed, forming an initial first stop layer on the surface of the initial first flat layer.

Optionally, the method further includes: etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first stop layer is exposed to form a first mask layer; and etching the initial first stop layer by taking the first mask layer as a mask until the surface of the initial first flat layer is exposed to form a first stop layer.

Optionally, the method further includes: etching the initial first flat layer by taking the first stop layer as a mask until the surface of the layer to be etched is exposed to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

Optionally, the method further includes: and before etching the initial first stop layer, performing first thinning etching on the side wall of the first mask layer for more than 1 time.

Optionally, the method further includes: and before etching the initial first flat layer, performing second thinning etching on the side wall of the first stop layer for more than 1 time.

Optionally, the method further includes: after the initial first stop layer is formed, removing part of the initial first stop layer on the surface of the initial first flat layer to form a first stop layer; after the first stop layer is formed, forming a mask side wall on the surface of the side wall of the first stop layer; after the mask side wall is formed, removing the first stop layer; and after removing the first stop layer, etching the initial first flat layer by using the mask side wall as a mask until the surface of the layer to be etched is exposed to form a first flat layer.

Optionally, the method further includes: and etching the layer to be etched by taking the first flat layer as a mask.

Optionally, the method for forming the first stop layer includes: removing part of the initial first mask layer on the surface of the initial first stop layer to form a first mask layer; forming a first side wall on the side wall surface of the first mask layer; after the first side wall is formed, removing the first mask layer; and etching the initial first stop layer by taking the first side wall as a mask after the first mask layer is removed until the surface of the initial first flat layer is exposed.

Optionally, the method for forming the first mask layer includes: after the second mask layer is formed, forming second side walls on the side wall surfaces of the second mask layer; after the second side wall is formed, removing the second mask layer; and after the second mask layer is removed, etching the initial first mask layer by taking the second side wall as a mask until the surface of the initial first stop layer is exposed.

Optionally, the method for forming the second mask layer includes: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein part of the surface of the second mask material layer is exposed out of the photoresist pattern layer; forming a third side wall on the side wall of the photoresist pattern layer; after the third side wall is formed, removing the photoresist pattern layer; and after removing the photoresist pattern layer, etching the second mask material layer by taking the third side wall as a mask until the surface of the initial first mask layer is exposed.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the semiconductor structure provided by the technical scheme of the invention, the initial first flat layer is used for repairing the surface of the layer to be etched. The initial first mask layer is used for forming a first mask layer, and the second mask layer and the first mask layer are used for transferring the photoetching pattern of the photoetching adhesive layer so as to improve the stability of the photoetching pattern. In the photoetching process using extreme ultraviolet light as a light source, the photoresist layer is thinner. Because the third thickness is smaller than the first thickness, when the photoresist layer is used as a mask to etch the material layer of the second mask layer, the thinner material layer of the second mask layer can form the second mask layer before the photoresist layer is completely worn, and the transfer of the photoetching pattern under the extreme ultraviolet photoetching process is realized. Because the second thickness is smaller than the first thickness, on one hand, when the second mask layer is used as a mask to etch the initial first mask layer, the thinner initial first mask layer can form a first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first flat layer can enable the semiconductor structure to have higher flatness, and when the photoetching patterns are transferred to the layer to be etched through the initial first flat layer, the initial first mask layer and the second mask layer, the pattern precision in the transfer process is improved. In summary, with the semiconductor structure, while the integration degree is improved by the photolithography process for dealing with the extreme ultraviolet light, the pattern precision of the photolithography pattern in the transfer process can be increased to improve the performance of the semiconductor device.

Furthermore, because the semiconductor structure further comprises the initial first stop layer positioned between the initial first flat layer and the initial first mask layer, on one hand, when the initial first mask layer is etched, the initial first stop layer can protect the initial first flat layer and reduce the influence of the etching process for etching the initial first mask layer on the initial first flat layer, thereby improving the precision of the photoetching pattern transferred to the initial first flat layer; on the other hand, when the photoetching pattern transferred to the initial first mask layer is detected to have poor precision, and the initial first mask layer is removed and a new initial first mask layer is formed again, the influence of the process for removing the initial first mask layer on the initial first flat layer can be reduced through the initial first stop layer, so that the performance of the semiconductor device is improved.

Further, since the initial first stop layer has a fourth thickness, and the fourth thickness is smaller than the second thickness, the initial first stop layer with the smaller thickness forms the first stop layer, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase the process window of the etching process for etching the initial first flat layer, thereby improving the performance of the semiconductor device.

Correspondingly, in the method for forming the semiconductor structure provided by the technical scheme of the invention, the formed initial first flat layer is used for repairing the surface of the layer to be etched. The formed initial first mask layer is used for forming a first mask layer subsequently, and the first mask layer and the formed second mask layer are used for transferring the photoetching pattern of the photoetching adhesive layer so as to improve the stability of the photoetching pattern. In the photoetching process using extreme ultraviolet light as a light source, the photoresist layer is thinner. Because the third thickness is smaller than the first thickness, when the photoresist layer is used as a mask to etch the material layer of the second mask layer, the thinner material layer of the second mask layer can form the second mask layer before the photoresist layer is completely worn, and the transfer of the photoetching pattern under the extreme ultraviolet photoetching process is realized. Because the second thickness is smaller than the first thickness, on one hand, when the second mask layer is taken as a mask to etch the initial first mask layer in the subsequent process, the thinner initial first mask layer can form a first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first flat layer can enable the semiconductor structure to have higher flatness, and when the photoetching patterns are transferred to the layer to be etched through the initial first flat layer, the initial first mask layer and the second mask layer, the pattern precision in the transfer process is improved. In summary, through the formation method of the semiconductor structure, the pattern precision of the photoetching pattern in the transfer process can be increased while the integration degree is improved by the photoetching process of the extreme ultraviolet light, so as to improve the performance of the semiconductor device.

Further, the process for forming the initial first mask layer comprises a deposition process, and the deposition process is characterized in that the number of defects in a formed material layer is small, and the number of defects is less influenced by the thickness of the material layer, so that the defects in the initial first mask layer can be reduced when the initial first mask layer with small thickness is formed by adopting the deposition process, and the pattern precision of a photoetching pattern formed by the initial first mask layer in the follow-up process is improved.

Furthermore, the spin coating process has better filling performance, and the process for forming the initial first flat layer comprises the spin coating process, so that uneven parts on the layer to be etched can be better filled through the spin coating process, and the flatness of the initial first flat layer is further improved.

Further, the side wall of the first stop layer is subjected to second thinning etching, so that the critical dimension of the graph of the first stop layer can be reduced, and therefore the graph with smaller critical dimension can be formed on the layer to be etched, the design requirement of smaller critical dimension can be met, and the integration level of the semiconductor device is further improved.

Drawings

FIGS. 1-2 are schematic cross-sectional views of steps in a method of forming a semiconductor structure;

FIGS. 3-9 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

FIGS. 10-16 are cross-sectional structural illustrations of steps in a method of forming a semiconductor structure in accordance with another embodiment of the present invention;

fig. 17 to 22 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to yet another embodiment of the present invention.

Detailed Description

As described in the background, the performance of semiconductor devices still needs to be improved. The analysis will now be described with reference to specific examples.

It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1 to 2 are schematic cross-sectional views of steps of a method for forming a semiconductor structure.

Referring to fig. 1, a layer to be etched 10 is provided; forming an initial planarization layer 20 on the surface of the layer to be etched 10 by adopting a spin coating process; forming a masking material layer 30 on the surface of the initial planarization layer 20; a photoresist layer 40 is formed on the surface of the masking material layer 30, and the photoresist layer 40 exposes a portion of the surface of the masking material layer 30.

The method of forming the photoresist layer 40 includes: forming a photoresist material layer (not shown) on the surface of the mask material layer 30; and carrying out exposure and development processes on the photoresist material layer. Wherein, the light source of the exposure process is extreme ultraviolet light.

Referring to fig. 2, the photoresist layer 40 is used as a mask to etch the mask material layer 30 until the surface of the initial planarization layer 20 is exposed, so as to form a mask layer 31; after the mask layer 31 is formed, removing the photoresist layer 40; after removing the photoresist layer 40, etching the initial planarization layer 20 by using the mask layer 31 as a mask until the surface of the layer to be etched 10 is exposed to form a planarization layer 21; after the planarization layer 21 is formed, the layer to be etched 10 is etched by using the planarization layer 21 as a mask.

In the above embodiment, on one hand, since the light source for exposing the photoresist material layer is the extreme ultraviolet light, which has a shorter wavelength, the photoresist layer 40 having the photoresist pattern with smaller critical dimension and higher integration level can be formed, thereby improving the integration level of the semiconductor device. On the other hand, since the initial planarization layer 20 is formed by a spin coating process with good filling performance, the surface flatness of the semiconductor structure can be improved, and the interface state of the layer to be etched 10 can be improved.

To meet the requirements of the extreme ultraviolet lithography process, a smaller photoresist layer 40 with a thickness M3 (shown in fig. 1) is required. To avoid the over-etching problem caused by the smaller thickness M3, it is desirable to reduce the thickness M2 of the masking material layer 30 (shown in fig. 1) and the thickness M1 of the initial planarization layer 20 (shown in fig. 1).

However, since the formation of the initial planarization layer 20 by the spin-coating process is affected by the spin-coating process, the number of defects in the formed initial planarization layer 20 is greatly affected by the thickness M1, i.e., when the thickness M1 is reduced, the defects in the initial planarization layer 20 are increased, and thus, the performance of the subsequently formed semiconductor device is poor.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which an initial first mask layer with a smaller thickness is formed between an initial first planarization layer and a second mask layer, so that the thickness of the initial first planarization layer is not reduced, and the second mask layer with a smaller thickness is enabled to correspond to the initial first mask layer, so that the flatness of the surface of the semiconductor structure is improved, the interface state of the surface of a layer to be etched is improved, and at the same time, not only the defects of the initial first planarization layer are reduced, but also the requirements of the extreme ultraviolet lithography process are met. Thus, the performance of the semiconductor device is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 9 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 3, a layer to be etched 100 is provided.

The material of the layer to be etched 100 comprises a semiconductor material.

In this embodiment, the material of the layer to be etched 100 includes silicon.

In other embodiments, the material of the layer to be etched comprises silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the layer to be etched 100 has device layers (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

Referring to fig. 4, an initial first planarization layer 110 is formed on the layer to be etched 100.

The initial first planarization layer 110 is used to repair the surface of the layer to be etched 100, on the one hand, and to provide a material for the subsequent formation of the first planarization layer, on the other hand.

The initial first planarization layer 110 has a first thickness H1 in a direction perpendicular to the surface of the layer to be etched 100.

In the present embodiment, the process of forming the initial first planarization layer 110 includes a spin coating process.

The reason why the initial first planarization layer 110 is formed using the spin coating process is that: the spin coating process has a good filling performance, and therefore, the initial first flat layer 110 formed by the spin coating process can better fill up uneven parts on the layer to be etched 100, so that the interface state of the initial layer to be etched 100 is improved, and the formed initial first flat layer 110 has high flatness, so that the pattern precision of the semiconductor structure is improved, and the performance of the semiconductor structure is improved.

In the present embodiment, the first thickness H1 ranges from 150 nm to 300 nm.

The reason for choosing the range of the first thickness H1 is that: if the first thickness H1 is too large, on the one hand, the process time and material costs for forming the semiconductor structure may increase. On the other hand, when the initial first planarization layer 110 is subsequently etched to form the first planarization layer, the pattern of the first planarization layer has a larger aspect ratio, so that the reaction gas of the etching process is hard to reach the portion of the initial first planarization layer close to the layer to be etched 100, which not only increases the difficulty of the etching process, but also causes the first planarization layer to be formed with a poor morphology. Since the initial first flat layer 110 is formed by using a spin coating process, the number of defects in the initial first flat layer 110 is related to the size of the first thickness H1 due to the spin coating process, and the smaller the first thickness H1 is, the greater the number of defects is, and therefore, if the first thickness H1 is too small, the excessive number of defects in the initial first flat layer 110 is caused, thereby resulting in poor performance of the semiconductor device. Therefore, by setting the range of the first thickness H1 to 150 nm to 300 nm, the process time and the material cost for forming the semiconductor structure can be set within a reasonable range, and not only can the difficulty of the etching process for subsequently etching the initial first flat layer 110 be reduced, but also the first flat layer with good morphology can be formed, and simultaneously the number of defects in the initial first flat layer 110 can be reduced, and the performance of the semiconductor device can be improved.

In this embodiment, the process parameters of the spin coating process include: the film forming temperature is 400 ℃ or lower. The film forming temperature is high, so that the influence of the temperature on the initial first flat layer 110 in the subsequent process of forming the semiconductor structure can be reduced, and the performance of the semiconductor structure is improved.

In this embodiment, the material of the initial first planarization layer 110 includes a carbon-containing organic material.

Referring to fig. 5, an initial first stop layer 120 is formed on the surface of the initial first planarization layer 110.

The initial first stop layer 120 provides material for the subsequent formation of the first stop layer.

Subsequently, an initial first mask layer is formed on the surface of the initial first stop layer, and the initial first stop layer 120 is used as an etching stop layer for subsequently etching the initial first mask layer.

Due to the formation of the initial first stop layer 120, on one hand, when the initial first mask layer is etched, the initial first stop layer 120 can protect the initial first flat layer 110, and reduce the influence of the etching process for etching the initial first mask layer on the initial first flat layer 110, so that the precision of the photoetching pattern transferred to the initial first flat layer 110 can be improved; on the other hand, when the accuracy of the photoetching pattern transferred to the initial first mask layer is detected to be poor, when the initial first mask layer is removed and a new initial first mask layer is newly formed, the influence of the process for removing the initial first mask layer on the initial first flat layer 110 can be reduced through the initial first stop layer, so that the performance of the semiconductor device is improved, and in addition, when the initial first mask layer is removed, the initial first flat layer 110 does not need to be removed, so that the forming process of the semiconductor structure is simplified, the forming time of the semiconductor structure is reduced, and the efficiency for manufacturing the semiconductor structure is improved.

In this embodiment, the material of the initial first stop layer 120 includes a metal oxide.

Because the subsequent etching process for etching the initial first mask layer has a larger selective etching ratio for the material of the initial first mask layer and the material of the initial first stop layer 120, the influence of the etching process for etching the initial first mask layer on the initial first stop layer 120 can be reduced, and the precision of the transferred photoetching pattern can be further improved.

In this embodiment, the initial first stop layer 120 has a fourth thickness H4 in a direction perpendicular to the surface of the layer to be etched 100.

In the present embodiment, the range of the fourth thickness H4 is

The range of the fourth thickness H4 is selected because if the fourth thickness H4 is too large, it results in an increase in process time and material cost for forming the semiconductor structure, and when the first stop layer is used as a mask, the mask pattern has a large aspect ratio, reducing the process window of the etching process for etching the initial first planarization layer 110; if the fourth thickness H4 is too small, the function of the initial first stop layer 120 as an etch stop layer is affected. Therefore, with the initial first stop layer 120 having the above-mentioned range of the fourth thickness H4, it is possible to make the pattern of the first stop layer as a mask have a smaller aspect ratio while ensuring the function as an etch stop layer, thereby increasing the process window of the etching process for etching the initial first flat layer 110, improving the performance of the semiconductor device, and it is possible to reduce the thickness of the semiconductor structure, and to reduce the process time and material cost for forming the semiconductor structure.

In other embodiments, the initial first stop layer is not formed.

Referring to fig. 6, an initial first mask layer 130 is formed on the initial first planarization layer 110.

Specifically, in this embodiment, the forming of the initial first mask layer 130 on the initial first planarization layer 110 means forming the initial first mask layer 130 on the surface of the initial first stop layer 120.

In other embodiments, the initial first mask layer is formed on the surface of the initial first planarization layer, since the initial first stop layer is not formed.

The initial first mask layer 130 provides material for the subsequent formation of a first mask layer.

In this embodiment, the initial first mask layer 130 has a second thickness H2 in a direction perpendicular to the surface of the layer to be etched 100, the second thickness H2 is less than the first thickness H1, and the fourth thickness H4 is less than the second thickness H2.

Since the second thickness H2 is smaller than the first thickness H1, on one hand, when a second mask layer is formed subsequently and the initial first mask layer 130 is etched by using the second mask layer as a mask, the thinner initial first mask layer 130 can form the first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first flat layer 110 can enable the semiconductor structure to have higher flatness, and when the initial first flat layer 110, the initial first mask layer 130 and the second mask layer are used for transferring the photoetching pattern to the layer to be etched 100, the pattern precision in the transferring process is improved.

Since the fourth thickness H4 is smaller than the second thickness H2, the thickness of the first stop layer is smaller, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase the process window of the etching process for etching the initial first flat layer 110, thereby improving the performance of the semiconductor device.

In the present embodiment, the second thickness H2 is in a range of 30 nm to 100 nm.

The reason for selecting the range of the second thickness H2 is that if the second thickness H2 is too large, the first mask layer cannot be formed before the second mask layer is completely worn, and the transfer of the pattern of the second mask layer is realized, and if the second thickness H2 is too small, the process difficulty of forming the initial first mask layer is increased, so that, on the one hand, the lithography pattern transfer under the extreme ultraviolet light process can be realized by selecting the second thickness H2, and at the same time, the process difficulty of forming the initial first mask layer is reduced.

In this embodiment, the process of forming the initial first mask layer 130 includes a deposition process.

The reason why the first mask layer 130 is formed by a deposition process is that the deposition process is characterized in that the number of defects in the formed material layer is small and the number of defects is less influenced by the thickness of the material layer. Therefore, by forming the initial first mask layer 130 by using the deposition process, the initial first mask layer 130 with the smaller second thickness H2 can be formed to cope with the photolithography pattern transfer under the euv light process, and at the same time, the number of defects in the initial first mask layer 130 can be reduced, thereby improving the pattern precision of the first mask layer.

In this embodiment, the deposition process includes a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, the material of the initial first mask layer 130 includes a carbon-containing organic material.

Referring to fig. 7, a second mask layer 140 is formed on the surface of the initial first mask layer 130, and the second mask layer 140 exposes a portion of the surface of the initial first mask layer 130.

The second mask layer 140 and the first mask layer are used for transferring the lithography pattern of the photoresist layer to improve the stability of the lithography pattern.

In the embodiment, the second mask layer 140 has a third thickness H3 in a direction perpendicular to the surface of the layer to be etched 100, and the third thickness H3 is smaller than the first thickness H1.

In the photoetching process using extreme ultraviolet light as a light source, the photoresist layer is thinner. Since the third thickness H3 is smaller than the first thickness H1, when the photoresist layer is used as a mask to etch the material layer of the second mask layer 140, the thinner material layer of the second mask layer 140 can form the second mask layer 140 before the photoresist layer is completely consumed, thereby realizing the transfer of the lithography pattern under the extreme ultraviolet lithography process.

In the present embodiment, the third thickness H3 is greater than or equal to 12 nm.

In this embodiment, the material of the second mask layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the method for forming the second mask layer 140 includes: forming a second mask material layer (not shown) on the surface of the initial first mask layer 130; forming a photoresist pattern layer (not shown) on the surface of the second mask material layer, wherein the photoresist pattern layer exposes a part of the surface of the second mask material layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer 130 is exposed.

And the process for etching the second mask material layer comprises a dry etching process or a wet etching process.

In this embodiment, the process of etching the second mask material layer includes a dry etching process.

In this embodiment, after the second mask layer 140 is formed, and before the initial first mask layer 130 is subsequently etched, the photoresist pattern layer is removed.

Subsequently, the method for forming the semiconductor structure further comprises the following steps: and forming a first flat layer, and etching the layer to be etched by taking the first flat layer as a mask. Specifically, please refer to fig. 8 and 9 for the steps of forming the first planarization layer and etching the layer to be etched.

Referring to fig. 8, after the second mask layer 140 is formed, the initial first mask layer 130 is etched with the second mask layer 140 as a mask until the surface of the initial first stop layer 120 is exposed to form a first mask layer 131; and etching the initial first stop layer 120 by taking the first mask layer 131 as a mask until the surface of the initial first flat layer 110 is exposed to form a first stop layer 121.

In other embodiments, since the first stop layer is not formed, the method of forming the first mask layer includes: and etching the initial first mask layer by taking the second mask layer as a mask until the surface of the first flat layer is exposed.

The process of etching the initial first mask layer 130 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first mask layer 130 includes a dry etching process.

The process of etching the initial first stop layer 120 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first stop layer 120 includes a dry etching process.

In this embodiment, after the first stop layer 121 is formed, and before the initial first planarization layer 110 is subsequently etched, the first mask layer 131 is removed.

In other embodiments, the first mask layer is not removed after the first stop layer is formed and before the subsequent etching of the initial first planarization layer.

Referring to fig. 9, the initial first planarization layer 110 is etched using the first stop layer 121 as a mask until the surface of the layer to be etched 100 is exposed, so as to form a first planarization layer 111; and etching the layer to be etched 100 by taking the first flat layer 111 as a mask.

In other embodiments, since the first stop layer is not formed, or the first mask layer is not removed after the first stop layer is formed and before the initial first planarization layer is etched, the method of forming the first planarization layer includes: and after the second mask layer is formed, etching the initial first flat layer by taking the first mask layer as a mask until the surface of the layer to be etched is exposed.

In summary, through the formation method of the semiconductor structure, the pattern precision of the photoetching pattern in the transfer process can be increased while the integration degree is improved by the photoetching process of the extreme ultraviolet light, so as to improve the performance of the semiconductor device.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 7, including: a layer to be etched 100; an initial first planarization layer 110 on the layer to be etched 100; an initial first mask layer 130 on the initial first planarization layer 110; a second mask layer 140 on the initial first mask layer 130, the second mask layer 140 exposing a portion of the surface of the initial first mask layer 130.

The initial first planarization layer 110 is used to repair the surface of the layer to be etched 100 and provide material for forming the first planarization layer.

The initial first mask layer 130 is used to form a first mask layer.

In a direction perpendicular to the surface of the layer to be etched 100, the initial first planarization layer 110 has a first thickness H1, the initial first mask layer 130 has a second thickness H2, the second mask layer 140 has a third thickness H3, the second thickness H2 is less than the first thickness H1, and the third thickness H3 is less than the first thickness H1.

Since the second thickness H2 is less than the first thickness H1, on one hand, when the initial first mask layer 130 is etched by using the second mask layer 140 as a mask to form a first mask layer, the thinner initial first mask layer 130 can form the first mask layer before the second mask layer 140 is completely worn, so that the transfer of the pattern of the second mask layer 140 is realized; on the other hand, the thicker initial first planarization layer 110 can enable the semiconductor structure to have higher flatness, and when the initial first planarization layer 110, the initial first mask layer 130 and the second mask layer 140 are used for transferring the photoetching pattern to the layer to be etched 100, the pattern precision in the transferring process is improved.

In summary, with the semiconductor structure, while the integration degree is improved by the photolithography process for dealing with the extreme ultraviolet light, the pattern precision of the photolithography pattern in the transfer process can be increased to improve the performance of the semiconductor device.

The material of the layer to be etched 100 comprises a semiconductor material.

In the present embodiment, the first thickness H1 ranges from 150 nm to 300 nm.

The reason for choosing the range of the first thickness H1 is that: if the first thickness H1 is too large, on the one hand, the process time and material costs for forming the semiconductor structure may increase. On the other hand, when the initial first planarization layer 110 is etched to form the first planarization layer, the pattern of the first planarization layer has a larger aspect ratio, so that the reaction gas of the etching process is hard to reach the portion of the initial first planarization layer close to the layer to be etched 100, which not only increases the difficulty of the etching process, but also causes the first planarization layer to be formed with a poor morphology. Furthermore, when the initial first planarization layer 110 is formed by using a spin coating process, the number of defects in the initial first planarization layer 110 is related to the size of the first thickness H1 due to the spin coating process, and the smaller the first thickness H1, the greater the number of defects, and therefore, if the first thickness H1 is too small, the greater the number of defects in the initial first planarization layer 110 may be, thereby resulting in poor performance of the semiconductor device. Therefore, by setting the range of the first thickness H1 to 150 nm to 300 nm, the process time and the material cost for forming the semiconductor structure can be set within a reasonable range, and at the same time, the difficulty of the etching process for etching the initial first flat layer 110 can be reduced, and the first flat layer with a better morphology can be formed, the number of defects in the initial first flat layer 110 can be reduced, and the performance of the semiconductor device can be improved.

The reason for selecting the range of the second thickness H2 is that if the second thickness H2 is too large, the first mask layer cannot be formed before the second mask layer 140 is completely worn, and the pattern of the second mask layer 140 is transferred, and if the second thickness H2 is too small, the process difficulty of forming the initial first mask layer 130 is increased, so that, by selecting the second thickness H2, the photolithography pattern transfer under the extreme ultraviolet light process can be realized, and at the same time, the process difficulty of forming the initial first mask layer 130 is reduced.

In this embodiment, the semiconductor structure further includes: an initial first stop layer 120 between the initial first planarization layer 110 and the initial first mask layer 130.

The initial first stop layer 120 provides a material for forming a first stop layer, and the initial first stop layer 120 is used as an etch stop layer when etching the initial first mask layer 130.

Since the semiconductor structure further includes the initial first stop layer 120, on one hand, when the initial first mask layer 130 is etched, the initial first stop layer 120 can protect the initial first flat layer 110, and reduce the influence of the etching process for etching the initial first mask layer 130 on the initial first flat layer 110, thereby improving the precision of the lithography pattern transferred to the initial first flat layer 110; on the other hand, when it is detected that the accuracy of the lithography pattern transferred to the initial first mask layer 130 is poor, when the initial first mask layer 130 is removed and a new initial first mask layer is newly formed, the influence of the process for removing the initial first mask layer 130 on the initial first flat layer 110 can be reduced through the initial first stop layer 120, so that the performance of the semiconductor device is improved, and in addition, when the initial first mask layer 130 is removed, the initial first flat layer 110 does not need to be removed, so that the forming process of the semiconductor structure is simplified, the forming time of the semiconductor structure is reduced, and the efficiency of manufacturing the semiconductor structure is improved.

In other embodiments, the semiconductor structure does not include the initial first stop layer.

Since the etching process for etching the initial first mask layer 130 to form the first mask layer has a larger selective etching ratio for the material of the initial first mask layer 130 and the material of the initial first stop layer 120, the influence of the etching process for etching the initial first mask layer 130 on the initial first stop layer 120 can be reduced, and the precision of the transferred photoetching pattern can be further improved.

In the present embodiment, the initial first stop layer 120 has a fourth thickness H4 in a direction perpendicular to the surface of the layer to be etched 100, and the fourth thickness H4 is less than the second thickness H2.

Since the fourth thickness H4 is smaller than the second thickness H2, the thickness of the first stop layer formed by the initial first stop layer 120 is smaller, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase the process window of the etching process for etching the initial first flat layer 110, thereby improving the performance of the semiconductor device.

In the present embodiment, the range of the fourth thickness H4 is

Fig. 10 to 16 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 10, a layer to be etched 200 is provided.

The material of the layer to be etched 200 comprises a semiconductor material.

In this embodiment, the material of the layer to be etched 200 includes silicon.

In this embodiment, the layer to be etched 200 has device layers (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

Referring to fig. 11, an initial first planarization layer 210 is formed on the layer to be etched 200.

The initial first planarization layer 210 is used to repair the surface of the layer to be etched 200, on the one hand, and to provide a material for the subsequent formation of the first planarization layer, on the other hand.

The initial first planarization layer 210 has a first thickness T1 in a direction perpendicular to the surface of the layer to be etched 200.

In the present embodiment, the process of forming the initial first planarization layer 210 includes a spin-on process.

The reason why the initial first planarization layer 210 is formed using the spin coating process is that: the spin coating process has a good filling performance, and therefore, the initial first planarization layer 210 formed by the spin coating process can better fill up uneven parts on the layer to be etched 200, so that the interface state of the initial layer to be etched 200 is improved, and the formed initial first planarization layer 210 has high flatness, so that the pattern precision of the semiconductor structure is improved, and the performance of the semiconductor structure is improved.

In the present embodiment, the first thickness T1 ranges from 150 nm to 300 nm.

The reason for choosing the range of the first thickness T1 is that: if the first thickness T1 is too large, on the one hand, the process time and material costs for forming the semiconductor structure may increase. On the other hand, when the initial first planarization layer 210 is etched subsequently to form the first planarization layer, the pattern of the first planarization layer has a larger aspect ratio, so that the reaction gas of the etching process is hard to reach the portion of the initial first planarization layer close to the layer to be etched 200, which not only increases the difficulty of the etching process, but also causes the first planarization layer to be formed with a poor morphology. Since the initial first planarization layer 210 is formed by using the spin coating process, the number of defects in the initial first planarization layer 210 is related to the size of the first thickness T1 due to the spin coating process, and the smaller the first thickness T1, the greater the number of defects, and therefore, if the first thickness T1 is too small, the greater the number of defects in the initial first planarization layer 210 may be, thereby resulting in poor performance of the semiconductor device. Therefore, by setting the range of the first thickness T1 to 150 nm to 300 nm, the process time and the material cost for forming the semiconductor structure can be set within a reasonable range, and not only can the difficulty of the etching process for subsequently etching the initial first flat layer 210 be reduced, but also the first flat layer with good morphology can be formed, and at the same time, the number of defects in the initial first flat layer 210 can be reduced, and the performance of the semiconductor device can be improved.

In this embodiment, the process parameters of the spin coating process include: the film forming temperature is 400 ℃ or lower. The film forming temperature is high, so that the influence of the temperature on the initial first planarization layer 210 in the subsequent process of forming the semiconductor structure can be reduced, and the performance of the semiconductor structure is improved.

In this embodiment, the material of the initial first planarization layer 210 includes a carbon-containing organic material.

Referring to fig. 12, an initial first stop layer 220 is formed on the surface of the initial first planarization layer 210.

The initial first stop layer 220 provides material for the subsequent formation of the first stop layer.

Subsequently, an initial first mask layer is formed on the surface of the initial first stop layer, and the initial first stop layer 220 is used as an etching stop layer for subsequently etching the initial first mask layer.

Due to the formation of the initial first stop layer 220, on one hand, when the initial first mask layer is etched, the initial first stop layer 220 can protect the initial first flat layer 210, and reduce the influence of the etching process for etching the initial first mask layer on the initial first flat layer 210, so that the precision of the photoetching pattern transferred to the initial first flat layer 210 can be improved; on the other hand, when it is detected that the accuracy of the lithographic pattern transferred to the initial first mask layer is poor, when the initial first mask layer is removed and a new initial first mask layer is newly formed, the influence of the process for removing the initial first mask layer on the initial first flat layer 210 can be reduced through the initial first stop layer, so that the performance of the semiconductor device is improved, and in addition, when the initial first mask layer is removed, the initial first flat layer 210 does not need to be removed, so that the forming process of the semiconductor structure is simplified, the forming time of the semiconductor structure is reduced, and the efficiency of manufacturing the semiconductor structure is improved.

In the present embodiment, the material of the initial first stop layer 220 includes amorphous silicon.

The amorphous silicon is chosen because: when the sidewall of the first stop layer formed by the initial first stop layer 220 is subjected to thinning etching subsequently, a simpler manufacturing process with a larger process window can be adopted, so that a pattern with a smaller critical dimension can be formed better. When the first stop layer is used as a sacrificial layer and a side wall is formed on the side wall surface of the first stop layer in the subsequent process, an etchant adopted by an etching process for etching the material layer of the side wall or the etchant adopted by the etching process for removing the first stop layer has a high selective etching ratio on the material of the first stop layer and the material of the side wall, so that the influence of the etching process on the first stop layer or the side wall is reduced, and the pattern morphology of the semiconductor structure is improved.

In this embodiment, the initial first stop layer 220 has a fourth thickness T4 in a direction perpendicular to the surface of the layer to be etched 200.

In the present embodiment, the fourth thickness T4 is in a range of 5 nm to 10 nm.

The range of the fourth thickness T4 is selected because if the fourth thickness T4 is too large, it results in an increase in process time and material cost for forming the semiconductor structure, and when the first stop layer is used as a mask, the mask pattern has a large aspect ratio, reducing the process window of the etching process for etching the initial first planarization layer 210. If the fourth thickness T4 is too small, on one hand, the function of the initial first stop layer 220 as an etching stop layer is affected, and on the other hand, when the initial first planarization layer 210 is etched using the first stop layer as a mask to form a first planarization layer, the first stop layer is easily worn out before the first planarization layer is formed, so that the pattern transfer of the first stop layer cannot be realized. Therefore, with the initial first stop layer 220 having the above-mentioned range of the fourth thickness T4, on the one hand, not only the function as an etching stop layer can be ensured and the transfer of the pattern of the first stop layer can be realized, but also the pattern of the first stop layer as a mask can be made to have a smaller aspect ratio, thereby increasing the process window of the etching process for etching the initial first planarization layer 210, improving the performance of the semiconductor device, and reducing the thickness of the semiconductor structure, and reducing the process time and material cost for forming the semiconductor structure. In addition, when the sidewall of the first stop layer is subjected to the second thinning etching subsequently, the range of the fourth thickness T4 can also provide a margin for the thinning etching for the first stop layer after the second thinning etching to have a proper thickness.

Referring to fig. 13, an initial first mask layer 230 is formed on the initial first planarization layer 210.

Specifically, in this embodiment, the forming of the initial first mask layer 230 on the initial first planarization layer 210 means forming the initial first mask layer 230 on the surface of the initial first stop layer 220.

The initial first mask layer 230 provides material for the subsequent formation of a first mask layer.

In this embodiment, the initial first mask layer 230 has a second thickness T2 in a direction perpendicular to the surface of the layer to be etched 200, the second thickness T2 is less than the first thickness T1, and the fourth thickness T4 is less than the second thickness T2.

Since the second thickness T2 is smaller than the first thickness T1, on one hand, when a second mask layer is formed subsequently and the initial first mask layer 230 is etched by using the second mask layer as a mask, the thinner initial first mask layer 230 can form the first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first planarization layer 210 can make the semiconductor structure have higher flatness, which is beneficial to improving the pattern precision in the transfer process when the initial first planarization layer 210, the initial first mask layer 230 and the second mask layer are used for transferring the photoetching pattern to the layer to be etched 200.

Since the fourth thickness T4 is smaller than the second thickness T2, the thickness of the first stop layer is smaller, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase the process window of the etching process for etching the initial first planarization layer 210, thereby improving the performance of the semiconductor device.

In the present embodiment, the second thickness T2 is in a range of 30 nm to 100 nm.

The reason for selecting the range of the second thickness T2 is that if the second thickness T2 is too large, the first mask layer cannot be formed before the second mask layer is completely worn, and the transfer of the pattern of the second mask layer is achieved, and if the second thickness T2 is too small, the process difficulty of forming the initial first mask layer is increased, so that, on the one hand, the lithography pattern transfer under the extreme ultraviolet light process can be achieved by selecting the second thickness T2, and at the same time, the process difficulty of forming the initial first mask layer is reduced.

In this embodiment, the process of forming the initial first mask layer 230 includes a deposition process.

The reason why the first mask layer 230 is formed by a deposition process is that the deposition process is characterized in that the number of defects in the formed material layer is small and the number of defects is less influenced by the thickness of the material layer. Therefore, by forming the initial first mask layer 230 by using the deposition process, the initial first mask layer 230 with the smaller second thickness T2 can be formed to cope with the photolithography pattern transfer under the euv light process, and at the same time, the number of defects in the initial first mask layer 230 can be reduced, thereby improving the pattern accuracy of the first mask layer.

In this embodiment, the material of the initial first mask layer 230 includes a carbon-containing organic material.

Referring to fig. 14, a second mask layer 240 is formed on the surface of the initial first mask layer 230, and the second mask layer 240 exposes a portion of the surface of the initial first mask layer 230.

The second mask layer 240 and the first mask layer are used for transferring the photoresist pattern of the photoresist layer to improve the stability of the photoresist pattern.

In the embodiment, the second mask layer 240 has a third thickness T3 in a direction perpendicular to the surface of the layer to be etched 200, and the third thickness T3 is smaller than the first thickness T1.

In the photoetching process using extreme ultraviolet light as a light source, the photoresist layer is thinner. Since the third thickness T3 is smaller than the first thickness T1, when the photoresist layer is used as a mask to etch the material layer of the second mask layer 240, the thinner material layer of the second mask layer 240 can form the second mask layer 240 before the photoresist layer is completely consumed, thereby realizing the transfer of the lithography pattern under the extreme ultraviolet lithography process.

In the present embodiment, the third thickness T3 is greater than or equal to 12 nm.

In this embodiment, the material of the second mask layer 240 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the method for forming the second mask layer 240 includes: forming a second mask material layer (not shown) on the surface of the initial first mask layer 230; forming a photoresist pattern layer (not shown) on the surface of the second mask material layer, wherein the photoresist pattern layer exposes a part of the surface of the second mask material layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer 230 is exposed.

In other embodiments, the method of forming the second mask layer includes: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein part of the surface of the second mask material layer is exposed out of the photoresist pattern layer; forming a third side wall on the side wall of the photoresist pattern layer; after the third side wall is formed, removing the photoresist pattern layer; and after removing the photoresist pattern layer, etching the second mask material layer by taking the third side wall as a mask until the surface of the initial first mask layer is exposed.

In this embodiment, after the second mask layer 240 is formed and before the initial first mask layer 230 is subsequently etched, the photoresist pattern layer is removed.

Subsequently, the method for forming the semiconductor structure further comprises the following steps: and forming a first flat layer, and etching the layer to be etched by taking the first flat layer as a mask. Specifically, please refer to fig. 15 and 16 for the steps of forming the first planarization layer and etching the layer to be etched.

Referring to fig. 15, after the second mask layer 240 is formed, the initial first mask layer 230 is etched with the second mask layer 240 as a mask until the surface of the initial first stop layer 220 is exposed to form a first mask layer 231; the initial first stop layer 220 is etched by using the first mask layer 231 as a mask until the surface of the initial first planarization layer 210 is exposed, so as to form a first stop layer 221.

The process of etching the initial first stop layer 220 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first stop layer 220 includes a dry etching process.

The process of etching the initial first mask layer 230 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first mask layer 230 includes a dry etching process.

In this embodiment, before the initial first stop layer 220 is etched, the sidewall of the first mask layer 231 is subjected to the first thinning etching for more than 1 time.

Since the first thinning etching is performed on the sidewall of the first mask layer 231 for more than 1 time, the critical dimension of the pattern of the first mask layer 231 can be reduced, so that a pattern with a smaller critical dimension can be formed on the layer to be etched, the design requirement with a smaller critical dimension can be met, and the integration level of the semiconductor device can be further improved.

In this embodiment, the method of performing the first thinning etching on the sidewall of the first mask layer 231 for 1 time includes: performing a first modification treatment on the first mask layer 231, and converting the side wall surface of the first mask layer 231 into a first layer to be removed; and etching the first layer to be removed until the first layer to be removed is removed.

In this embodiment, the first modified process includes a thermal oxidation process.

The process for etching the first layer to be removed comprises a dry etching process or a wet etching process.

In this embodiment, the process of etching the first layer to be removed includes a dry etching process.

In other embodiments, the first thinning etch process is not performed.

In this embodiment, after the first stop layer 221 is formed, and before the initial first planarization layer 210 is subsequently etched, the first mask layer 231 is removed.

Referring to fig. 16, the initial first planarization layer 210 is etched using the first stop layer 221 as a mask until the surface of the layer to be etched 200 is exposed, so as to form a first planarization layer 211; and etching the layer to be etched 200 by taking the first flat layer 211 as a mask.

In this embodiment, before etching the initial first planarization layer 210, the sidewall of the first stop layer 221 is subjected to a second thinning-etching process for more than 1 time.

Since the sidewall of the first stop layer 221 is subjected to the second thinning etching for more than 1 time, the critical dimension of the pattern of the first stop layer 221 can be reduced, and thus a pattern with a smaller critical dimension can be formed on the layer to be etched, so that the design requirement with a smaller critical dimension can be met, and the integration level of the semiconductor device can be further improved.

In this embodiment, the method of performing the second thinning etching on the sidewall of the first stop layer 221 1 time includes: performing second modification treatment on the first stop layer 221, and converting the surface of the side wall of the first stop layer 221 into a second layer to be removed; and etching the second layer to be removed until the second layer to be removed is removed.

In this embodiment, the process of the second modification treatment includes a thermal oxidation process.

And the process for etching the second layer to be removed comprises a dry etching process or a wet etching process.

In this embodiment, the process of etching the second layer to be removed includes a dry etching process.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above forming method, referring to fig. 14, including: layer to be etched 200; an initial first planarization layer 210 on the layer to be etched 200; an initial first mask layer 230 on the initial first planarization layer 210; a second mask layer 240 on the initial first mask layer 230, wherein the second mask layer 240 exposes a portion of the surface of the initial first mask layer 230.

The initial first planarization layer 210 is used to repair the surface of the layer to be etched 200 and provide material for forming the first planarization layer.

The initial first mask layer 230 is used to form a first mask layer.

In a direction perpendicular to the surface of the layer to be etched 200, the initial first planarization layer 210 has a first thickness T1, the initial first mask layer 230 has a second thickness T2, the second mask layer 240 has a third thickness T3, the second thickness T2 is smaller than the first thickness T1, and the third thickness T3 is smaller than the first thickness T1.

Since the second thickness T2 is smaller than the first thickness T1, on one hand, when the initial first mask layer 230 is etched by using the second mask layer 240 as a mask to form a first mask layer, the thinner initial first mask layer 230 can form a first mask layer before the second mask layer 240 is completely worn, so that the transfer of the pattern of the second mask layer 240 is realized; on the other hand, the thicker initial first planarization layer 210 can make the semiconductor structure have higher flatness, which is beneficial to improving the pattern precision in the transfer process when the initial first planarization layer 210, the initial first mask layer 230 and the second mask layer 240 are used for transferring the photoetching pattern to the layer to be etched 200.

The material of the layer to be etched 200 comprises a semiconductor material.

In the present embodiment, the first thickness T1 ranges from 150 nm to 300 nm.

The reason for choosing the range of the first thickness T1 is that: if the first thickness T1 is too large, on the one hand, the process time and material costs for forming the semiconductor structure may increase. On the other hand, when the initial first planarization layer 210 is etched to form the first planarization layer, the pattern of the first planarization layer has a larger aspect ratio, so that the reaction gas of the etching process is hard to reach the portion of the initial first planarization layer close to the layer to be etched 200, which not only increases the difficulty of the etching process, but also causes the first planarization layer to be formed with a poor morphology. Furthermore, when the initial first planarization layer 210 is formed by using the spin coating process, the number of defects in the initial first planarization layer 210 is related to the size of the first thickness T1 due to the spin coating process, and the smaller the first thickness T1, the greater the number of defects, and thus, if the first thickness T1 is too small, the greater the number of defects in the initial first planarization layer 210, thereby resulting in poor performance of the semiconductor device. Therefore, by setting the range of the first thickness T1 to 150 nm to 300 nm, the process time and the material cost for forming the semiconductor structure can be set within a reasonable range, and at the same time, the difficulty of the etching process for etching the initial first flat layer 210 can be reduced, and the first flat layer with a better morphology can be formed, the number of defects in the initial first flat layer 210 can be reduced, and the performance of the semiconductor device can be improved.

The second thickness T2 is selected because if the second thickness T2 is too large, the first mask layer cannot be formed before the second mask layer 240 is completely worn, and the pattern of the second mask layer 240 is transferred, and if the second thickness T2 is too small, the process difficulty of forming the initial first mask layer 230 is increased, and therefore, if the second thickness T2 is selected, the photolithography pattern transfer under the extreme ultraviolet light process can be achieved, and the process difficulty of forming the initial first mask layer 230 is reduced.

In this embodiment, the semiconductor structure further includes: an initial first stop layer 220 between the initial first planarization layer 210 and the initial first mask layer 230.

The initial first stop layer 220 provides a material for forming a first stop layer, and the initial first stop layer 220 is used as an etch stop layer when etching the initial first mask layer 230.

Since the semiconductor structure further includes the initial first stop layer 220, on one hand, when the initial first mask layer 230 is etched, the initial first stop layer 220 can protect the initial first flat layer 210, and reduce the influence of the etching process for etching the initial first mask layer 230 on the initial first flat layer 210, thereby improving the precision of the lithography pattern transferred to the initial first flat layer 210; on the other hand, when it is detected that the accuracy of the lithography pattern transferred to the initial first mask layer 230 is poor, when the initial first mask layer 230 is removed and a new initial first mask layer is newly formed, the influence of the process for removing the initial first mask layer 230 on the initial first planarization layer 210 can be reduced through the initial first stop layer 220, so that the performance of the semiconductor device is improved, and in addition, when the initial first mask layer 230 is removed, the initial first planarization layer 210 does not need to be removed, so that the forming process of the semiconductor structure is simplified, the forming time of the semiconductor structure is reduced, and the efficiency of manufacturing the semiconductor structure is improved.

The amorphous silicon is chosen because: when the sidewall of the first stop layer formed by the initial first stop layer 220 is thinned and etched, a simpler manufacturing process with a larger process window can be adopted, so that a pattern with a smaller critical dimension can be formed better. When the first stop layer is used as a sacrificial layer and a side wall is formed on the side wall surface of the first stop layer, an etchant adopted by an etching process for etching the material layer of the side wall or the etchant adopted by the etching process for removing the first stop layer has a high selective etching ratio for the material of the first stop layer and the material of the side wall, so that the influence of the etching process on the first stop layer or the side wall is reduced, and the pattern morphology of the semiconductor structure is improved.

In the present embodiment, the initial first stop layer 220 has a fourth thickness T4 in a direction perpendicular to the surface of the layer to be etched 200, and the fourth thickness T4 is less than the second thickness T2.

Since the fourth thickness T4 is smaller than the second thickness T2, the thickness of the first stop layer formed by the initial first stop layer 220 is smaller, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase the process window of the etching process for etching the initial first planarization layer 210, thereby improving the performance of the semiconductor device.

The range of the fourth thickness T4 is selected because if the fourth thickness T4 is too large, it results in an increase in process time and material cost for forming the semiconductor structure, and when the first stop layer is used as a mask, the mask pattern has a large aspect ratio, reducing the process window of the etching process for etching the initial first planarization layer 210. If the fourth thickness T4 is too small, on one hand, the function of the initial first stop layer 220 as an etching stop layer is affected, and on the other hand, when the initial first planarization layer 210 is etched using the first stop layer as a mask to form a first planarization layer, the first stop layer is easily worn out before the first planarization layer is formed, so that the pattern transfer of the first stop layer cannot be realized. Therefore, with the initial first stop layer 220 having the above-mentioned range of the fourth thickness T4, on the one hand, not only the function as an etching stop layer can be ensured and the transfer of the pattern of the first stop layer can be realized, but also the pattern of the first stop layer as a mask can be made to have a smaller aspect ratio, thereby increasing the process window of the etching process for etching the initial first planarization layer 210, improving the performance of the semiconductor device, and reducing the thickness of the semiconductor structure, and reducing the process time and material cost for forming the semiconductor structure. Besides, when the sidewall of the first stop layer is subjected to the second thinning etching, the range of the fourth thickness T4 can also provide a margin for the thinning etching for the first stop layer after the second thinning etching to have a proper thickness.

Fig. 17 to 22 are schematic cross-sectional structure diagrams of steps of a method for forming a semiconductor structure according to still another embodiment of the present invention, and the main difference between this embodiment and the embodiment shown in fig. 10 to 16 is that after the second mask layer 240 is formed, a method and a structure for forming a first mask layer, a first stop layer, and a first planarization layer are formed, and a method and a structure for etching the band etching layer 200 are different, so this embodiment continues to explain a process for forming a semiconductor structure on the basis of the above-described embodiment.

Referring to fig. 17 on the basis of fig. 14, after the second masking layer 240 is formed, second sidewalls 242 are formed on the sidewalls of the second masking layer 240; after the second sidewalls 242 are formed, the second masking layer 240 is removed.

In this embodiment, the method for forming the second side walls 242 includes: depositing a second sidewall material layer (not shown) on the surface of the second mask layer 240 and the surface of the initial first mask layer 230; the second sidewall material layer is etched back until the top surface of the second masking layer 240 and the surface of the initial first masking layer 230 are exposed.

In this embodiment, the process of removing the second mask layer 240 includes a dry etching process or a wet etching process.

Referring to fig. 18, after removing the second mask layer 240, the initial first mask layer 230 is etched using the second sidewalls 242 as a mask until the surface of the initial first stop layer 220 is exposed, so as to form a first mask layer 250.

In the present embodiment, after the first mask layer 250 is formed, the second sidewalls 242 are removed.

Referring to fig. 19, after removing the second sidewalls 242, first sidewalls 251 are formed on the sidewall surfaces of the first masking layer 250; after the first sidewall 251 is formed, the first mask layer 250 is removed.

In this embodiment, the method for forming the first sidewall 251 includes: depositing a first sidewall material layer (not shown) on the surface of the first mask layer 250 and the surface of the initial first stop layer 220; the first sidewall material layer is etched back until the top surface of the first mask layer 250 and the surface of the initial first stop layer 220 are exposed.

In this embodiment, the process of removing the first mask layer 250 includes a dry etching process or a wet etching process.

Referring to fig. 20, after removing the first mask layer 250, the initial first stop layer 220 is etched using the first sidewall 251 as a mask until the surface of the initial first planarization layer 210 is exposed, so as to form a first stop layer 260.

In this embodiment, after the first stop layer 260 is formed, the first sidewall 251 is removed.

Referring to fig. 21, after removing the first sidewall 251, a mask sidewall 261 is formed on a sidewall of the first stop layer 260; after the mask sidewall 261 is formed, the first stop layer 260 is removed.

In this embodiment, the process of removing the first stop layer 260 includes a dry etching process or a wet etching process.

Referring to fig. 22, after removing the first stop layer 260, the initial first planarization layer 210 is etched by using the mask sidewall 261 as a mask until the surface of the layer to be etched 200 is exposed, so as to form a first planarization layer 211.

The process of etching the initial first planarization layer 210 includes a dry etching process or a wet etching process.

In this embodiment, after the first planarization layer 211 is formed, the mask sidewall 261 is removed; after removing the mask sidewall 261, the layer to be etched 200 is etched with the first flat layer 211 as a mask.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

etching the layer to be etched;

an initial first planarization layer on the layer to be etched, the initial first planarization layer having a first thickness;

an initial first mask layer on the initial first planarization layer, the initial first mask layer having a second thickness, the second thickness being less than the first thickness;

and the second mask layer is positioned on the initial first mask layer, the second mask layer exposes a part of the surface of the initial first mask layer, and the second mask layer has a third thickness which is smaller than the first thickness.

2. The semiconductor structure of claim 1, in which a material of the initial first planarization layer comprises a carbon-containing organic material.

3. The semiconductor structure of claim 1, in which a material of the initial first mask layer comprises a carbon-containing organic material.

4. The semiconductor structure of claim 1, wherein the first thickness is in a range from 150 nanometers to 300 nanometers.

5. The semiconductor structure of claim 1, wherein the second thickness is in a range from 30 nanometers to 100 nanometers.

6. The semiconductor structure of claim 1, wherein the third thickness is greater than 12 nanometers.

7. The semiconductor structure of claim 1, further comprising: an initial first stop layer between the initial first planarization layer and the initial first mask layer.

8. The semiconductor structure of claim 7, in which the initial first stop layer has a fourth thickness, the fourth thickness being less than the second thickness.

9. The semiconductor structure of claim 7, in which a material of the initial first stop layer comprises a metal oxide.

10. The semiconductor structure of claim 9, wherein the fourth thickness is in a range of

11. The semiconductor structure of claim 7, wherein a material of the initial first stop layer comprises amorphous silicon.

12. The semiconductor structure of claim 11, wherein the fourth thickness is in a range from 5 nanometers to 10 nanometers.

13. The semiconductor structure of claim 1, wherein a material of the second mask layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

14. A method of forming a semiconductor structure, comprising:

providing a layer to be etched;

forming an initial first flat layer on the layer to be etched, wherein the initial first flat layer has a first thickness;

forming an initial first mask layer on the initial first flat layer, wherein the initial first mask layer has a second thickness, and the second thickness is smaller than the first thickness;

and forming a second mask layer on the initial first mask layer, wherein the second mask layer exposes a part of the surface of the initial first mask layer, and the second mask layer has a third thickness which is smaller than the first thickness.

15. The method of forming a semiconductor structure of claim 14, wherein the process of forming the initial first mask layer comprises a deposition process.

16. The method of forming a semiconductor structure of claim 14, wherein the process of forming the initial first planarization layer comprises a spin-on process.

17. The method of forming a semiconductor structure of claim 16, wherein the process parameters of the spin coating process comprise: the film forming temperature is 400 ℃ or lower.

18. The method of forming a semiconductor structure of claim 14, wherein forming the second mask layer comprises: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein part of the surface of the second mask material layer is exposed out of the photoresist pattern layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer is exposed.

19. The method of forming a semiconductor structure of claim 14, further comprising: and etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first flat layer is exposed to form a first mask layer.

20. The method of forming a semiconductor structure of claim 19, further comprising: etching the initial first flat layer by taking the first mask layer as a mask until the surface of the layer to be etched is exposed to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

21. The method of forming a semiconductor structure of claim 14, further comprising: and before the initial first mask layer is formed, forming an initial first stop layer on the surface of the initial first flat layer.

22. The method of forming a semiconductor structure of claim 21, wherein the initial first stop layer has a fourth thickness, the fourth thickness being less than the second thickness.

23. The method of forming a semiconductor structure of claim 21, further comprising: etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first stop layer is exposed to form a first mask layer; and etching the initial first stop layer by taking the first mask layer as a mask until the surface of the initial first flat layer is exposed to form a first stop layer.

24. The method of forming a semiconductor structure of claim 23, further comprising: etching the initial first flat layer by taking the first stop layer as a mask until the surface of the layer to be etched is exposed to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

25. The method of forming a semiconductor structure of claim 24, wherein a material of the initial first stop layer comprises a metal oxide.

26. The method of forming a semiconductor structure of claim 24, further comprising: and before etching the initial first stop layer, performing first thinning etching on the side wall of the first mask layer for more than 1 time.

27. The method of forming a semiconductor structure of claim 26, further comprising: and before etching the initial first flat layer, performing second thinning etching on the side wall of the first stop layer for more than 1 time.

28. The method of forming a semiconductor structure of claim 26, wherein a material of the initial first stop layer comprises amorphous silicon.

29. The method of forming a semiconductor structure of claim 21, further comprising: after the initial first stop layer is formed, removing part of the initial first stop layer on the surface of the initial first flat layer to form a first stop layer; after the first stop layer is formed, forming a mask side wall on the surface of the side wall of the first stop layer; after the mask side wall is formed, removing the first stop layer; and after removing the first stop layer, etching the initial first flat layer by using the mask side wall as a mask until the surface of the layer to be etched is exposed to form a first flat layer.

30. The method of forming a semiconductor structure of claim 29, further comprising: and etching the layer to be etched by taking the first flat layer as a mask.

31. The method of forming a semiconductor structure of claim 29, wherein a material of the initial first stop layer comprises amorphous silicon.

32. The method of forming a semiconductor structure of claim 29, wherein forming the first stop layer comprises: removing part of the initial first mask layer on the surface of the initial first stop layer to form a first mask layer; forming a first side wall on the side wall surface of the first mask layer; after the first side wall is formed, removing the first mask layer; and etching the initial first stop layer by taking the first side wall as a mask after the first mask layer is removed until the surface of the initial first flat layer is exposed.

33. The method of forming a semiconductor structure of claim 32, wherein the method of forming the first mask layer comprises: after the second mask layer is formed, forming second side walls on the side wall surfaces of the second mask layer; after the second side wall is formed, removing the second mask layer; and after the second mask layer is removed, etching the initial first mask layer by taking the second side wall as a mask until the surface of the initial first stop layer is exposed.

34. The method of forming a semiconductor structure of claim 29, wherein forming the second mask layer comprises: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein part of the surface of the second mask material layer is exposed out of the photoresist pattern layer; forming a third side wall on the side wall of the photoresist pattern layer; after the third side wall is formed, removing the photoresist pattern layer; and after removing the photoresist pattern layer, etching the second mask material layer by taking the third side wall as a mask until the surface of the initial first mask layer is exposed.