CN113496662A - Fan screen display method and system based on SOC-FPGA - Google Patents
Fan screen display method and system based on SOC-FPGA Download PDFInfo
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- CN113496662A CN113496662A CN202010254153.4A CN202010254153A CN113496662A CN 113496662 A CN113496662 A CN 113496662A CN 202010254153 A CN202010254153 A CN 202010254153A CN 113496662 A CN113496662 A CN 113496662A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/005—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes forming an image using a quickly moving array of imaging elements, causing the human eye to perceive an image which has a larger resolution than the array, e.g. an image on a cylinder formed by a rotating line of LEDs parallel to the axis of rotation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a fan screen display method and system based on SOC-FPGA, comprising the following steps: the SOC chip decodes video data to be displayed and then sends the decoded video data to the FPGA chip at an N-frame refresh rate; the FPGA chip writes in data of odd frames and stores the data in the SRAM module, the data of the next odd frame covers the data of the previous odd frame, the data written in the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing in of the even frame, and the LED lamp bar rotates each time
The FPGA chip drives and refreshes the LED light bar once in time; the distance between a lamp bead on the LED lamp strip and the rotation center is R, the polar coordinates X = RcosA, Y = RsinA, and the FPGA chip acquires all X and Y coordinate values and finally drives the LED lamp strip to display a video. The invention converts the plane coordinate into the polar coordinate through the FPGA chip and drives the LED to display, thereby achieving the purpose of real videoThe effect of the time display.
Description
Technical Field
The invention relates to the technical field of fan screen display, in particular to a fan screen display method and system based on an SOC-FPGA.
Background
When the object moves rapidly, after the image seen by human eyes disappears, the human eyes can still keep the image of the image for about 0.1-0.4 second, and the phenomenon is called persistence of vision. When the human eye views an object, the image is formed on the retina, and the image is input into the human brain by the optic nerve, and the image of the object is sensed. However, when the object is removed, the impression of the object by the optic nerve does not disappear immediately, but lasts for a period of 0.1-0.4 seconds, and this property of the human eye is called "ocular persistence". Similarly, the fan screen displays 3D images using the effect of persistence of vision.
In a fan screen display system in the prior art, video data is generally converted from data of a plane coordinate system into data under a polar coordinate system through an upper computer, a server and the like, and then a lower computer such as a single chip microcomputer, an SOC or an FPGA drives an LED to display a video to be displayed.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a fan screen display method and system based on SOC-FPGA, which convert video data to be displayed from a planar coordinate system to data of a polar coordinate system through an SOC chip and an FPGA chip, thereby realizing real-time decoding and real-time playing of the video data.
The technical scheme of the invention is as follows:
a fan screen display method based on SOC-FPGA comprises the following steps:
the SOC chip decodes video data to be displayed and then sends the decoded video data to the FPGA chip at the refresh rate of N frames;
the FPGA chip writes in data of odd frames and stores the data in the SRAM module, the data of the next odd frame covers the data of the previous odd frame, the data written in the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing in of the even frame, and the LED lamp bar rotates each time
The FPGA chip drives and refreshes the LED light bar once;
assuming that the distance between a lamp bead on the LED lamp strip and a rotation center is R, the polar coordinates X = RcosA and Y = RsinA, the FPGA chip acquires all X and Y coordinate values and data in the SRAM module, and finally drives the LED lamp strip to display a video to be displayed, wherein A is the rotation angle of the LED lamp strip.
Preferably, after the SOC chip decodes the video data to be displayed, before the SOC chip sends the video data to the FPGA chip at a refresh rate of N frames, the method further includes:
when the LED light bar rotates for one circle, the SOC chip calculates the size of sinA and cosA of the LED light bar rotating to each position, and the total calculation is carried out
And secondly, after the FPGA chip is started, the SOC chip sends the calculated sizes of all sinA and cosA to the FPGA chip.
Preferably, the SOC chip sends to the FPGA chip at a refresh rate of 60 frames.
Preferably, the LED light bar rotates once
And driving and refreshing the LED lamp strip once by the FPGA chip.
Preferably, the SOC chip receives video data to be displayed through the WIFI module.
The invention also provides a fan screen display system based on the SOC-FPGA, which comprises the following components:
the SOC chip is used for decoding video data to be displayed and then sending the video data to the FPGA chip at the refresh rate of N frames;
the FPGA chip is used for writing in data of odd frames and storing the data in the SRAM module, the data of the next odd frame covers the data of the previous odd frame, the data written in the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing in of the even frame, and the LED lamp bar rotates every time
The FPGA chip drives and refreshes the LED light bar once, and the lamp beads and the rotating center on the LED light bar are assumedThe distance of the LED lamp strip is R, the polar coordinates X = RcosA, and Y = RsinA, the FPGA chip acquires all X and Y coordinate values and data in the SRAM module, wherein A is the rotating angle of the LED lamp strip;
and the LED light bar is used for rotationally displaying the video to be displayed according to all the coordinate values of X and Y acquired by the FPGA chip and the data in the SRAM module.
Preferably, the SOC-FPGA-based fan screen display system further includes:
the calculation sending module is connected with the SOC chip, and when the LED light bar rotates for one circle, the calculation sending module is used for calculating the sizes of sinA and cosA of the LED light bar rotating to each position, and the total calculation is carried out
And secondly, sending the calculated sizes of all sinA and cosA to the FPGA chip after the FPGA chip is started.
Preferably, the SOC chip sends to the FPGA chip at a refresh rate of 60 frames.
Preferably, the LED light bar rotates once
And driving and refreshing the LED lamp strip once by the FPGA chip.
Preferably, the SOC chip receives video data to be displayed through the WIFI module.
Compared with the prior art, the embodiment of the application mainly has the following beneficial effects:
according to the SOC-FPGA-based fan screen display method and system, the planar coordinate is converted into the polar coordinate through the FPGA chip, data of the polar coordinate are read, and the LED lamp bar is driven to display, so that the effect of displaying videos in real time is achieved.
Drawings
In order to illustrate the solution of the present application more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a schematic flow chart of a preferred embodiment of a fan screen display method based on SOC-FPGA according to the present invention.
FIG. 2 is a flowchart illustrating a method for displaying a fan screen based on SOC-FPGA according to another preferred embodiment of the present invention.
FIG. 3 is a block diagram of a preferred embodiment of a SOC-FPGA based fan-screen display system of the present invention.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions. The terms "first," "second," and the like in the description and claims of this application or in the above-described drawings are used for distinguishing between different objects and not for describing a particular order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
As shown in fig. 1, a fan screen display method based on SOC-FPGA according to a preferred embodiment of the present invention includes the following steps:
s100, after decoding video data to be displayed, the SOC chip sends the video data to the FPGA chip at the refresh rate of N frames;
s200, writing data of odd frames into the FPGA chip, storing the data in an SRAM module, and thenThe data of an odd frame covers the data of the previous odd frame, the data written into the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing into the even frame, and each time the LED lamp bar rotates
The FPGA chip drives and refreshes the LED light bar once;
300. assuming that the distance between a lamp bead on the LED lamp strip and a rotation center is R, the polar coordinates X = RcosA and Y = RsinA, the FPGA chip acquires all X and Y coordinate values and data in the SRAM module, and finally drives the LED lamp strip to display a video to be displayed, wherein A is the rotation angle of the LED lamp strip.
As shown in fig. 2, after the S100 and the SOC chip decode the video data to be displayed, before the SOC chip sends the video data to the FPGA chip at the refresh rate of N frames, the method further includes:
s400, when the LED light bar rotates for one circle, the SOC chip calculates the size of sinA and cosA of the LED light bar rotating to each position, and the total calculation is carried out
And secondly, after the FPGA chip is started, the SOC chip sends the calculated sizes of all sinA and cosA to the FPGA chip.
After the SOC chip is communicated with the FPGA chip, the external SRAM module stores one frame of video data, the SOC chip sends the frame of video data to the FPGA chip at a refresh rate of 60 frames, the FPGA chip writes one frame of data, the second frame gives up writing the data and then drives to refresh the LED light bar, the third frame of data is written to cover the first frame of data, the fourth frame of data gives up and then drives to refresh the LED light bar, the time space changing effect is achieved, and 24 frames of LED display is sequentially driven.
Assuming that the FPGA chip completes driving every 0.2 degree, the accumulated driving times is 360/0.2=1800 times, the radius of the polar coordinate is R, the polar coordinate X = RcosA, and Y = RsinA, and then the FPGA chip reads data in the SRAM module through the acquired X and Y coordinates, and finally drives the LED light bar to display.
As the FPGA chip can not obtain the numerical values of cosA and sinA, the SOC chip calculates 1800 (360/0.2) sinA and cosA data, the SOC chip starts the system and sends the data to the FPGA chip, the FPGA chip stores the data to the internal SRAM module, and the X and Y coordinates are calculated by continuously checking the table, so that the frame buffer data stored by the external SRAM is obtained, and the LED lamp bar is driven to display. Of course, the SOC chip may be other main control chips, such as an MCU chip.
In specific implementation, the WIFI module is used for transmitting video data to be displayed.
According to the invention, the SOC chip and the FPGA chip are used for converting the video plane coordinate data into the polar coordinate data of the fan screen device, so that real-time decoding and real-time playing of the video can be realized, and meanwhile, the speed of the upper computer for transmitting data through WIFI is increased.
As shown in fig. 3, the present invention further provides a fan screen display system based on SOC-FPGA, which includes:
the SOC chip is used for decoding video data to be displayed and then sending the video data to the FPGA chip at the refresh rate of N frames;
the FPGA chip is used for writing in data of odd frames and storing the data in the SRAM module, the data of the next odd frame covers the data of the previous odd frame, the data written in the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing in of the even frame, and the LED lamp bar rotates every time
The FPGA chip drives and refreshes the LED light bar once, assuming that the distance between a lamp bead on the LED light bar and a rotation center is R, the polar coordinates are X = RcosA and Y = RsinA, and the FPGA chip acquires coordinate values of all X and Y and data in the SRAM module, wherein A is the rotation angle of the LED light bar;
and the LED light bar is used for rotationally displaying the video to be displayed according to all the coordinate values of X and Y acquired by the FPGA chip and the data in the SRAM module.
In a further preferred embodiment of the present invention, the SOC-FPGA-based fan screen display system further includes:
the calculation sending module is connected with the SOC chip and used as an LED lampWhen the strip rotates for one circle, the calculation and sending module is used for calculating the sizes of sinA and cosA of the LED light bar rotating to various positions, and the total calculation is carried out
And secondly, sending the calculated sizes of all sinA and cosA to the FPGA chip after the FPGA chip is started.
In specific implementation, the SOC chip sends the refresh rate of 60 frames to the FPGA chip, and each time the LED light bar rotates, the LED light bar is sent to the FPGA chip
And driving and refreshing the LED lamp strip once by the FPGA chip.
In specific implementation, the SOC receives video data to be displayed through the WIFI module.
The method can be applied to naked eye 3D advertisement putting, naked eye 3D video live broadcasting, naked eye 3D holographic displays and multi-display equipment splicing of fan screens based on an FPGA (field programmable gate array) planar coordinate conversion polar coordinate algorithm.
In summary, the fan screen display method and system based on SOC-FPGA provided by the present invention includes the following steps: the SOC chip decodes video data to be displayed and then sends the decoded video data to the FPGA chip at the refresh rate of N frames; the FPGA chip writes in data of odd frames and stores the data in the SRAM module, the data of the next odd frame covers the data of the previous odd frame, the data written in the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing in of the even frame, and the LED lamp bar rotates each time
The FPGA chip drives and refreshes the LED light bar once; assuming that the distance between a lamp bead on the LED lamp strip and a rotation center is R, the polar coordinates X = RcosA and Y = RsinA, the FPGA chip acquires all X and Y coordinate values and data in the SRAM module, and finally drives the LED lamp strip to display a video to be displayed, wherein A is the rotation angle of the LED lamp strip, so that the planar coordinate is converted into the polar coordinate through the FPGA chip, and then the polar coordinate data is read and the video is driven to be displayedAnd the LED lamp strip is moved to display, so that the effect of real-time video display is achieved.
It is to be understood that the above-described embodiments are merely illustrative of some, but not restrictive, of the broad invention, and that the appended drawings illustrate preferred embodiments of the invention and do not limit the scope of the invention. This application is capable of embodiments in many different forms and is provided for the purpose of enabling a thorough understanding of the disclosure of the application. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to one skilled in the art that the present application may be practiced without modification or with equivalents of some of the features described in the foregoing embodiments. All equivalent structures made by using the contents of the specification and the drawings of the present application are directly or indirectly applied to other related technical fields and are within the protection scope of the present application.
Claims (10)
1. A fan screen display method based on SOC-FPGA is characterized by comprising the following steps:
the SOC chip decodes video data to be displayed and then sends the decoded video data to the FPGA chip at the refresh rate of N frames;
the FPGA chip writes in data of odd frames and stores the data in the SRAM module, the data of the next odd frame covers the data of the previous odd frame, the data written in the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing in of the even frame, and the LED lamp bar rotates each time
The FPGA chip drives and refreshes the LED light bar once;
assuming that the distance between a lamp bead on the LED lamp strip and a rotation center is R, the polar coordinates X = RcosA and Y = RsinA, the FPGA chip acquires all X and Y coordinate values and data in the SRAM module, and finally drives the LED lamp strip to display a video to be displayed, wherein A is the rotation angle of the LED lamp strip.
2. The SOC-FPGA-based fan screen display method of claim 1, wherein after the SOC chip decodes the video data to be displayed, before the SOC chip sends the video data to the FPGA chip at a refresh rate of N frames, the method further comprises:
when the LED light bar rotates for one circle, the SOC chip calculates the size of sinA and cosA of the LED light bar rotating to each position, and the total calculation is carried out
And secondly, after the FPGA chip is started, the SOC chip sends the calculated sizes of all sinA and cosA to the FPGA chip.
3. The SOC-FPGA-based fan screen display method of claim 2, wherein the SOC chip sends to the FPGA chip at a refresh rate of 60 frames.
4. The SOC-FPGA-based fan screen display method of claim 3, wherein the LED light bar rotates each time
And driving and refreshing the LED lamp strip once by the FPGA chip.
5. The SOC-FPGA-based fan screen display method of claim 4, wherein the SOC chip receives video data to be displayed through a WIFI module.
6. A fan screen display system based on SOC-FPGA is characterized by comprising:
the SOC chip is used for decoding video data to be displayed and then sending the video data to the FPGA chip at the refresh rate of N frames;
the FPGA chip is used for writing in data of odd frames and storing the data in the SRAM module, the data of the next odd frame covers the data of the previous odd frame, the data written in the even frame is abandoned, and the LED lamp bar is driven and refreshed in the time period of abandoning the writing in of the even frame, and the LED lamp bar rotates every time
The FPGA chip drives and refreshes the LED light bar once, assuming that the distance between a lamp bead on the LED light bar and a rotation center is R, the polar coordinates are X = RcosA and Y = RsinA, and the FPGA chip acquires coordinate values of all X and Y and data in the SRAM module, wherein A is the rotation angle of the LED light bar;
and the LED light bar is used for rotationally displaying the video to be displayed according to all the coordinate values of X and Y acquired by the FPGA chip and the data in the SRAM module.
7. The SOC-FPGA based fan screen display system of claim 6, further comprising:
the calculation sending module is connected with the SOC chip, and when the LED light bar rotates for one circle, the calculation sending module is used for calculating the sizes of sinA and cosA of the LED light bar rotating to each position, and the total calculation is carried out
And secondly, sending the calculated sizes of all sinA and cosA to the FPGA chip after the FPGA chip is started.
8. The SOC-FPGA based fanscreen display system of claim 7, wherein the SOC chip sends to the FPGA chip at a refresh rate of 60 frames.
9. The SOC-FPGA-based fan screen display system of claim 8, wherein the LED light bar rotates each time
And driving and refreshing the LED lamp strip once by the FPGA chip.
10. The SOC-FPGA based fan screen display system of claim 9, wherein said SOC chip receives video data to be displayed via a WIFI module.
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