CN113495283B - Beidou broadband interference resistant module, antenna and terminal - Google Patents
Beidou broadband interference resistant module, antenna and terminal Download PDFInfo
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- CN113495283B CN113495283B CN202010268967.3A CN202010268967A CN113495283B CN 113495283 B CN113495283 B CN 113495283B CN 202010268967 A CN202010268967 A CN 202010268967A CN 113495283 B CN113495283 B CN 113495283B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/21—Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
- G01S19/37—Hardware or software details of the signal processing chain
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Abstract
The application discloses a Beidou broadband interference resistant module, an antenna and a terminal, and belongs to the technical field of wireless. The anti-broadband interference module of big dipper includes: a radio frequency sub-module and a baseband sub-module integrated together; the radio frequency sub-module comprises m N-channel radio frequency chips, wherein each N-channel radio frequency chip is used for simultaneously receiving N identical first analog signals and outputting N second analog signals; the baseband submodule comprises m N-channel analog-to-digital conversion chips and an FPGA chip, wherein the N-channel analog-to-digital conversion chips are used for receiving N second analog signals output by corresponding N-channel radio frequency chips and converting the received N second analog signals into serial digital signals, and the FPGA chip is used for performing broadband interference resistance processing on the serial digital signals output by each N-channel analog-to-digital conversion chip. The technical scheme provided by the embodiment of the application can resist broadband interference to the signals of the Beidou satellite navigation system.
Description
Technical Field
The application relates to the technical field of wireless communication, in particular to a Beidou broadband interference resistant module, an antenna and a terminal.
Background
With the gradual perfection of the Beidou satellite navigation system, the Beidou satellite navigation product has realized large-scale popularization and promotion in the civil field and the military field, and gets rid of the restriction of foreign navigation systems.
However, in practical application, since the signal frequency characteristic and the modulation characteristic of the beidou satellite navigation system are well known, and the signal carrier-to-noise ratio of the beidou satellite navigation system is low, the signal of the beidou satellite navigation system is easy to be interfered by broadband, and the broadband interference refers to that a malicious user deliberately transmits a signal with a frequency domain width covering the whole frequency band on the frequency band of the beidou satellite navigation system, so that the signal of the beidou satellite navigation system is interfered.
The function of the Beidou satellite navigation system is likely to be disabled due to broadband interference. Thus, there is a need for a device that can resist broadband interference.
Disclosure of Invention
Based on the above, the embodiment of the application provides a Beidou broadband interference resistant module, an antenna and a terminal, which can resist broadband interference to signals of a Beidou satellite navigation system.
In a first aspect, a Beidou broadband interference resistant module is provided, and comprises a radio frequency sub-module and a baseband sub-module which are integrated together;
the radio frequency sub-module comprises m N-channel radio frequency chips, wherein each N-channel radio frequency chip is used for simultaneously receiving N identical first analog signals and outputting N second analog signals, and m and N are integers larger than 1;
The baseband submodule comprises m N-channel analog-to-digital conversion chips and an FPGA chip, wherein the m N-channel analog-to-digital conversion chips are in one-to-one correspondence with the m N-channel radio frequency chips, the N-channel analog-to-digital conversion chips are used for receiving N second analog signals output by the corresponding N-channel radio frequency chips and converting the received N second analog signals into serial digital signals, and the FPGA chip is used for performing broadband interference resistance processing on the serial digital signals output by the N-channel analog-to-digital conversion chips and outputting the processed digital signals.
In one embodiment, the baseband sub-module further includes a DSP chip;
the DSP chip is used for receiving the anti-interference configuration parameters and controlling the FPGA chip to perform broadband interference resistance processing according to the anti-interference configuration parameters.
In one embodiment, the DSP chip is further configured to read interference processing data in the FPGA chip, and output at least one of an interference incoming wave direction, interference power, and an interference number according to the interference processing data, where the interference processing data is obtained by the FPGA chip during the anti-broadband interference processing.
In one embodiment, the baseband sub-module further includes a first memory, the first memory storing the anti-interference configuration parameter, and the DSP chip is configured to read the anti-interference configuration parameter from the first memory after power-up.
In one embodiment, the baseband submodule further includes a second memory, the second memory stores an anti-wideband interference processing program, and the FPGA chip is configured to read the anti-wideband interference processing program from the second memory after power is on, and perform anti-wideband interference processing based on the anti-wideband interference processing program.
In one embodiment, the FPGA chip outputs P processed digital signals, the baseband submodule further includes a P-channel digital-to-analog conversion chip, the radio frequency submodule further includes P up-conversion circuits, and P is a positive integer;
the P-channel digital-to-analog conversion chip is used for converting the P processed digital signals into P third analog signals;
Each up-conversion circuit is used for carrying out frequency mixing processing on the third analog signal and local oscillation signals output by the m N-channel radio frequency chips, and outputting a fourth analog signal obtained after the frequency mixing processing from the Beidou broadband interference resistant module.
In one embodiment, the first analog signal is a single-ended analog signal, the second analog signal is a differential intermediate frequency analog signal, and the radio frequency sub-module includes m first transformer groups corresponding to the m N-channel radio frequency chips one by one, and m second transformer groups corresponding to the m N-channel radio frequency chips one by one;
Each first transformer group comprises N first transformers, each first transformer is used for receiving one first analog signal and coupling the received first analog signal into a differential analog signal to be input to a corresponding N-channel radio frequency chip;
Each second transformer group comprises N second transformers, and each second transformer is used for receiving one second analog signal output by the corresponding N-channel radio frequency chip, converting the received second analog signal into a single-ended intermediate frequency analog signal and outputting the single-ended intermediate frequency analog signal to the corresponding N-channel analog-to-digital conversion chip.
In one embodiment, the rf sub-module includes m intermediate frequency filter banks corresponding to the m second transformer banks one to one, each intermediate frequency filter bank including N intermediate frequency filters;
Each intermediate frequency filter is used for receiving the single-ended intermediate frequency analog signal output by one second transformer in the corresponding second transformer group, filtering the received single-ended intermediate frequency analog signal, and outputting the single-ended intermediate frequency analog signal subjected to filtering to the corresponding N-channel analog-to-digital conversion chip.
In one embodiment, the third analog signal is a differential analog signal, and the rf sub-module further includes P third transformers;
each third transformer is used for converting one third analog signal into a single-ended analog signal;
The up-conversion circuit is used for carrying out frequency mixing processing on the single-ended analog signal and local oscillation signals output by the m N-channel radio frequency chips, and outputting a fourth analog signal obtained after the frequency mixing processing from the Beidou broadband interference resistant module
In a second aspect, a Beidou broadband interference resistant antenna is provided, and the Beidou broadband interference resistant antenna comprises an antenna array, a low noise amplifier group and the Beidou broadband interference resistant module according to any one of the first aspect.
In a third aspect, a Beidou broadband interference resistant terminal is provided, where the Beidou broadband interference resistant terminal includes the Beidou broadband interference resistant antenna in the second aspect.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least:
The Beidou broadband interference resistant module comprises a radio frequency sub-module and a baseband sub-module, wherein the radio frequency sub-module comprises m N-channel radio frequency chips, each N-channel radio frequency chip is used for simultaneously receiving N identical first analog signals and outputting N second analog signals, the baseband sub-module comprises an FPGA chip and m N-channel analog-to-digital conversion chips which are in one-to-one correspondence with the m N-channel radio frequency chips, the N-channel analog-to-digital conversion chips are used for receiving the N second analog signals output by the corresponding N-channel radio frequency chips and converting the received N second analog signals into serial digital signals, and the FPGA chip is used for carrying out broadband interference resistant processing on the serial digital signals output by each N-channel analog-to-digital conversion chip and outputting the processed digital signals.
Drawings
Fig. 1 is a block diagram of a Beidou broadband interference resistant module provided by an embodiment of the present application;
fig. 2 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application;
fig. 3 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application;
fig. 4 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application;
fig. 5 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application;
fig. 6 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application;
fig. 7 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application;
Fig. 8 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application;
Fig. 9 is a block diagram of another beidou broadband interference resistant module provided by an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1, a schematic diagram of a beidou anti-broadband interference module provided by an embodiment of the present application is shown. As shown in fig. 1, the beidou anti-broadband interference module may include a radio frequency sub-module 10 and a baseband sub-module 20 integrated together.
The rf sub-module 10 includes m N-channel rf chips 101, where each N-channel rf chip 101 is configured to simultaneously receive N identical first analog signals a and output N second analog signals b, where m and N are integers greater than 1.
It should be noted that "receiving" in the embodiment of the present application may refer to direct receiving or indirect receiving through other circuit devices, and "output" in the embodiment of the present application may refer to direct output or indirect output through other circuit devices.
The baseband sub-module 20 includes m N-channel analog-to-digital conversion chips 201 and an FPGA chip 202, where the m N-channel analog-to-digital conversion chips 201 are in one-to-one correspondence with the m N-channel radio frequency chips 101 described above.
The N-channel analog-to-digital conversion chip 201 is configured to receive N second analog signals b output by the corresponding N-channel radio frequency chip 101, and sample and quantize the received N second analog signals b, thereby converting the received N second analog signals b into a serial digital signal c.
The FPGA chip 202 is configured to perform anti-wideband interference processing on the serial digital signals c output by the N-channel analog-to-digital conversion chips 201, and output a processed digital signal d.
In an alternative embodiment of the present application, the process of anti-broadband processing by FPGA chip 202 may include: the serial digital signal is converted into a parallel digital signal, the parallel digital signal is converted into a quadrature baseband signal through digital quadrature down-conversion, interference in the quadrature baseband signal is filtered, digital up-conversion is completed, and the quadrature baseband signal after interference filtering is converted into a digital intermediate frequency signal. In other words, the processed digital signal d is a digital intermediate frequency signal.
In an alternative embodiment of the present application, the value of m may be 2, and the value of n may be 4, that is, the rf sub-module 10 may include 2 4-channel rf chips, the baseband sub-module 20 may include 2 4-channel analog-to-digital conversion chips, and fig. 1 also illustrates that the rf sub-module 10 includes 2 4-channel rf chips and the baseband sub-module 20 includes 2 4-channel analog-to-digital conversion chips. The drawings herein are each exemplarily drawn with a value of m being 2 and a value of n being 4.
In an alternative embodiment of the present application, the 4-channel RF chip described above may be selected from CA-RF1947 developed by Shanghai Chuan-Mimo, inc. The main functions and features of CA-RF1947 are as follows:
CA-RF1947 is a 4-channel radio frequency chip working at 1.1 GHz-1.7 GHz and 2.3 GHz-2.7 GHz, supports to receive the analog signals (radio frequency signals) of 4 same frequency points simultaneously, and can form an anti-interference array receiver. CA-RF1947 integrates 4 independent down-conversion receive channels and a low noise fractional frequency synthesizer and sampling clock circuit. CA-RF1947 supports internal local oscillation and external local oscillation modes, and is convenient for the expansion application of a plurality of chips. CA-RF1947 has extremely high linearity and low noise characteristics, and can be used for constructing an anti-interference array receiver by using a small number of external passive devices. CA-RF1947 has high linearity and high isolation.
In an alternative embodiment of the present application, the 4-channel analog-to-digital conversion chip described above may be selected from BLAD16Q125 developed by Shanghai Beehive, inc. The features and functions of BLAD16Q125 are as follows:
BLAD16Q125 is a 4-channel, 16-bit analog-to-digital converter. BLAD16Q125 built-in sample-and-hold circuits are designed specifically for low power consumption, small size and ease of use. The conversion rate of BLAD16Q125 can reach 125MSPS, and the BLAD16Q125 has outstanding dynamic performance and low power consumption characteristics, and is suitable for application of emphasized small package size. Many application requirements can be met without an external reference voltage source or driving device. BLAD16Q125 built-in PLL automatically multiplies the sampling clock, thereby generating an appropriate LVDS serial data rate. It provides a Data Clock Output (DCO) for capturing data at the output and a Frame Clock Output (FCO) for sending the new output byte signal.
The embodiment of the application provides a Beidou broadband interference resistant module, which comprises a radio frequency sub-module and a baseband sub-module which are integrated together, wherein the radio frequency sub-module comprises m N-channel radio frequency chips, each N-channel radio frequency chip is used for simultaneously receiving N identical first analog signals and outputting N second analog signals, the baseband sub-module comprises an FPGA chip and m N-channel analog-to-digital conversion chips which are in one-to-one correspondence with the m N-channel radio frequency chips, the N-channel analog-to-digital conversion chips are used for receiving the N second analog signals output by the corresponding N-channel radio frequency chips and converting the received N second analog signals into serial digital signals, and the FPGA chip is used for carrying out broadband interference resistant processing on the serial digital signals output by each N-channel analog-to-digital conversion chip and outputting the processed digital signals.
Meanwhile, the Beidou broadband interference resistant module integrates the radio frequency sub-module and the baseband sub-module, so that the size of the Beidou broadband interference resistant module can be reduced, and hardware multiplexing and general modular design can be realized to the greatest extent.
In addition, the N-channel radio frequency chip and the N-channel analog-to-digital conversion chip are arranged in the beidou anti-broadband interference module, the same N identical first analog signals can be processed at the same time, instead of the N discrete radio frequency chips and the N discrete analog-to-digital conversion chips which are used for respectively processing the N identical first analog signals, in practical application, the noise, amplitude, gain, phase and other indexes of each discrete device are required to be ensured to be within an error range based on an anti-interference circuit of the discrete device, consistency is ensured, meanwhile, isolation is required to be ensured to meet the index requirement, so that design complexity and debugging difficulty are high, and meanwhile, due to the fact that the number of the anti-interference circuits is large, power consumption is also large, the beidou anti-broadband interference module provided by the embodiment of the application is provided with the N-channel radio frequency chips and the N-channel analog-to-digital conversion chips, compared with the N discrete radio frequency chips and the N discrete analog-to-digital conversion chips, design complexity and debugging difficulty are reduced, and energy consumption and volume of the beidou anti-broadband interference module are reduced.
Referring to fig. 2, in an alternative embodiment of the present application, the baseband sub-module 20 in the beidou anti-wideband interference module may further include a DSP chip 203.
The DSP chip 203 is configured to receive the anti-interference configuration parameter, and control the FPGA chip 202 to perform anti-wideband interference processing according to the anti-interference configuration parameter.
In another optional embodiment of the present application, the DSP chip 203 is further configured to read interference processing data in the FPGA chip 202, and output at least one of an interference incoming wave direction, interference power, and interference number according to the read interference processing data, where the interference processing data is acquired by the FPGA chip 202 during the broadband interference rejection processing.
Referring to fig. 3, in an alternative embodiment of the present application, the baseband sub-module 20 in the beidou anti-wideband interference module may further include a first memory 204, where the first memory 204 stores the anti-interference configuration parameter described above, and the DSP chip 203 is configured to read the anti-interference configuration parameter from the first memory 204 after power-up.
Referring to fig. 4, in an alternative embodiment of the present application, the baseband sub-module 20 in the beidou anti-wideband interference module may further include a second memory 205, where an anti-wideband interference processing program is stored in the second memory 205, and the FPGA chip 202 is configured to read the anti-wideband interference processing program from the second memory 205 after power-up, and perform anti-wideband interference processing based on the anti-wideband interference processing program.
In an alternative embodiment of the present application, the FPGA chip 202 may output P processed digital signals d, referring to fig. 5, the baseband sub-module 20 may further include a P-channel digital-to-analog conversion chip 206, and the rf sub-module 10 may further include P up-conversion circuits 102, where P is a positive integer.
The P-channel digital-to-analog conversion chip 206 is configured to convert the P processed digital signals d into P third analog signals e.
Each up-conversion circuit 102 is configured to perform mixing processing on a third analog signal e and the local oscillation signals z output by the m N-channel radio frequency chips 101, and output a fourth analog signal f obtained after the mixing processing from the beidou broadband interference resistant module.
In an alternative embodiment of the present application, the third analog signal e may be a differential analog signal, referring to fig. 6, and as shown in fig. 6, the rf sub-module 10 in the beidou anti-wideband interference module may further include P third transformers 103.
Each third transformer 103 is configured to convert a third analog signal e into a single-ended analog signal.
Correspondingly, each up-conversion circuit 102 is configured to perform mixing processing on a single-ended analog signal converted by the third transformer 103 and local oscillation signals output by the m N-channel radio frequency chips 101, and output a fourth analog signal f obtained after the mixing processing from the beidou broadband interference resistant module.
It should be noted that in an alternative embodiment of the present application, the value of P may be 2, and in fig. 5 and 6, only the value of P is illustrated as 2. That is, the FPGA chip 202 may output 2 processed digital signals d, the baseband sub-module 20 is provided with a 2-channel digital-to-analog conversion chip, the 2-channel digital-to-analog conversion chip may convert the 2 processed digital signals d into 2 third analog signals e, the rf sub-module 10 is provided with 2 third transformers, each third transformer is configured to convert one third analog signal e into a single-ended analog signal, and meanwhile, the rf sub-module 10 is provided with 2 up-conversion circuits, where each up-conversion circuit is configured to perform mixing processing on the single-ended analog signals output by the 1 third transformer and the local oscillation signals z output by the m N-channel rf chips 101, and output a fourth analog signal f obtained after the mixing processing from the beidou anti-wideband interference module.
In an alternative embodiment of the application, the first analog signal a may be a single-ended analog signal and the second analog signal b may be a differential intermediate frequency analog signal.
Referring to fig. 7, the rf sub-module 10 in the beidou anti-wideband interference module may further include m first transformer groups 104 corresponding to the m N-channel rf chips 101 one by one, and m second transformer groups 105 corresponding to the m N-channel rf chips 101 one by one.
Each first transformer set 104 includes N first transformers, each first transformer is configured to receive a first analog signal a, and couple the received first analog signal a into a differential analog signal, and input the differential analog signal to the corresponding N-channel radio frequency chip 101.
In other words, the N-channel rf chip 101 may indirectly receive the first analog signal a through the first transformer bank 104.
Each second transformer group 105 includes N second transformers, and each second transformer is configured to receive one second analog signal b output by the corresponding N-channel radio frequency chip 101, and convert the received second analog signal b into a single-ended intermediate frequency analog signal, and output the single-ended intermediate frequency analog signal to the corresponding N-channel analog-to-digital conversion chip 201.
Referring to fig. 8, in an alternative embodiment of the present application, the rf sub-module 10 in the beidou anti-wideband interference module may further include m intermediate frequency filter banks 106 corresponding to the m second transformer banks 105 one to one, where each intermediate frequency filter bank 106 includes N intermediate frequency filters.
Each intermediate frequency filter is configured to receive a single-ended intermediate frequency analog signal output by one second transformer in the corresponding second transformer bank 105, and perform filtering processing on the received single-ended intermediate frequency analog signal, so as to obtain a filtered single-ended intermediate frequency analog signal, and output the filtered single-ended intermediate frequency analog signal to the corresponding N-channel analog-to-digital conversion chip 201.
In other words, the N-channel rf chip 101 may indirectly output the second analog signal b through the second transformer bank 105 and the intermediate frequency filter bank 106.
Correspondingly, the N-channel analog-to-digital conversion chip 201 is configured to receive the N single-ended intermediate frequency analog signals subjected to filtering output by the corresponding intermediate frequency filter bank 106, and sample and quantize the received N single-ended intermediate frequency analog signals subjected to filtering, so as to convert the received N single-ended intermediate frequency analog signals subjected to filtering into the serial digital signal c.
It should be noted that the circuit devices shown in fig. 1 to 8 in the embodiments of the present application may be arbitrarily combined to form the beidou anti-broadband interference module finally provided in the embodiments of the present application.
Referring to fig. 9, a schematic diagram of an exemplary beidou anti-broadband interference module after circuit device assembly is shown.
As shown in fig. 9, the beidou broadband interference resistant module may include a radio frequency sub-module and a baseband sub-module.
The radio frequency sub-module may include 2 4-channel radio frequency chips, 2 first transformer banks, 2 second transformer banks, 2 intermediate frequency filter banks, 2 third transformers, and 2 up-conversion circuits.
Each first transformer group comprises 4 first transformers, each second transformer group comprises 4 second transformers, and each intermediate frequency filter group comprises 4 intermediate frequency filters.
The baseband sub-module may include 2 4-channel analog-to-digital conversion chips, an FPGA chip, a DSP chip, a first memory, a second memory, and a 2-channel digital-to-analog conversion chip.
The first memory stores anti-interference configuration parameters, the DSP chip can read the anti-interference configuration parameters from the first memory after power-on, and the DSP chip can control the FPGA chip to perform broadband anti-interference processing according to the anti-interference configuration parameters.
The second memory stores broadband interference processing program, and the FPGA chip can read the broadband interference resisting processing program from the second memory after being electrified and perform broadband interference resisting processing based on the broadband interference resisting processing program.
As shown IN fig. 9, RFk-IN (k is an integer having a value of 1 to 8) is the same single-ended analog signal, after RFk-IN is input to the first transformer, the first transformer may couple it into differential analog signals rfk_p and rfk_n (k is an integer having a value of 1 to 8) to be input to the 4-channel rf chip, the 4-channel rf chip may output differential intermediate frequency analog signals ifk_p and ifk_n to the second transformer, the second transformer may couple the differential intermediate frequency analog signals ifk_p and ifk_n (k is an integer having a value of 1 to 8) into a single-ended intermediate frequency analog signal IFk (k is an integer having a value of 1 to 8), the single-ended intermediate frequency analog signal IFk may output a relatively flat and pure intermediate frequency analog signal after being filtered by the intermediate frequency filter, the 4-channel analog-to-digital conversion chip can convert the intermediate frequency analog signals output by each intermediate frequency filter into serial digital signals and input the serial digital signals into an FPGA chip, the FPGA chip can convert the serial digital signals into parallel digital signals, the parallel digital signals are converted into quadrature baseband signals through digital quadrature down-conversion, interference IN the quadrature baseband signals is filtered, digital up-conversion is completed, the quadrature baseband signals after interference filtering are converted into digital intermediate frequency signals DA1 and DA2 for output, the 2-channel digital-to-analog conversion chip can receive the digital intermediate frequency signals DA1 and DA2 and output differential analog signals DA1_p/n and DA2_p/n, the differential analog signals DA1_p/n and DA2_p/n can output single-ended analog signals DA1_out and DA2_out after being coupled through a third transformer, the up-conversion circuit can respectively carry out frequency mixing processing on the da1_out and the da2_out and local oscillation signals output by the 4-channel radio frequency chip, and outputs analog signals RF1_out and RF2_out obtained after the frequency mixing processing from the Beidou broadband interference resistant module.
As shown in fig. 9, the beidou broadband interference prevention module may further include a power supply part, where the power supply part may convert an externally input voltage into a voltage required by each device, so as to ensure normal operation of each device in the beidou broadband interference prevention module, and an output voltage range of the power supply part is 5±0.2V.
The embodiment of the application also provides a Beidou broadband interference resistant antenna which comprises an antenna array, a low-noise amplifier group and the Beidou broadband interference resistant module in any embodiment.
The antenna array can receive signals transmitted by the Beidou navigation satellite system, the low-noise amplification group can amplify the signals received by the antenna array, and the amplified signals are input into the Beidou broadband interference resistant module.
The Beidou broadband interference resistant module can conduct broadband interference resistant processing on signals input by the low-noise amplification group and output signals subjected to broadband interference resistant processing to the low-noise amplification group.
In a third aspect, a Beidou broadband interference resistant terminal is provided, where the Beidou broadband interference resistant terminal includes the Beidou broadband interference resistant antenna described in the foregoing embodiment.
Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (SYNCHLINK) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (9)
1. The Beidou broadband interference resistant module is characterized by comprising a radio frequency sub-module and a baseband sub-module which are integrated together;
the radio frequency sub-module comprises m N-channel radio frequency chips, wherein each N-channel radio frequency chip is used for simultaneously receiving N identical first analog signals and outputting N second analog signals, and m and N are integers larger than 1;
The baseband submodule comprises m N-channel analog-to-digital conversion chips, an FPGA chip and a P-channel digital-to-analog conversion chip;
The m N-channel analog-to-digital conversion chips are in one-to-one correspondence with the m N-channel radio frequency chips, and the N-channel analog-to-digital conversion chips are used for receiving N second analog signals output by the corresponding N-channel radio frequency chips and converting the received N second analog signals into serial digital signals;
the FPGA chip is used for converting serial digital signals output by the N-channel analog-to-digital conversion chips into parallel digital signals, converting the parallel digital signals into quadrature baseband signals through digital quadrature down-conversion, filtering interference in the quadrature baseband signals, converting the quadrature baseband signals after interference filtering into digital intermediate frequency signals, and outputting P digital intermediate frequency signals by the FPGA chip, wherein P is a positive integer;
the P-channel digital-to-analog conversion chip is used for converting the P digital intermediate frequency signals into P third analog signals, wherein the third analog signals are differential analog signals;
the radio frequency sub-module further comprises P up-conversion circuits;
Each up-conversion circuit is used for carrying out frequency mixing processing on one third analog signal and local oscillation signals output by the m N-channel radio frequency chips, and outputting a fourth analog signal obtained after the frequency mixing processing from the Beidou broadband interference resistant module.
2. The Beidou anti-broadband interference module of claim 1, wherein the baseband submodule further comprises a DSP chip;
The DSP chip is used for receiving the anti-interference configuration parameters and controlling the FPGA chip to perform broadband interference resistance processing according to the anti-interference configuration parameters.
3. The big dipper broadband interference prevention module of claim 2, wherein the DSP chip is further configured to read interference processing data in the FPGA chip, and output at least one of an interference incoming wave direction, interference power, and interference number according to the interference processing data, where the interference processing data is obtained by the FPGA chip during the broadband interference prevention processing.
4. The big dipper broadband interference prevention module of claim 2, wherein the baseband sub-module further comprises a first memory, the first memory stores the interference prevention configuration parameter, and the DSP chip is configured to read the interference prevention configuration parameter from the first memory after power-up.
5. The big dipper broadband interference prevention module of any one of claims 1 to 4, wherein the baseband sub-module further comprises a second memory, the second memory stores a broadband interference prevention processing program, and the FPGA chip is configured to read the broadband interference prevention processing program from the second memory after power-up, and perform broadband interference prevention processing based on the broadband interference prevention processing program.
6. The Beidou anti-broadband interference module of claim 1, wherein the first analog signal is a single-ended analog signal, the second analog signal is a differential intermediate frequency analog signal, and the radio frequency sub-module comprises m first transformer groups in one-to-one correspondence with the m N-channel radio frequency chips and m second transformer groups in one-to-one correspondence with the m N-channel radio frequency chips;
Each first transformer group comprises N first transformers, each first transformer is used for receiving one first analog signal, coupling the received first analog signals into differential analog signals and inputting the differential analog signals to a corresponding N-channel radio frequency chip;
Each second transformer group comprises N second transformers, and each second transformer is used for receiving one second analog signal output by the corresponding N-channel radio frequency chip, converting the received second analog signal into a single-ended intermediate frequency analog signal and outputting the single-ended intermediate frequency analog signal to the corresponding N-channel analog-to-digital conversion chip.
7. The Beidou anti-broadband interference module of claim 6, wherein the radio frequency sub-module comprises m intermediate frequency filter banks in one-to-one correspondence with the m second transformer banks, each intermediate frequency filter bank comprising N intermediate frequency filters;
Each intermediate frequency filter is used for receiving a single-ended intermediate frequency analog signal output by one second transformer in the corresponding second transformer group, filtering the received single-ended intermediate frequency analog signal, and outputting the single-ended intermediate frequency analog signal subjected to filtering to the corresponding N-channel analog-to-digital conversion chip.
8. The Beidou broadband interference resistant antenna is characterized by comprising an antenna array, a low-noise amplifier group and the Beidou broadband interference resistant module as claimed in any one of claims 1 to 7.
9. The Beidou broadband interference resistant terminal is characterized by comprising the Beidou broadband interference resistant antenna of claim 8.
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