CN113490983B - Method and apparatus for NAND flash memory - Google Patents

Abstract

Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method for programming a NAND flash memory is provided. The method comprises the following steps: pre-powering up a selected bit line of a selected memory cell with a bias voltage level while unselected bit lines maintain an inhibit voltage; applying a verify voltage to a selected word line coupled to a selected memory cell; and discharging the selected bit line coupled to the turned-on cell for a first time interval. The method further comprises the following steps: sensing a sense voltage level on the selected bit line; loading the selected bit line with an inhibit voltage level when the sense voltage level is above the threshold level and loading the selected bit line with a program voltage when the sense voltage level is equal to or below the threshold level; and repeating the sensing and loading operations for each selected bit line.

Description

Method and apparatus for NAND flash memory

Cross Reference to Related Applications

This application is a partially-filed patent application (CIP) with united states patent application number 16/687,556 entitled "METHODS AND APPARATUS FOR NAND flash MEMORY (METHODS AND APPARATUS FOR NAND FLASH MEMORY"), filed on 18/11/2019. The CIP application claims an interest in 35 u.s.c. 119 in accordance with U.S. provisional patent application No. 62/884,139 entitled "NAND Flash Memory Read and Write Operations" filed 5.5.2019, an united states provisional patent application No. 62/843,556 entitled "NAND Flash Memory Read and Write Operations" filed 5.15.2019, an united states provisional patent application No. 62/848,567 entitled "NAND Flash Memory Read and Write Operations", filed 7.7.2019, an united states provisional patent application No. 62/871,198 entitled "NAND Flash Memory Read and Write Operations", and an united states provisional patent application No. 62/884,139 filed 8.7.2019, all of these U.S. provisional patent applications are incorporated by reference herein in their entirety.

Application 16/687,556 claims that U.S. provisional patent application No. 62/768,979 entitled "NAND Flash Memory Read and Write Operations (NAND Flash Memory Read and Write Operations)" filed on 18.11.18.2018, U.S. provisional patent application No. 62/770,150 entitled "NAND Flash Memory Read and Write Operations (NAND Flash Memory Read and Write Operations)" filed on 20.11.20.2018, U.S. provisional patent application No. 62/774,128 entitled "NAND Flash Memory Read and Write Operations" filed on 30.12.20.2018, U.S. provisional patent application No. 62/783,199 entitled "NAND Flash Memory Read and Write Operations" filed on 31.1.31.2018, and "NAND Flash Memory Read and Write Operations (NAND Flash Memory Read and Write Operations)" filed on 31.1.31.2019 Read and Write Operations) "us provisional patent application No. 62/799,669, entitled 35 u.s.c. § 119, all of which are incorporated herein by reference in their entirety.

Technical Field

Exemplary embodiments of the invention relate generally to the field of semiconductors and integrated circuits, and more particularly to the design and operation of NAND flash memories (flash memories).

Background

Storage devices are widely used in industrial and consumer electronics. In many cases, the limitations of memory affect the size, performance, or cost of industrial or consumer devices such as mobile phones.

One type of memory used in many devices is referred to as NAND flash memory. This type of memory is organized into one or more blocks, and each block includes strings of memory cells accessed by word lines and bit lines. Data is programmed into or read from the memory cells using page buffers coupled to the bit lines. In a typical NAND flash memory, the number of bit lines that can be programmed or read at one time is equal to the number of page buffers. This is called "page programming" or "page reading". Increasing the number of page buffers may increase data read/write throughput to enhance memory performance. However, the circuit size of the page buffer is quite large, and typically occupies about 20% to 40% of the die size of the memory. Therefore, the typical number of page buffers is limited to the range of 16Kb to 64Kb in today's 512Gb to 1Tb products, which limits the read/write performance of NAND flash memories.

Disclosure of Invention

In various exemplary embodiments, NAND flash memory architectures and methods are provided for use with two-dimensional (2D) or three-dimensional (3D) NAND memory arrays. These embodiments may also be applied to Single-Level Cell (SLC), Multi-Level Cell (MLC), Triple-Level Cell (TLC), Quad-Level Cell (QLC), or any number of bits per Cell technologies.

In an embodiment, the NAND architecture includes a bit line select gate that connects the page buffer to a large number of bit lines to increase read/write throughput. In another embodiment, bit line select gates couple page buffers to non-adjacent bit lines to mitigate capacitive coupling. In other embodiments, additional bypass gates and data registers are used to enhance the operation of the NAND memory. In other embodiments, novel programming and read operations are provided that result in improved performance.

In an embodiment, there is provided a method for programming a NAND flash memory, comprising: setting a programming condition on a word line to set programming of a plurality of memory cells associated with a plurality of bit lines; and sequentially enabling the bit line select gates to load data from the page buffer to a plurality of bit lines of the memory. After each bit line is loaded with selected data, the associated bit line select gate is disabled such that the selected data is maintained on the bit line using bit line capacitance. The method further comprises the following steps: waiting for a programming interval to complete after all bit lines are loaded with data to program a plurality of memory cells associated with a plurality of bit lines. At least a portion of the plurality of memory cells are programmed simultaneously.

In an embodiment, a NAND flash memory is provided that includes a memory array having a plurality of bit lines and a plurality of word lines, and a page buffer storing data to be written into or read from the memory array. The page buffer includes a plurality of data lines and is configured to program memory cells in a plurality of cell strings of the memory array simultaneously. The memory also includes a bit line select gate that selectively connects individual data lines of the page buffer to two or more bit lines of the memory array.

In an embodiment, a method for programming a NAND flash memory is provided. The method comprises the following steps: pre-powering up a selected bit line of a selected memory cell with a bias voltage level while unselected bit lines maintain an inhibit voltage; applying a verify voltage to a selected word line coupled to a selected memory cell; and discharging the selected bit line coupled to the turned-on cell for a first time interval. The method further comprises the following steps: sensing a sense voltage level on the selected bit line; loading the selected bit line with an inhibit voltage level when the sense voltage level is above the threshold level and loading the selected bit line with a program voltage when the sense voltage level is equal to or below the threshold level; and repeating the sensing and loading operations for each selected bit line.

In an embodiment, a method for reading a multi-level cell NAND flash memory is provided. The NAND flash memory includes a string of memory cells coupled to a bit line and a word line and a unit data latch coupled to the bit line. The method comprises the following steps: the bits of the cell are read by performing the following operations: applying the selected word line voltage level to the cell to sense the output of the cell; flipping the latch to a first data value when the output indicating cell is a disconnect cell; and repeating the applying and toggling operations until all of the word line voltages have been applied to the cell, such that the value of the bit is stored in the latch. The method further includes repeating the read operation for each bit of the cell to be read.

Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.

Drawings

Exemplary embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.

FIG. 1A illustrates an exemplary block diagram of a NAND flash memory architecture in accordance with embodiments of the invention.

FIG. 1B illustrates another embodiment of a NAND flash memory architecture constructed in accordance with embodiments of the invention.

Fig. 1C illustrates a detailed embodiment of a conventional 3D NAND flash memory cell array and a page buffer.

FIG. 1D shows the configuration of a conventional structure of a 3D NAND memory array.

FIG. 1E shows an embodiment of an array structure according to the present invention.

Fig. 1F shows an embodiment of a 3D array structure according to the present invention.

FIG. 2A illustrates an embodiment of a page buffer and bit line select gate configuration according to an embodiment of the present invention.

Fig. 2B illustrates another embodiment of a page buffer configuration according to an embodiment of the present invention.

FIGS. 2C-2E show embodiments illustrating bit line select gates in accordance with the present invention.

Fig. 3A to 3D show an embodiment of a page buffer circuit.

Fig. 4A to 4D illustrate operations of the page buffer and the bit line select gate according to the present invention.

Fig. 5A-5E illustrate exemplary waveforms for multi-page programming according to the present invention.

Fig. 6A through 6C illustrate a multipage read operation according to an embodiment of the present invention.

Fig. 6D illustrates an exemplary embodiment of a page buffer, a bit line select gate, and a data register according to the present invention.

Fig. 6E illustrates an exemplary embodiment of a page buffer and a bit line select gate according to the present invention.

FIG. 6F illustrates an exemplary embodiment of a single layer chip page buffer and bit line select gates according to the present invention.

Fig. 7A to 7D illustrate embodiments of read operation waveforms according to the present invention.

Fig. 8A-8C illustrate embodiments of program and program-verify operations.

FIGS. 9A-9D illustrate a NAND flash memory array architecture divided into sub-arrays.

Fig. 10A to 10E show embodiments of a 3D array architecture according to the present invention.

FIG. 11A shows an embodiment of a 3D array according to the present invention in which bit lines are used as temporary data storage.

FIG. 11B shows an embodiment of waveforms in accordance with the present invention, illustrating how data is loaded into multiple bit lines.

FIG. 11C illustrates another embodiment of waveforms for loading data into multiple bit lines in accordance with the present invention.

FIG. 11D shows exemplary waveforms illustrating reading data from a bit line capacitor in accordance with the present invention.

Figures 12A-12B illustrate embodiments of 3D arrays providing SLC and TLC programming according to the present invention.

FIG. 13 illustrates an embodiment of a NAND flash memory array illustrating bit line to bit line capacitance.

FIG. 14 shows an array with bit line shields to prevent bit line coupling.

15A-15B illustrate another embodiment of a circuit and corresponding waveforms for mitigating bit line to bit line coupling.

Fig. 16 illustrates an exemplary embodiment of a circuit that solves the last bit line coupling problem as described with reference to fig. 15A-15B.

Fig. 17A shows an embodiment of a circuit including even and odd page buffers as illustrated in fig. 16.

Fig. 17B-17C illustrate embodiments of 2D and 3D versions of an array (or sub-array) for use in the circuit of fig. 17A.

Fig. 18A to 18B show circuits having a divided bit line structure.

FIGS. 19A-19B illustrate another embodiment of a bit line select gate circuit and its corresponding operating waveforms in accordance with the present invention.

20A-20B illustrate embodiments of circuits and associated read waveforms that resolve bit line coupling without sacrificing read data throughput.

21A-21B illustrate embodiments of readout circuits and associated operating waveforms according to the present invention.

Fig. 22A-22B illustrate exemplary embodiments of readout circuits and associated waveforms according to the present invention.

Fig. 23A-23B illustrate exemplary embodiments of readout circuits and associated waveforms according to the present invention.

Fig. 24A-24B illustrate exemplary embodiments of readout circuits and associated waveforms according to the present invention.

Fig. 25A to 25C illustrate an exemplary embodiment of a page buffer and a bit line decoder circuit according to the present invention.

FIG. 26A shows an exemplary embodiment of a circuit according to the present invention that is implemented with only one data latch.

FIG. 26B illustrates a program verify operation for use with the circuit shown in FIG. 26A.

FIG. 26C illustrates an embodiment of a circuit implementation of the data buffer shown in FIG. 26A.

Fig. 27A to 27B illustrate another embodiment using the readout circuit and associated waveforms shown in fig. 20A.

Fig. 27C illustrates another embodiment of a program verify operation using the page buffer circuit illustrated in fig. 3C according to the present invention.

Fig. 28A to 28B illustrate exemplary embodiments of waveforms for a read operation.

Fig. 29A shows a layout arrangement of a page buffer circuit of a conventional 3D NAND flash memory.

Fig. 29B shows a conventional array configuration with two adjacent sub-arrays 601a and 601B.

Fig. 30A shows an embodiment of a layout arrangement of page buffers and circuits for a 3D array according to the present invention.

FIG. 30B illustrates an exemplary embodiment of a tile (tile) formed from two adjacent sub-arrays as shown in FIG. 30A.

Fig. 31A to 31B show an embodiment of a page buffer configuration according to the present invention.

Fig. 32 illustrates an exemplary embodiment of a page buffer and bit line select gate structure according to the present invention.

Fig. 33A shows another embodiment of a page buffer and bit line select gate structure according to the present invention.

Fig. 33B-33C illustrate embodiments configured for MLC programming.

FIG. 34A shows page buffers and bit line connections for a conventional 3D NAND flash memory.

Fig. 34B to 34C illustrate page buffers and bit line connections of a 3D NAND flash memory according to the present invention.

Fig. 35 shows an exemplary Vt distribution of a three-layer cell TLC.

FIG. 36 shows an embodiment of a single latch page buffer circuit according to the present invention.

Fig. 37A to 37C illustrate a method for reading bits using the single latch page buffer shown in fig. 36.

Fig. 37D to 37E show exemplary diagrams associated with the operation of the circuit shown in fig. 36.

38A-38B show embodiments of waveforms illustrating signals for reading bits using the circuit shown in FIG. 36.

Fig. 39 shows another embodiment of the page buffer circuit according to the present invention.

FIG. 40 shows an embodiment of waveforms illustrating signals for reading bits using the circuit shown in FIG. 39.

FIG. 41A illustrates an exemplary alternative embodiment of the page buffer circuit shown in FIG. 36 implemented using complementary logic.

Fig. 41B to 41D show exemplary methods and schematic diagrams associated with the operation of the page buffer circuit shown in fig. 41A.

42A-42F illustrate schematic diagrams providing word line voltages for reading various configurations of multi-level cells using unit latches, in accordance with the present invention.

FIG. 43 illustrates an exemplary method of reading a multi-level cell using a unit latch according to the present invention.

Fig. 44A-44B illustrate an exemplary array structure and data loading and output sequence in accordance with the present invention.

Fig. 45A to 45C show an exemplary array structure and data loading and output sequence according to the present invention.

Fig. 46A to 46C show an exemplary array structure and data loading and output sequence according to the present invention.

Fig. 47A to 47B illustrate an embodiment of a refresh operation according to the present invention.

Detailed Description

In various exemplary embodiments, methods and apparatus are provided for the design and operation of a NAND flash memory architecture that may be used with two-dimensional (2D) or three-dimensional (3D) NAND arrays. These embodiments may also be applied to single-layer cell (SLC), multi-layer cell (MLC), triple-layer cell (TLC), quad-layer cell (QLC), or any number of bit-per-cell technologies.

Those of ordinary skill in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to implementations of the exemplary embodiments of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

FIG. 1A illustrates an exemplary block diagram of a NAND flash memory architecture 100 in accordance with embodiments of the invention. Architecture 100 includes a 2D or 3D NAND flash memory array 101 accessible using a plurality of word lines (WL [0-m ]) and bit lines (BL [0-k ]). Architecture 100 includes a row decoder 102 and a page buffer 103. The page buffer 103 includes a plurality of page buffers, such as the page buffer 200 shown in fig. 2A and 3A. The page buffer 103 performs functions of both a program buffer for a program operation and a sense amplifier for a read operation. In the conventional NAND flash memory, each page buffer is connected to one Bit Line called an All Bit Line (ABL Line) structure or two Bit lines called a Half Bit Line (HBL) structure. In either case, the number of bit lines that can be programmed and read together is equal to the number of page buffers. This is called "page programming" or "page reading". Increasing the number of page buffers may increase data read/write throughput to enhance memory performance. However, the circuit size of the page buffer is quite large. It typically occupies about 20% to 40% of the die size. Therefore, the typical number of page buffers is limited to the range of 16Kb to 64Kb in today's 512Gb to 1Tb products, which limits the read/write performance of NAND flash memories.

In an exemplary embodiment, the architecture 100 includes a bit line select gate block 106. The bit line select gate block 106 includes a plurality of bit line select gates, such as the select gates 210 shown in fig. 2A and 2B. The bit line select gates allow the page buffer to be coupled to multiple bit lines. Multiple bit lines can be programmed and read together using the novel architecture disclosed. This is referred to as "multi-page programming" and "multi-page reading". This can significantly increase data read/write throughput without increasing the number of page buffers.

In an embodiment, data registers 104a-d are provided and may also be referred to as a data cache. Although four data registers are shown, any desired number of data registers may be present. The data register allows parallelism between the operation of the array 101 and data input/output (I/O). During operation, when the array 101 performs a read or write operation using the page buffer 103, new data may be loaded into or output from the data registers 104 a-d. This may enhance the performance of the memory. In an embodiment, architecture 100 includes an input/output (I/O) buffer 106 connected to an external data bus DQ [0-n ].

FIG. 1B illustrates another embodiment of a NAND flash memory architecture 107 constructed in accordance with an embodiment of the invention. In the present embodiment, the array is divided into a plurality of sub-arrays 101a to 101 p. Each sub-array has a respective row decoder 102a to 102p, bit line select gates 106a to 106p, and page buffers 103a to 103 p. In an embodiment, each sub-array has the same number of bit lines as array 101 shown in FIG. 1A, e.g., BLA [0-k ] for sub-array 101A and BLp [0-k ] for sub-array 101 p. In an embodiment, the total number of page buffers is the same as the embodiment shown in fig. 1A to keep the die size the same. Assuming that the number of sub-arrays is P, the number of page buffers 103a to 103P of the respective sub-arrays 101a to 101P will be reduced to 1/P. As a result, the number of bit lines connected to the respective page buffers increases by P times.

Fig. 1C shows a detailed embodiment of the conventional 3D NAND flash memory cell array 101 and the page buffer 103. Memory array 101 includes bit lines BL [0-K ]. Each bit line is connected to one of the page buffers 200a to 200 k.

FIG. 1D shows the configuration of a conventional structure of a 3D NAND memory array. The 3D memory cell array 101 is located on top of the page buffer circuit 103 to save silicon area.

FIG. 1E shows an embodiment of an array structure according to the invention. Bit line BL [0-k ] is connected to page buffer 103 through bit line select gate 106. Therefore, the number of page buffers 103 can be reduced compared to the conventional architecture. For example, two bit lines are connected to respective page buffers, which reduces the number of page buffers used.

Fig. 1F shows an embodiment of a 3D array structure according to the present invention. The 3D cell array is divided into sub-arrays 101a to 101D located on top of the page buffers 103a to 103D. Subarrays 101 a-101 d are accessed through bit line select gates 106 a-106 d. Each sub-array is connected to one page buffer.

FIG. 2A illustrates an embodiment of a page buffer and bit line select gate configuration according to an embodiment of the present invention. The bit lines 201a to 201n are a plurality of bit lines BL [0] to BL [ n ] in an array or sub-array. The bit lines may include multiple strings of NAND flash memory cells, such as strings 211 a-211 n. The strings may be formed using a 2D or 3D array architecture. The bit lines are connected to the page buffer 200 through bit line select gates 210, which include individual select gates 202 a-202 n. The various bit line select gates 202 a-202 n may be selectively enabled or disabled by select gate signals BSG [0] to BSG [ n ], respectively. The number of bit lines connected to one page buffer may be any number, e.g., 2, 4, 8, 16, etc. There is no limitation on the number of bit lines that can be connected to one page buffer.

The page buffer 200 serves as both a program buffer and a sense amplifier. The page buffer 200 includes a plurality of latches 207a to 207n to store program data. Sense amplifier 208 is operative to read data from the cell. In a program mode, latches 207 a-207 n apply program data to the bit lines. In the program verify mode, the sense amplifier 208 reads data from the cell and updates program data stored in the latches 207a to 207 n. In a read mode, sense amplifier 208 reads data from the cell and stores it in latches 207 a-207 b, and may then transfer the data to an output buffer.

In conventional systems during programming, one page buffer may only provide one data value to one bit line at a time. During read and program verify, one page buffer can read data from only one bit line at a time. Therefore, the total bit lines in programming, verifying, and reading is equal to the number of page buffers. For example, in one conventional system, each bit line is connected to one page buffer. This is referred to as an All Bit Line (ABL) architecture. In another conventional design, two bit lines are shared with one page buffer. This architecture is referred to as a Half Bit Line (HBL) architecture. This architecture reduces the number of page buffers by half. However, during read and write modes, only half of the bit lines may be connected to the page buffer, thus reducing data throughput 1/2.

In various exemplary embodiments, a novel architecture is disclosed to simultaneously read and write a plurality of bit lines using one page buffer, so that data throughput may be significantly increased. For example, in fig. 2A, assuming that word line WL [ m ] is selected, cells 204a to 204n can be read and programmed at the same time by one page buffer 200. Accordingly, the number of page buffers can be reduced, and read and write data throughput can be increased. A more detailed description of the design and operation of the novel NAND flash memory architecture is provided below.

It should also be noted that cells 204 a-204 n may belong to different pages. A page may be selected by bit line select gate signals BSG [0] to BSG [ n ]. Thus, the architecture may provide multiple bit line read and write operations, or multiple page read and write operations.

In conventional page buffer designs, the number of latches in the page buffer is determined by the number of bits stored in one cell. For example, for an SLC design, the page buffer may have only one latch to store 1 bit of data. For MLC designs, the page buffer may have two latches to store 2 bits of data. For TLC, the page buffer may have 3 latches to store 3 bits of data. For QLC, the page buffer may have 4 latches to store 4 bits of data. However, according to embodiments of the present invention, additional latches may be added to further enhance the advantages of multi-page read and write operations.

Fig. 2B illustrates another embodiment of a page buffer configuration according to an embodiment of the present invention. As illustrated in FIG. 2B, the array may have multiple layers of bit line select gates, e.g., 202a through 202n and 205a through 205 k. In this case, select gates 202 a-202 n are first level bit line select gates connected to control signals BSGA [0] through BSGA [ n ]. Select gates 205 a-205 k are second level bit line select gates connected to control signals BSGB [0] through BSGB [ k ]. This embodiment reduces the number of control signals compared to the embodiment shown in fig. 2A. For example, assuming 16 bit lines share one page buffer, the embodiment in fig. 2A uses 16 control signals, while the embodiment in fig. 2B uses 8 control signals (e.g., 4 for the first layer and 4 for the second layer). In various embodiments, there is no limit to the number of layers of bit line select gates that can be used. For example, the array may have 2, 3, 4, etc. bit line select gates. In embodiments, the bit line select gates may be implemented using any suitable devices. They are not limited to NMOS devices only.

FIGS. 2C-2E show embodiments illustrating bit line select gates in accordance with the present invention.

Fig. 2C shows a circuit that illustrates how the bit line select gates 202 a-202 n may be implemented with native or depletion mode devices to increase the bit line pre-charge voltage and current.

FIG. 2D shows a circuit that illustrates how the bit line select gates 202 a-202 n may be implemented with PMOS devices.

FIG. 2E shows a circuit that illustrates how the bit line select gates 202 a-202 n may be implemented with PMOS-NMOS pairs. Also, the bit line select gate may be implemented by a High Voltage (HV) device or a Low Voltage (LV) device. Such modifications and variations are within the scope of the embodiments.

Fig. 3A illustrates an embodiment of a page buffer circuit 200. The page buffer 200 circuit is configured as both a program buffer and a sense amplifier (sense amplifier). The program buffer includes three latches 207a to 207 c. Latches 207 a-207 c store data in the Q0, Q1, and Q2 nodes as shown. The data of the latches 207a to 207c can be set to 0(0V) by turning on the set devices 311a to 311c, and reset to 1(VDD) by turning on the reset devices 312a to 312 c. Latch bypass gates 220 a-220 d are also shown. During the programming mode, 3 bits of data D0, D1, and D2 are first loaded into three latches 207a through 207 c. Signals P0 through P3 select and turn on one of the bypass gates 220a through 220d according to the programmed Vt level to bypass the data of latches 207a through 207c to the selected bit line to program the selected cell. Sense amplifiers 208 are also shown.

During a read mode, data may be read from the cell by sense amplifier 208 and then latched in three latches 207 a-207 c. The sense node 302 of the sense amplifier is denoted by (SA). Sense node 302 is connected to the gate of sense device 310. The sense amplifier 208 includes a pre-power-up device 303 and a discharge device 304. During bit line pre-power up, pre-power up device 303 is turned on to pre-power up SA node 302 and the bit line to VDD. During the read mode, VDD is applied to the signal PREB to turn off the pre-power-on device 303, or a reference voltage Vref is applied to the signal to limit the pull-up current of the pre-power-on device 303. The pull-up current is designed to be lower than the turn-on cell current, so the turn-on cell can discharge the bit line to pull the SA node 302 low.

After the turn-on cells discharge the bit line voltage below the Vt of the sense device 310, depending on which of the D0-D2 bits is read, the selected signals to S0-S2 are pulsed to turn on the set devices 311 a-311 c to set the latches 207 a-207 c. Latches 207 a-207 c were previously reset to data 1 (VDD). For the on cell, the bitline and SA node 302 discharge below the Vt of sense device 310, which turns off sense device 310 so the data of the latch remains at 1 (VDD). For an off cell, because SA node 302 remains at VDD, this turns on sense device 310 and allows the latch to be set to data 0 (VDD).

More detailed operation the operation of the sense amplifier 208 will be described below with reference to fig. 6A to 6C.

It should be noted that the exemplary circuit shown in fig. 3A does not have a biasing device. However, fig. 3B illustrates an alternative circuit that includes a biasing device 306. Bias device 306 serves as a cascade stage to control the pre-charge voltage of the bit line. In the embodiment shown in FIG. 3A, the function of the biasing devices is performed by the bit line select gates, which is illustrated by the read operation waveforms shown in FIG. 7D and FIGS. 20A-20B.

In another embodiment, the page buffer circuit shown in FIG. 3A may be modified as shown in FIG. 3D to include a biasing device 306. In the embodiment shown in FIG. 3D, the BIAS signal biases biasing device 306 to control the bit line pre-charge voltage. Accordingly, the VDD level can be supplied to the signal of the bit line selection gate.

Fig. 3B shows another embodiment of the page buffer circuit 200. The page buffer 200 shown in fig. 3B is used for current sensing, while the embodiment shown in fig. 3A is used for voltage sensing. In this embodiment, a gain stage, such as a comparator 305, is added to the sense amplifier 208 to amplify the voltage of the sense node 302. In another embodiment, comparator 305 is replaced by an inverter. Also, a biasing device 306 may be added to become a cascaded stage. Biasing device 306 limits the pre-power-up voltage of the bit line to (BIAS-Vt) instead of VDD, thus reducing the pre-power-up time.

Fig. 3C illustrates another embodiment of a page buffer circuit 200 that uses a single data latch for SLC applications. The page buffer 200 circuit is configured as both a program buffer and a sense amplifier. The program buffer includes a data latch 207. A latch bypass gate 220 is also shown. During the programming mode, signal PGM turns on the bypass gate 220 to bypass the data of latch 207 to the selected bit line to program the selected cell. Sense amplifiers 208 are also shown. During a read mode, data may be read from the cell by sense amplifier 208 and then latched in data latch 207. The sense node 302 of the sense amplifier is denoted by (SA). Sense amplifier 208 includes a pre-power-up device 303. During read and program verify modes, signal PREB turns on pre-power-up device 303 to charge the SA node to VDD and also charges the selected bit line through bias device 306. The signal BIAS is applied to the BIAS device 306 to control the pre-charge voltage of the selected bit line. The bit lines will be pre-powered up to BIAS-Vt, where Vt is the threshold voltage of the BIAS device 306. After the bit lines are pre-powered up, the selected cells are read by applying a read voltage to the selected word line. If the selected cell is a turned-on cell, it will discharge the bit line voltage. When the bit line voltage discharges below BIAS-Vt, the biasing device 306 will be turned on and pull the SA node down to the same voltage as the bit line. When the bit line voltage discharges below the Vt of sense device 310, sense device 310 turns off. If the cell is an off cell, the bit line will remain at the pre-power-up voltage and the SA node will remain at VDD. The SA node voltage will turn on sensing device 310. The set device 311 and reset device 312 are used to set and reset the Q and QB nodes of the latch 207. When device 310 is turned on, signal SET or RES may be pulsed with a VDD level to turn on devices 311 or 312 to SET the Q node of latch 207 to DATA 0(0V) or DATA 1(VDD), respectively.

Fig. 4A to 4D illustrate operations of the page buffer and the bit line select gate according to the present invention.

Fig. 4A shows an exemplary embodiment using a TLC page buffer 200. The TLC page buffer 200 includes three data latches 207a to 207c and a sense amplifier 208. For embodiments using MLC and QLC, the page buffer may include two and four data latches, respectively. The page buffer 200 is connected to a plurality of bit lines 201a to 201c through bit line select gates 202a to 202 c. The bit line capacitances 206a to 206c represent bit line capacitances of the bit lines 201a to 201c, respectively.

Fig. 4B illustrates the basic TLC programming operation. The TLC programming operation programs three bits of data into one selected cell. TLC programming may include multiple programming steps to program the cell from an erased Vt to eight Vt levels to represent three bits of data. Assume that cell 204a is selected. In various programming steps, one of the data latches 207 a-207 c may be selected depending on which Vt level is programmed to load data to the selected bit line 201a to program the cell 204 a. For example, when programming bit D0, the data stored in latch 0207 a is loaded to selected bit line 201a to program selected cell 204 a. When programming bit D1, the data stored in latch 1207 b may be loaded onto selected bit line 201a to program selected cell 204 a. When programming bit D2, the data stored in latch 2207 c may be loaded onto selected bit line 201a to program selected cell 204 a. In this operation, the number of cells to be programmed is equal to the number of page buffers. Therefore, it is referred to as "single page programming".

FIG. 4C illustrates a multiple page programming operation according to the present invention. In an embodiment, the data stored in the latches 207 a-207 c is programmed to multiple cells 204 a-204 c on multiple bit lines 201 a-201 c simultaneously. If the page buffer has N data latches, it can program N cells simultaneously. This significantly increases the programming data throughput by a factor of N.

To load multiple pages of data, the bit line select gates 202 a-202 c may be sequentially turned on to load data from the latches 207 a-207 c to the bit lines 201 a-201 c, respectively, as indicated by the arrowed lines. After loading data to the bit lines 201 a-201 c, the bit line select gates 202 a-202 c are turned off, and then the data is held by the bit line capacitances 206 a-206 c. Thereafter, a programming condition is applied to the selected word line WL [ m ] to program the selected cells 204 a-204 c according to the data stored in the bit line capacitances 206 a-206 c. By using these operations, data of a plurality of bit lines can be programmed at the same time.

In an exemplary embodiment, the page buffer performs two program function modes. One is TLC programming and the other is SLC programming. When the page buffer performs TLC programming, the data latches 207a to 207c are used to store three-bit data D0, D1, and D2 of one cell and program the three data bits into a single cell. In SLC programming, three data latches may be used to store three unit cells of data, which are then programmed into three cells. This is called "multipage programming".

By using the multi-page SLC programming described above, data throughput can be significantly increased. Thus, this mode can be used to program data into the cell at high speed. Later in idle time, data may be read out of the SLC cells and reprogrammed to other cells using TLC mode, and then the SLC cells may be erased to increase the storage capacity of the memory.

The disclosed multi-page programming operation is applicable not only to SLC, but also to multi-level cells such as MLC, TLC, and QLC, among others. For example, referring to FIG. 4C, assume that three pages of data are programmed into selected cells 204 a-204C using a TLC mode. Each cell can store one of eight Vt levels, representing three bits of data D0, D1, and D2. In a first step, data of a first page is loaded into the data latches 207a to 207 c. Then, data is sequentially loaded to the bit lines 201a to 201c using the previously described operation, and then a program condition is applied to the cells 204a to 204c to program the respective cells according to the bit line data. The cell will be programmed to the Vt level corresponding to the D0 bit. A program verify operation may be performed to check the Vt of the cell. The program verifying operation will be described later with reference to fig. 6A to 6C. After the data is successfully programmed, the data in latches 207a through 207c may be cleared.

In a second step, the data for the second page is loaded into three latches 207 a-207 c and then sequentially into the bit lines 201 a-201 c to program the cells 204 a-204 c to the Vt level corresponding to the D1 bit. After the data of the second page is successfully programmed, the data in the latches 207a to 207c may be cleared. In a third step, the data for the third page is loaded into latches 207 a-207 c, which are then applied to bit lines 201 a-201 c to program cells 204 a-204 c to the Vt level corresponding to the D2 bits. By repeating the sequence, the cell can be programmed to any number of multi-level cells, such as MLC, TLC, QLC, etc.

FIG. 4D shows another exemplary programming embodiment in accordance with the present invention. Assume that the chip has multiple data registers 212 a-212 c. Each data register includes a multi-bit latch, e.g., Reg 0 through Reg 2. During the SLC programming mode, data from the first data register 212a is loaded into latches 207 a-207 c and then onto bit lines 201 a-201 c, respectively, to program cells 204 a-204 c. After the data is successfully programmed, the data of the next register 212b may be loaded to latches 207 a-207 c and then to bit lines 201 a-201 c, respectively, to program another page, such as cells 214 a-214 b. In this way, multiple pages of data can be programmed simultaneously to increase program data throughput.

For the TLC programming mode, the data stored in first data register 212a may be transferred to latches 207 a-207 c and then programmed to the Vt level of the D0 bits corresponding to the selected cells 204 a-204 c. The data stored in second data register 212b may then be transferred to latches 207 a-207 c and then programmed to the Vt level corresponding to the D1 bit of the selected cell 204 a-204 c. This operation may be repeated to program the data of the third data register 212c to bit D2 of the selected cell 204 a-204 c.

In embodiments, the data in the data registers 212 a-212 c may be programmed to the cells in any suitable order. For example, in another embodiment, in a first step, the data stored in Reg 0 of data registers 212 a-212 c may be sequentially transferred to data latch 207a, then loaded onto bit lines 201 a-201 c, then programmed to the Vt level of the D0 bit for cells 204 a-204 c. In a second step, the data stored in Reg 1 of the data registers 212 a-212 c may be sequentially transferred to the data latch 207b, then loaded to the bit lines 201 a-201 c, then programmed to the Vt level for the D1 bit in cells 204 a-204 c. In a third step, the data stored in Reg 2 of data registers 212 a-212 c can be sequentially transferred to data latch 207c, then loaded to bit lines 201 a-201 c, and then programmed to the Vt level for the D2 bits in cells 204 a-204 c.

FIG. 5A shows exemplary waveforms for multi-page programming of the circuit shown in FIG. 4C. Referring now to both FIG. 4C and FIG. 5A, at time T1, BSG [0] to BSG [2] may go high to turn on the bit line select gates 202a to 202C. It is assumed that output data of the page buffer is referred to as PB. A Page Buffer (PB) may apply VDD to all bit lines BL [0] to BL [2 ]. The Drain Select Gate (DSG) of the selected cell string is supplied with VDD. The Source Select Gate (SSG) is supplied with 0V. Thus, the channel regions of strings STRG [0] to STRG [2] may be charged to the VDD-Vt of the drain select gate.

At time T2, a program voltage of, for example, 20V and an inhibit voltage of, for example, 10V are supplied to the selected word line WL [ m ] and other unselected word lines, respectively. The voltage of the word line may couple the channel regions of all strings STRG [0] to STRG [2] to a voltage of approximately 8V. This voltage may inhibit programming of the cell. Since the bit line is supplied with VDD, the drain select gate is reverse biased. Thus, the drain select gate will be turned off to prevent the channel voltage from leaking to the bit line.

At time T3, the bit line select gates BSG [0] to BSG [2] are turned off. Bit line capacitances such as 206a through 206C shown in FIG. 4C hold the bit line voltage at VDD.

At time T4, the first bit line select gate BSG [0] is turned on, and the Page Buffer (PB) applies the first data to the first bit line BL [0 ]. If the data is "1" (VDD), the channel of string STRG [0] will remain at the inhibit voltage, e.g., 8V. If the data is "0" (0V), the drain select gate will be turned on and the string STRG [0] will be discharged to 0V. This will result in the first selected cell 204a being programmed. After the first bit line select gate BSG [0] is turned off at time T5, the bit line BL [0] and string STRG [0] may remain at 0V due to bit line capacitance 206 a.

These steps may be repeated to sequentially turn on the bit line select gates BSG [1] to BSG [2] to load data from the Page Buffer (PB) to the bit lines BL [1] and BL [2] and their strings STRG [1] and STRG [2 ].

After all the data is loaded, at time T6, the timer may begin counting program pulses Tpgm over a time interval from 10us to 30 us. The programming pulse is then ended. By using the above process, multiple bit lines can be loaded with different data and programmed simultaneously.

It should be noted that the waveforms of fig. 5A are for illustration and are not drawn to scale. In practice, the total programming time is governed by Tpgm. The data loading time is negligible. Thus, multi-page programming can significantly reduce overall programming time and increase program data throughput.

FIG. 5B shows another embodiment of waveforms for multiple page programming in accordance with the present invention. These waveforms are similar to those shown in FIG. 5A, except that the bit line select gates BSG [0] to BSG [2] may be turned off after the bit line is pre-powered to VDD at time T1 (illustrated as 506). Therefore, the voltage of the bit line is held by the bit line capacitance.

FIG. 5C shows another embodiment of waveforms for multi-page programming in accordance with the present invention. These waveforms are similar to FIG. 5A, except that the Drain Select Gate (DSG) of the selected string may be turned off after data is loaded to multiple bit lines at time T6 (as illustrated by 508). Thus, if the floating bitline has leakage, the bitline voltage needs to drop from VDD to a Vt lower than the drain select gate to turn on the drain select gate. Thus, this approach provides a higher margin for failure for the string's inhibit voltage.

FIG. 5D illustrates another embodiment of waveforms for multi-page programming, where the operations shown in FIG. 5C are applied to the waveforms shown in FIG. 5B to produce the waveforms shown in FIG. 5D. In an embodiment, after pre-powering up (as illustrated by 510) the string at time T1, the Drain Select Gate (DSG) of the selected string is turned off. The DSG may be turned on at time T3 (as illustrated by 512) to load multiple pages of data into the string and then turned off at time T6 (as illustrated by 514) to increase the leakage margin of the floating bit line.

FIG. 5E illustrates another embodiment of waveforms for multi-page programming in accordance with the present invention. At time T1, the selected Drain Select Gate (DSG) is turned on and the Source Select Gate (SSG) is turned off. From time T1 to time T2, the Page Buffer (PB) supplies page data: data 0, data 1, and data 2. The bit line select gates BSG [0] to BSG [2] are sequentially turned on to load data to BL [0] to BL [2] and STRG [0] to STRG [2 ]. At time T3, a program voltage of 20V and an inhibit voltage of 10V are supplied to the selected word line and the unselected word lines, respectively. The voltage of the word line couples the channel regions of STRG [0] to STRG [2] having a data value of "1" to a voltage of about 8V to inhibit programming of the cell. For a string storing a data value of "0" (0V), the drain select gate is turned on, so it will cause charge sharing between the capacitance of the string and the bit line capacitance. Since the bit line capacitance is much higher than the string capacitance, the string voltage is very close to 0V as a result. This will result in the selected cell being programmed.

In an embodiment, the circuit shown in FIG. 2A allows for program verification and reading of multiple page cells simultaneously by using page buffers 200.

Fig. 6A to 6C illustrate a multiple page read operation according to an embodiment of the present invention. In an embodiment, a multiple page read operation includes three steps. The three steps are pre-charging the bit line, discharging the bit line and sensing.

FIG. 6A shows an exemplary circuit that performs the pre-charge bit line step. During operation, all of the bit line select gates 202 a-202 c are turned on, and a pre-charge device, such as device 303 in sense amplifier 208 shown in FIG. 3A, is turned on to pre-charge the bit line capacitances 206 a-206 c to a pre-charge voltage, such as VDD or Vbias-Vt, as shown by the dashed lines.

FIG. 6B shows an exemplary circuit that performs the step of discharging the bit lines. During operation, the bit line select gates 201 a-202 c are turned off. Read bias conditions are applied to the selected cells 204 a-204 c. The read voltage is supplied to the selected word line, e.g., WL [ m ], to turn cells 204 a-204 c on or off according to the Vt of the cell. Turning on the cells will simultaneously discharge the bit lines. Assume that cells 204a and 204b are on and off cells, respectively. Turning on cell 204a discharges bit line capacitance 206a to 0V. The disconnect cell 204b will not discharge the bit line and thus the bit line capacitance 206b will remain at the pre-power-up voltage. This bit line discharge step may take about 25us to 35us because the on-cell current is very low (e.g., only about 1uA), and the bit line capacitance is high because it is connected to many strings. Thus, the read time is dominated by the bit line discharge time. Thus, by using multiple bit line discharges according to the present invention, the total read time is reduced and read data throughput is significantly increased.

Fig. 6C shows an exemplary circuit that performs the readout step. In this step, the bit line select gates 202a to 202c are sequentially turned on to allow the data stored by the bit line capacitances 206a to 206c to be read by the sense amplifiers 208 of the page buffer, as indicated by the dotted lines. When the bit line select gate is turned on, it will cause charge sharing between the bit line capacitance and the sense node 302 of the page buffer circuit, as shown in fig. 3A. Because the capacitance of the sense node 302 is much lower than the bit line capacitance, the sense node 302 will be pulled up or down in a very short time. Therefore, data of the respective bit lines can be read in a very short time.

After the data is stored in the data latches 207a to 207c, the data may be transferred to the data register, and then the data register may start outputting the data. At the same time, the page buffer may start reading data of the next page from the cell. If the chip has no data register, the data can be directly output from the data latches of the page buffer, and then the page buffer can start reading the data of the next page from the cell.

In an embodiment, the operations shown in FIGS. 6A-6C may also be used for multi-page program verification. The program verify operation is very similar to the read operation. The only difference is the word line voltage and the operation of the data latch. In the read mode, data read from the cell is stored directly in the data latch. In the program verify mode, the data read from the cells is used to update the data in the data latches.

Referring to FIG. 6B, for a program verify condition, a program verify voltage, instead of a read voltage, may be supplied to a selected word line in order to check the Vt of the cell. In FIG. 6C, after the sense amplifier 208 reads the cell's data, the data will be used to update the data stored in latches 207 a-207C for the next programming pulse. The logical operation of the refresh latch is well known and therefore not described herein.

Fig. 6D illustrates an exemplary embodiment of a page buffer, a bit line select gate, and a data register according to the present invention. In embodiments, the page buffer 200 and the bit line select gates 202 increase program and read data throughput in accordance with the present invention. In this embodiment, the chip includes a plurality of data registers 212 a-212 n. Also shown are NAND flash cell strings 211a through 211f, a page buffer 200 including a sense amplifier 208 and a plurality of data latches 207a through 207c, and bit line select gates 202a through 202 f. During operation, data of the first data register 212a is transferred to the data latches 207 a-207 c and then loaded onto the bit lines 201 a-201 c through the bit line select gates 202 a-202 c to program the first set of strings 215a, and data of the second data register 212n is transferred to the data latches 207 a-207 c and then loaded onto the bit lines 201 d-201 f through the bit line select gates 202 d-202 f to program the second set of strings 215 b.

During a read operation, data of the first group of strings 215a is read and stored in the capacitances of the bit lines 201 a-201 c. The data is read by sense amplifier 208 through bit line select gates 202 a-202 c and latched in data latches 207 a-207 c. Then, the data of the data latches 207a to 207c is transferred to the first data register 212 a. Similarly, the data of the second set of strings 215b is read and transferred to the second data register 212 n. The data may then be output from the data registers 212a through 212n to the I/O circuitry.

Fig. 6E illustrates an exemplary embodiment of a page buffer and a bit line select gate according to the present invention. In accordance with the present invention, the page buffer 200 and the bit line select gates 202 operate to increase program and read data throughput. This embodiment is similar to the embodiment shown in FIG. 6D, except that the data registers 212a through 212n are excluded. The page buffer 200 includes a plurality of data latches 207a to 207 c. The data latches 207a to 207c are directly connected to an I/O (input/output) bus 600. During a program operation, data is sequentially loaded from the I/O bus 600 to the data latches 207 a-207 c, then to the bit lines 201 a-201O and the strings 215 a-215 m. During a read operation, data for the strings 215a through 215m is read from the bit lines 201a through 201O and sequentially loaded into the data latches 207a through 207c, and then output to the I/O bus 600.

FIG. 6F shows an exemplary embodiment of a single-level cell (SLC) page buffer and bit line select gates according to the present invention. In accordance with the present invention, the page buffer 200 and the bit line select gates 202 operate to increase program and read data throughput. This embodiment is similar to the embodiment shown in fig. 6A, except that the page buffer 200 has a single data latch 207 for SLC applications. The page buffer 200 is connected to a plurality of bit lines 201a to 201n through bit line select gates 202a to 202 n. During a program operation, the bit line select gates 202a to 202n may be sequentially turned on by signals BSG [0] to BSG [ n ] to load program data from the page buffer 200 to the bit lines 201a to 201n, respectively. Data is stored in the bit line capacitances 206a through 206n and programmed to the selected cells 204a through 204n, respectively. This embodiment significantly increases the programming throughput because multiple cells 204 a-204 n can be programmed simultaneously by using one programming pulse.

During a read operation, data from the cells 204 a-204 n may be read and stored in the bit line capacitances 206 a-206 n. The bit line select gates 202a to 202n may be sequentially turned on to sense data of the bit line capacitances 206a to 206n by the sense amplifiers 208 of the page buffer, respectively. Since the plurality of cells 204a to 204n can be read simultaneously by using one bit line discharge period, the present embodiment significantly increases the read throughput.

FIG. 7A illustrates an embodiment of read operation waveforms according to the embodiment of the invention illustrated in FIGS. 6A-6C. A detailed circuit of the page buffer 200 is shown in fig. 3A. At time T1, the selected word line is supplied with a read voltage Vread to read the selected cell, and the unselected word lines are supplied with a bypass voltage Vpass, which is higher than Vt of unselected cells in the NAND cell string that turn on the unselected cells. Turning on the Drain Select Gate (DSG) and the Source Select Gate (SSG). The Source Line (SL) is supplied with 0V. These conditions turn the on unit on and turn the off unit off.

At time T2, the bit line select gates BSG [0] to BSG [2] are turned on, and as shown in the page buffer circuit in fig. 3A, a pre-power-up signal PREB is activated to pre-power up BL [0] to BL [2] to VDD-Vt (of the bit line select gates) or a predetermined voltage.

At time T3, the bit line select gates BSG [0] to BSG [2] are turned off. The bit lines BL [0] to BL [2] will become floating and the selected cell will begin to discharge the bit line. For a turned-on cell, the cell will conduct current to discharge the cell string and bit line to 0V. For an open cell, the bit line will remain at the pre-charge voltage because the cell is open.

Because the on-cell current is very low, perhaps only 1uA to 5uA, and the bit line capacitance is large, it can take a long time to discharge the bit line. The time to discharge the bit line is in the range of about 25us to 35 us. As a result, the bit line discharge time, shown as Tdis, may dominate the overall read time. However, according to the present invention, all BL [0] to BL [2] are discharged simultaneously, thus significantly reducing the total read time.

After a predetermined discharge time Tdis, the first bit line selection gate BSG [0] may be turned on at time T4. This allows charge sharing to occur between the sense node (SA) and BL [0 ]. Because BL [0] has a much higher capacitance than the sense node (SA) of the sense amplifier, the sense node (SA) can charge to almost VDD or discharge to almost 0V in a very short time. Then, the first set signal S0 is activated to latch data to the first data latch of the page buffer. After latching the data, BSG [0] may be turned off to isolate BL [0] from the sense node (SA).

Referring to the page buffer circuit shown in fig. 3A, at the start of a read operation, the latches 207a to 207c are reset to data 1. At time T4, the set signal S0 turns on the set device 311 a. If the sense node (SA) voltage is near VDD, it will turn on sense device 310 and allow signal S0 to set latch 207a to DATA 0 (off cell). If the sense node (SA) voltage is close to 0V, it will turn off sensing device 310, so set signal S0 will not set latch 207a, and latch 207a remains at DATA 1 (the on cell).

At time T5, a pre-power-up signal PREB is activated to pre-power up the sense node (SA) to VDD. Then, the second bit line select gate BSG [1] is turned on to read data of the second bit line BL [1 ]. The steps from T4 to T5 are repeated to read data from BL [1] and BL [2] and latch the data in data latches 207b and 207c using set signals S1 and S2, respectively.

If the chip has no data register, the data can be directly output from the page buffer after being latched to the page buffer. If the chip has a data register as shown at 212a to 212c in fig. 4D, data can be transferred from the page buffer to the data register. Thus, the data register may output data to the I/O buffer while the page buffer reads data of the next bit line.

In this embodiment, a plurality of bit lines can be read by using only one page buffer circuit. Since bit lines BL [0] to BL [2] are discharged simultaneously, the total read time and read data throughput are increased by a factor of three.

The waveforms shown in FIG. 7A are for reading one Vt level. For multi-level cells such as MLC, TLC, and QLC, the waveform may be repeated multiple times with different selected word line voltages to read multiple bits of the selected cell.

The waveform shown in fig. 7A illustrates the basic concept of the embodiment. The waveform may be modified in accordance with a number of design considerations or requirements. For example, in another embodiment, the word line voltage may be applied after T3 instead of at T1. Such modifications and variations are to be kept within the scope of the embodiments.

In another embodiment, referring again to FIG. 7A, at time T2, signals BSG [0] to BSG [2] are provided with bias voltage Vbias to limit the pre-charge voltage of the bit line. The bit lines BL [0:2] will be pre-powered up to Vbias-Vt for the bit line select gates. This reduces the bit line discharge time Tdis because the bit line is pre-powered to a lower voltage. In an exemplary embodiment, Vbias may be slightly higher than the Vt of sense device 310 shown in FIG. 3A. This reduces the time for the on cell to discharge the bit line voltage below the Vt of sensing device 310. For an off cell, since the bitline pre-charge voltage is higher than the Vt of sensing device 310, the sensing device will turn on to allow signal S0 to set latch 207 a.

In another exemplary embodiment using the page buffer circuit shown in fig. 3D, the pre-charge voltage of the bit line may be limited by the bias device 306. During pre-power-up, signal BIAS is provided with a BIAS voltage Vbias to pre-power up bit lines BL [0] to BL [2] to Vbias-Vt of BIAS device 306. Signals BSG [0] through BSG [0] are provided at a VDD level. This reduces the bit line discharge time Tdis. In an exemplary embodiment, Vbias may be slightly higher than Vt1+ Vt2, where Vt1 and Vt2 are the threshold voltages of biasing device 306 and sensing device 310, respectively. In this way, the bit lines are pre-powered up to a slightly higher Vt than the sense device 310, thus reducing the bit line discharge time.

FIG. 7B illustrates another embodiment of read operation waveforms in accordance with the present invention. This embodiment is similar to the embodiment shown in FIG. 7A, except that at time T1, the Source Line (SL) is supplied with a positive voltage, such as VDD.

At time T2, a Discharge Signal (DIS) shown as a page buffer circuit in fig. 3A is activated to Discharge the sense node (SA) and the bit lines BL [0] to BL [2] to 0V.

At time T3, the bit line select gates BSG [0] to BSG [2] are turned off so the bit lines BL [0] to BL [ n ] become floating. Turning on the cell may begin charging the bit line. The bit lines may be charged to Vread-Vt (of the turned-on cell).

At time T4, a pre-power-up signal PREB is activated to pre-power up the sense node (SA) to VDD. Then, the bit line select gate BSG [0] is turned on. The voltage of BSG [0] may not be higher than the bit line voltage + Vt (of the bit line select gate). Thus, for a turned-on cell, the bit line select gate will be turned off. The sense node (SA) will remain at VDD. For an off cell, the bit line select gate will be turned on because BL is held at 0V. The sense node (SA) will discharge to almost 0V due to charge sharing between the bit line and the sense node. Then, the latch signal LAT is activated to latch the data of the sense node in the page buffer. The steps from time T4 to T5 may then be repeated to read the data from the next bit line.

FIG. 7C illustrates another embodiment of read operation waveforms in accordance with the present invention. This embodiment uses a current sensing operation. For example, the page buffer circuit shown in fig. 3B may be used to perform current sensing. The operation shown in FIG. 7C is similar to the operation shown in FIG. 7A, except that at time T1, a pre-power-up signal PREB is activated to pre-power up the sense node (SA) and the bit lines BL [0] to BL [2 ]. The bias device 306 shown in FIG. 3B is biased to limit the bit line pre-charge voltage to Vbias-Vt (of the bias device). The bit line discharge time between times T3 and T4 is much shorter because the current sensing does not require the bit line voltage to discharge to near 0V. The bias devices can be turned on by simply discharging the bit line voltage below Vbias-Vt. At time T4, the reference voltage Vref is supplied to the pre-power-up signal PREB to limit the pull-up current of the pre-power-up device 303 shown in fig. 3B. The pull-up current is lower than the current to turn on the cell. Thus, for a turned-on cell, the sense node (SA) may be discharged to the same bit line voltage as the voltage of the turned-on cell. For a disconnected cell, the sense node (SA) is held at VDD. As a result, the gain stage of comparator 305 amplifies the SA voltage to full VDD and 0V. Then, the operation as described in fig. 7A is performed.

FIG. 7D illustrates another embodiment of read operation waveforms according to the present invention using current sensing. This embodiment is similar to the embodiment shown in fig. 7C, except that the biasing device 306 shown in fig. 3B is removed. Thus, the function of biasing the devices is performed by the bit line select gates 202 a-202 n. During pre-power-up and sensing, the bit line select gates BSG [0] to BSG [ n ] are supplied with a bias voltage Vbias, as shown in FIG. 7D.

FIG. 8A shows an embodiment of program and program verify pulses. As shown in FIG. 8A, a Word Line (WL) is subjected to a program pulse 801 and a program verify pulse 802. During these times, the word lines are supplied with programming voltages and verify voltages, respectively. For program pulse 801, multiple pages of data are loaded sequentially (as shown by 803) and then programmed simultaneously (as shown by 804). For verify pulse 802, the bit lines of multiple pages are discharged simultaneously (as shown at 805), and then the data for the bit lines is read out sequentially (as shown at 806).

FIG. 8B illustrates an embodiment of a read operation. As shown in fig. 8B, the bit lines of the pages are discharged simultaneously (as shown at 807), and then the data of the bit lines are sequentially read out (as shown at 808).

FIG. 8C illustrates an embodiment of an MLC read or program verify operation. As shown in fig. 8C, the word lines are supplied with multi-level voltages 809a to 809C. For each level, multiple bit lines are discharged simultaneously, as shown at 801a through 801c, and read out sequentially, as shown at 811a through 811 c.

FIG. 9A illustrates a conventional NAND flash memory array architecture. As shown in FIG. 9A, array 901 is accessed using M word lines and N bit lines. A page buffer 902 is provided which contains the same number of buffers as the number of bit lines.

FIG. 9B illustrates an embodiment of an array architecture according to the present invention. As shown in fig. 9B, the array is divided into two sub-arrays 901a and 901B. Each sub-array is accessed using M/2 word lines and N bit lines. Each subarray is connected to one of page buffers 902a and 902b by 2-to-1 bit line select gates 903a and 903 b. Therefore, the number of page buffers 902a and 902b may be each N/2. As a result, the number of total page buffers is N, which is the same as in the array shown in fig. 9A. Thus, the silicon area of the array architecture shown in fig. 9A-9B is similar. However, as described above, the array architecture in FIG. 9B may double the read data throughput as compared to the array shown in FIG. 9A. In addition, the bit line length of the array architecture shown in FIG. 9B is 1/2 times the BL length of the array shown in FIG. 9A, so its BL capacitance is also half. Therefore, the BL discharge time can be reduced to 1/2. Since the BL discharge time is in dominant alignment in the total read time, the total read time can be reduced by about 1/2. Note that this reduction in read time can benefit both random read and sequential read operations. Also, sub-arrays 901a and 901b can be read and programmed independently. This results in 2-plane operation.

Fig. 9C shows another embodiment of an array architecture using 4 sub-arrays 901a to 901 d. Each sub-array uses N/4 page buffers, e.g., 902a through 902 d. The bit lines are connected to the page buffer through 4-1 BL select gates (e.g., 903 a-903 d). As a result, the total page buffer number is the same as the array shown in fig. 9A. Thus, the silicon area of the array architecture is similar to the array shown in FIG. 9A. However, according to the present invention, the array has a read data throughput of 4 times as compared to the array of FIG. 9A. In addition, for this array architecture, the bit line length became 1/4, and its bit line capacitance and bit line discharge time also became 1/4. As a result, the read latency also becomes 1/4. Also, the 4 sub-arrays 901a to 901d can be independently read and programmed, which results in 4-plane operation.

In various exemplary embodiments, the array is divided into any number of sub-arrays. More sub-arrays, shorter read latency and higher data throughput can be achieved.

Fig. 9D assumes that the array is divided into K sub-arrays. The read latency becomes 1/K and the data throughput becomes K times the array as shown in fig. 9A. For example, a typical SLC NAND flash memory read latency is about 25us and data throughput is about 640 MB/s. Assuming that the array is divided into 32 sub-arrays, the read latency can be reduced to 25 us/32-0.8 us and the data throughput can be increased to 640Mb/s x 32-20.5 GB/s while the die size remains approximately the same. This high data throughput may saturate the I/O speed when a low I/O pin count, such as 8 or 16, is used. Therefore, it may be most advantageous to use with products having a High I/O pin count, such as Hybrid Memory Cubes (HMC) and High Bandwidth Memory (HBM), among others.

Fig. 10A-10E illustrate embodiments of 3D array architectures.

Fig. 10A shows an array architecture with a 3D array 1001 that includes multiple WL layers and bit lines extending in the Y direction. A page buffer circuit 1002 is located below the array 1001. This configuration may reduce die size and also allow more page buffers to be integrated. The page buffer may be connected to the bit line through bit line contact 1003.

Fig. 10B illustrates an embodiment of a 3D array architecture comprising 4 sub-arrays 1001a to 1001D. The page buffers may be divided into 4 groups 1002a to 1002 d. As shown, each page buffer group may be connected to a corresponding sub-array through bit line contacts 1003a to 1003 d. The die size of this architecture remains about the same as the array shown in fig. 10A, however, read latency can be reduced 1/4 and read data throughput can be increased by a factor of 4.

FIG. 10C illustrates another embodiment of a 3D array architecture according to the present invention. The array in fig. 10C is divided into K sub-arrays 1001a to 1001K. The page buffers are also divided into K groups 1002a to 1002K. By using this architecture, the die size can remain approximately the same as the array in FIG. 10A, however, the read latency can be reduced by 1/K and read data throughput can be increased by a factor of K.

Fig. 10D shows an embodiment of the 3D sub-array 1001a and its page buffer circuit 1002a as shown in fig. 10C. Sub-array 1001a includes a plurality of bit lines 1004 a-1004 n, and each bit line is coupled to a string, such as bit line 1004n coupled to strings 1005 a-1005 m. Also shown is a page buffer circuit 1002a that includes a bit line decoder. Page buffer and bitline decoder 1002a is located below 3D subarray 1001a to save silicon area. Bit lines 1004a through 1004n are connected to page buffer and bit line decoder 1002a through contacts 1003a through 1003 a'.

In a conventional array, the number of page buffers must be equal to the number of bit lines performing All Bit Line (ABL) programming and reading, and equal to half the number of bit lines performing Half Bit Line (HBL) programming and reading. In various exemplary embodiments, the number of page buffers may be 1/K of the bit lines, where K is the number of bit line select gate signals, such as BSG [0: k-1]. However, all bit lines can still be programmed and read simultaneously. By using this method, the array can be divided into K sub-arrays as shown in fig. 10D. The sub-arrays may be arranged as shown in fig. 10C. This results in the same die size as a conventional array, while data throughput can be increased by a factor of K, and the bit line length of each sub-array can be reduced by 1/K, which reduces the bit line discharge time by 1/K. As a result, a total of K can be achieved ² The read data throughput of (K × K) is improved.

Fig. 10E shows another embodiment of 3D sub-array 1001a and its page buffer circuit 1002 a. As shown in fig. 10E, a page buffer and bit line decoder 1002a is located on top of the 3D sub-array 1001 a. In one embodiment, the page buffer and bit line decoder 1002a is formed by a 3D process using, for example, a Silicon-on-Insulator (SOI) or the like. In another embodiment, the page buffer and bit line decoder 1002A is formed on another die or wafer. The die or wafer may be connected to the 3D subarray 1001a using a 3D integration process such as copper pillars, micro bumps, Cu-Cu bonding, Through-Silicon vias (TSVs), and other suitable techniques.

FIG. 11A shows another embodiment of a 3D array according to the present invention. In this embodiment, the bit lines are used as temporary data storage. As described above, data may be loaded from the page buffer 200 to a plurality of bit lines, e.g., 201a to 201c, and held by bit line capacitances, e.g., 206a to 206 c.

FIG. 11B shows waveforms illustrating how data is loaded into the plurality of bit lines BL [0] to BL [2] illustrated in FIG. 11A. In this embodiment, the Drain Select Gate (DSG) may be turned off to isolate the string from the bit line.

FIG. 11C illustrates another embodiment of waveforms to load data to multiple bit lines. In this embodiment, the Drain Select Gates (DSG) of the plurality or all of the strings on the bit lines are turned on, and the word lines of the plurality or all of the strings on the bit lines are supplied with a bypass voltage (Vpass), for example, 6V, to turn on all of the cells. The Source Select Gate (SSG) is turned off. By using these operations, the capacitance of the bit line can be increased by increasing the channel capacitance of the string.

Fig. 11D shows waveforms illustrating reading data from a bit line capacitor (e.g., 206). Assume that bit lines BL [0] to BL [2] store data 0 to data 2 in their bit line capacitances. By sequentially turning on the bit line select gates BSG [0] to BSG [2], charge sharing can occur between the bit line capacitance and the sense node 302 of the page buffer circuit 200, as shown in FIG. 3A. Because the bit line capacitance is much larger than the sense node 302, the sense node 302 will become almost the bit line voltage in a very short time. Thus, the bit line select gates BSG [0] to BSG [2] can be switched very quickly to read the data of BL [0] to BL [2] very quickly.

The data held by the bit line capacitances 206a to 206C can be read by using a sensing operation as described in fig. 6C. Thus, the bit line capacitor may be used to store data. Referring to fig. 9D, assume that the array is divided into K sub-arrays. Each array includes N bit lines. Thus, the entire array contains K N bit lines. According to the present invention, it is possible to realize the storage of K × N bit data using the bit line capacitor.

In one embodiment, the array stores data in bit line capacitance, which can be used as a working memory, such as a DRAM. The system can read, write and refresh data like DRAM. When data is ready to be stored to the NAND flash memory cell for non-volatile storage, the data may be read from the bit line capacitor to the page buffer, as shown in fig. 6C, and then programmed to the NAND flash memory cell, as described in fig. 4B to 5C.

In another embodiment, the bit lines may be used as data registers to temporarily store input data. The operation of FIG. 6C may be used to read data from the bit lines and then program it to a selected page of NAND flash memory cells. For example, referring to fig. 9C, input data may be temporarily stored to bit lines in the sub-arrays 901a to 901C. Data can then be read from the bit lines of these sub-arrays and programmed to sub-array 901 d. Such a store operation provides a large "free" data register without increasing the area of the circuit.

FIG. 12A shows another embodiment of a 3D array according to the present invention. The circuit is capable of performing TLC and SLC programming modes. The array in FIG. 12A includes bit line select gates 202A-202 c and data latches 207 a-207 c, which store data bits D0, D1, and D2, respectively, for TLC programming. Also shown are latch bypass gates 220 a-220 c, which are also shown in fig. 3A-3B. During the TLC mode, the page buffer will program three bits of data D0-D2 to a single cell. During SLC mode, the page buffer will program the three bits of data D0-D2 to three different cells located in three bit lines. During TLC programming, the SLC signal turns off the bypass gates 221 a-221 c. The bit select gate signals BSG [0] to BSG [2] selectively turn on one of the bit line select gates 202a to 202 c. Signals P0 through P2 selectively turn on one of the bypass gates 220a through 220d according to the programmed Vt level to bypass the data of the latches to the selected bit line.

During SLC programming, the bit line select gates 202 a-202 c and the latch bypass gates 220 a-220 c may all be off. The signal SLC turns on the bypass gates 221a to 221 c. Thus, the data of latches 207 a-207 c are bypassed to bitlines 201 a-201 c, respectively. In this way, the multi-bit line can be programmed by simultaneously using data stored in a plurality of latches in the page buffer.

FIG. 12B shows another embodiment of a 3D array according to the present invention. As shown in FIG. 12B, the array includes bit line select gates 202 a-202 c and data latches 207 a-207 c, which store data bits D0, D1, and D2, respectively, for TLC programming. Also shown are latch bypass gates 220 a-220 c, which are also shown in fig. 3A-3B. During TLC programming, the SLCB signal turns on bypass gates 222a and 222 b. Signals BSG [0] to BSG [2] selectively turn on one of the bit line select gates 202a to 202 c. Signals P0 through P2 selectively turn on one of the bypass gates 220a through 220d to bypass the data of the latch to the selected bit line according to the programmed Vt level.

During SLC programming, the bit line select gates 202 a-202 c and the latch bypass gates 220 a-220 c may all be turned on. The SLCB signal opens the bypass gates 222a and 222 b. Thus, the data of latches 207 a-207 c may be bypassed to bitlines 201 a-201 c, respectively. In this way, the multi-bit line can be programmed by simultaneously using data stored in a plurality of latches in the page buffer.

FIG. 13 illustrates an embodiment of a NAND flash memory array. In the array shown in FIG. 13, bit line to bit line capacitances, e.g., 401a through 401c, may dominate the parasitic capacitance of the bit lines. Especially for high density arrays, the bit lines may be very long and the bit line pitch may be very tight. This can cause bit line to bit line coupling problems when loading data to multiple bit lines.

As an example, after the bit line select gate 202a is turned on to load data from the page buffer 200 to the bit line BL [0]201a, the select gate 202a is turned off. Then, the select gate 202b is turned on to load the next data from the page buffer 200 to the BL [1]201 b. During loading, BL [0] floats with the previously loaded data. Thus, the data of BL [1]201b may couple BL [0]201a through capacitor 401 a. As a result, the data of BL [0]201a may change due to this coupling. Similarly, after the data of BL [1]201b is loaded, select gate 202b is turned off. The select gate 202c is turned on to load the next data from the page buffer 200 to BL [2]201 c. The data of BL [2]201c may be coupled to BL [1]201b to change the data of BL [1 ].

FIG. 14 shows an array with bit line shields to prevent bit line coupling as described above. The array includes shielding devices 402 a-402 d added to the bit lines. Page buffer 200 operates to load data only to even bit lines, e.g., BL [0] and BL [2], or odd bit lines, e.g., BL [1] and BL [3 ]. When the even bit lines are loaded, signal SHD [1] turns on devices 402b and 402d to bypass VDD from the VSHD signal to the odd bit lines BL [1] and BL [3 ]. Thus, when data is loaded to even bit lines, such as BL [0] and BL [2], they are shielded by the odd bit lines BL [1] and BL [3], and therefore no coupling occurs between the bit lines. Meanwhile, because the odd bit lines BL [1] and BL [3] are supplied with the inhibit data VDD, the cells on the odd bit lines may not be programmed. Thus, in an embodiment, only half of the bit lines may be programmed at a time, which may reduce programming throughput by half. However, by using the array architecture described herein, programming throughput can be increased many times, such that using the above-described bitline shields may be acceptable.

FIG. 15A illustrates another embodiment of a circuit for mitigating bit line to bit line coupling. In the circuit shown in FIG. 15A, a plurality of bit lines BL [0] to BL [5] are alternately connected to page buffers 200a and 200b through bit line select gates 202a to 202f as shown. Each page buffer includes three data latches as described above. The page buffer provides data to either odd or even bit lines so that when one set of bit lines is in use, shielding is provided by the other set of bit lines. It should be noted that the number of bit lines and bit line select gates shown in FIG. 15A is exemplary. The present invention is applicable to any number of bit lines and bit line select gates.

FIG. 15B shows waveforms illustrating how data is loaded into the bit lines of FIG. 15A to mitigate coupling. During operation, signals BSG [0], BSG [2], and BSG [4] are sequentially turned on to load data D [0], D [2], and D [4] to bit lines BL [0], BL [2], and BL [4 ]. Signals BSG [1], BSG [3], and BSG [5] are sequentially turned on to load data D [1], D [3], and D [5] to bit lines BL [1], BL [3], and BL [5 ]. Note the timing of lines BSG [0] to BSG [5 ]. When BSG [1] is turned on to load D [1] to BL [1], BSG [0] is still on, so BL [0] is not floating. When BL [1] is coupled to BL [0], page buffer 200a holds the data of BL [0 ]. Thus, the coupling problem is alleviated or solved. Similarly, when BSG [2] is turned on to load D [2] into BL [2], BSG [1] is still on, so BL [1] does not float. When BL [2] is coupled to BL [1], page buffer 200b maintains the data of BL [1 ]. Thus, by using the circuit of FIG. 15A, the bit line coupling problem can be reduced or eliminated. However, when the last bit line BL [5] of the group is loaded, although it may not couple BL [4], it may couple an adjacent bit line in the next group (not shown). To solve this problem, the data of BL [0] may be loaded again. This restores the data of the adjacent bit line.

Fig. 16 illustrates an exemplary embodiment of a circuit that solves the last bit line coupling problem as described with reference to fig. 15A-15B. The circuit of fig. 16 includes two adjacent groups of bit lines 403a and 403 b. For these groups, their bit line select gates 202 a-202 f and 202a '-202 f' are mirrored. When group 403a loads data from BL [0] to BL [5], group 403b loads data from BL [0] 'to BL [5 ]'. For example, the data of BL [5] and BL [5] 'are loaded simultaneously, which solves the coupling problem between BL [5] and BL [5 ]'.

Fig. 17A shows an embodiment of a circuit including even and odd page buffers 200a to 200d as illustrated in fig. 16, and these page buffers are disposed on both sides of the array 404. For example, array 404 may also be a sub-array as shown at 901a in FIG. 9D.

Fig. 17A-17C illustrate embodiments of 2D and 3D versions of an array (or sub-array) 404 for use in the circuit of fig. 17A.

Fig. 18A to 18B show circuits having a divided bit line structure.

FIG. 18A shows a circuit including a plurality of page buffers 200a to 200d connected to global bit lines GBL [0] to GBL [3 ]. Global bit lines are connected to the plurality of blocks 405a to 405 n. Each block receives bit line select gate signals, such as BSG0[0:5] through BSGn [0:5 ].

Fig. 18B illustrates an embodiment of a circuit of one of the blocks (e.g., block 405a) illustrated in fig. 18A. As illustrated in FIG. 18A, a global bit line, e.g., GBL [1], is connected to sub-bit lines BL [1], BL [3], and BL [5] through bit line decoders 202a to 202 c. The structure of the bit line select gate is similar to that shown in fig. 17A. Thus, the waveforms shown in FIG. 15B may be used to apply data to sub-bit lines BL [0] to BL [5] and BL [0] 'to BL [5 ]', to address bit line coupling issues.

FIG. 19A shows another embodiment of a bit line select gate circuit according to the present invention. The circuit in this embodiment is similar to the circuit shown in fig. 15A except that four page buffers 200a to 200d are used, and data for two bit lines can be loaded at a time.

Fig. 19B shows waveforms illustrating the operation of the circuit of fig. 19A. During operation, when BSG [0] goes high, it will turn on both bit line select gates 202a and 202 a' to load data D [0] and D [1] from page buffers 200a and 200b to BL [0] and BL [1], respectively. When BSG [1] goes high, it will turn on both bit line select gates 202b and 202 b' to load data D [2] and D [3] from page buffers 200c and 200D to BL [2] and BL [3], respectively. Note that when BSG [1] is turned on, BSG [0] is still turned on. Thus, the coupling between BL [1] and BL [2] is eliminated. This same mechanism applies to all other select gates. As a result, the bit line coupling problem is solved.

Note that the bit line coupling problem described in FIG. 13 can occur not only when data is loaded in a write operation, but also in a read operation. Referring to the read waveform shown in FIG. 7A, during times T3-T4, when multiple bit lines, e.g., BL [0] to BL [2], are discharged together, the bit line with the turned-on cell will be discharged by the turned-on cell. Neighboring bit lines may be coupled to the off cell by bit line to bit line capacitance (401 a through 401c as shown in figure 13). Therefore, the voltage of the adjacent bit line may be pulled low and cause the off cell to be erroneously read as the on cell. To solve this problem, a shield device as shown in fig. 14 may be implemented, wherein the shield voltage VSHD may be 0V for a read operation. However, a masked read operation may only read even or odd bit lines, so it reduces read data throughput by half. To solve this problem, a solution shown in fig. 15A to 17C is provided.

FIG. 20A illustrates an embodiment of a circuit that addresses bit line coupling without sacrificing read data throughput. The circuit of FIG. 20A includes bit line select gates 202 a-202 c connected to bit lines BL [0] through BL [2 ]. The pull-up device 501 is a PMOS pull-up device coupled to the bit line select gates 202 a-202 c. In another embodiment, the pull-up device 501 may be an NMOS.

Fig. 20B shows waveforms for performing a read operation by the circuit shown in fig. 20A. Time interval T1 is the "development phase" and time interval T2 is the "evaluation phase". During the development phase (T1), VREF is supplied with 0V and the bit line select gates BSG [0] to BSG [2] are supplied with Vbias. This charges the bit lines BL [0] to BL [2] to a predetermined voltage Vbias-Vt, where Vt is the threshold voltage of the select gates 202 a-202 c.

During the evaluation phase (T2), the signal VREF may be supplied with a voltage that limits the current of the pull-up device 501 to be lower than the on-cell current (e.g., 10nA to 100 nA). BSG [0] to BSG [2] are turned off and then sequentially turned on to connect the bit lines BL [0] to BL [2] to the sense node SA, respectively. If the bit line has a turned-on cell, the bit line voltage may be lower than Vbias-Vt due to the turned-on cell current. Therefore, the sense node SA may be pulled low to be the same as the bit line voltage. On the other hand, if the selected bit line has a broken cell, the bit line will be fully charged to Vbias-Vt and the bit line select gate will be off. Thus, the sense node SA will go to VDD. The signal SA may be sent to the input of a comparator or to the gate of a PMOS transistor to determine the data.

Fig. 21A shows another embodiment of a readout circuit according to the present invention. This embodiment is similar to fig. 20A-20B except that a large pull-up device 502 may be used to pre-power up the bit lines.

Fig. 21B shows waveforms illustrating the operation of the circuit of fig. 21A.

Fig. 22A shows another embodiment of a readout circuit according to the present invention. This embodiment is similar to fig. 21A-21B except that a biasing device 503 is used to limit the pre-charge voltage of the bit line. Thus, the bit line select gate signals BSG [0] to BSG [2] are supplied with the digital signals VDD and 0V.

Fig. 22B shows waveforms illustrating the operation of the circuit of fig. 22A.

Fig. 23A shows another embodiment of a readout circuit according to the present invention. This embodiment is similar to fig. 22A-22B except that the bit lines are pre-powered by using pull-up devices 504 a-504 c.

Fig. 23B shows waveforms illustrating the operation of the circuit of fig. 23A.

Fig. 24A shows another embodiment of a readout circuit according to the present invention. This embodiment uses "source sensing".

Fig. 24B shows waveforms illustrating the operation of the readout circuit shown in fig. 24A, in which T1 is the "development" phase and T2 is the "evaluation" phase. During operation, a read voltage (Vrd) is supplied to a selected word line, and a bypass voltage (Vpass) is supplied to unselected word lines. The Source Line (SL) of the selected cell string is supplied with VDD. A discharge device 505 is added to discharge the bit line. The bit line select gates BSG [0] to BSG [2] are biased (Vbias) to limit the discharge current to a current lower than that of the turned-on cells, e.g., 10nA to 100 nA. Turning on the cell conducts current from the source line SL to the bit line and charges the bit line up to about Vrd-Vt (cell), where Vt (cell) is the threshold voltage of the turning on cell. For a disconnected cell, the bit line will discharge to 0V. As shown in fig. 24B, when the bit line of the on cell is charged, it may be coupled to the bit line of the off cell. However, after the coupling stops, the bit line of the open cell will be discharged to 0V by discharge device 505. During the evaluation phase (T2), the discharge device 505 is turned off. The biasing device 503 is turned on. The bit line select gates BSG [0] to BSG [2] are sequentially turned on to connect the bit line to the sense node SA to determine data according to the bit line voltage.

FIG. 25A shows another embodiment of a page buffer and bit line decoder circuit according to the present invention. Fig. 25A shows a page buffer circuit 200 and bit line select gates 202a to 202 f. The even bit line select gates 202a, 202c, and 202e are connected to PB [0], and the odd bit line select gates 202b, 202d, and 202f are connected to PB [1 ]. Page buffer 200 is coupled to PB [0] and PB [1] through shield voltage select gates 230a and 203b, respectively. The shield voltage selection gates 230a and 230b control the page buffer 200 to load data to or read data from PB [0] or PB [1], respectively. PB [0] and PB [1] are coupled to a "shield" Voltage Source (VSH) through select gates 231a and 231b, respectively. The shielding voltage may be 0V, VDD or any other suitable voltage. When the page buffer 200 reads data from or loads data to the even (or odd) bit lines, the shield voltage is applied to the odd (or even) bit lines. This eliminates the bit line capacitive coupling problem described with reference to fig. 13.

As an example, to perform a multi-page read or write operation on even bit lines, the shield voltage select gate 230a is turned on, and 230b is turned off. The even bit line selection gates BSG [0], BSG [2] and BSG [4] are sequentially turned on to read data from the even bit lines BL [0], BL [2] and BL [4] to the page buffer 200 or load data from the page buffer 200 to the even bit lines. At the same time, select gate 231a is turned off and 231b is turned on. This applies a shielding voltage VSH to PB [1 ]. The odd bit line select gates BSG [1], BSG [3], and BSG [5] are all turned on to bypass the shield voltage VSH to the odd bit lines BL [1], BL [3], and BL [5 ]. With these operations, even bit lines are shielded from each other by odd bit lines, thus eliminating bit line capacitive coupling.

FIG. 25B illustrates another embodiment of a page buffer and bit line decoder circuit according to the present invention. This embodiment is similar to the embodiment shown in FIG. 25A, except that the bit line shield voltage VSH is applied by select gates 232a through 232 f. The even select gates 232a, 232c, and 232e are connected to a control signal SB1, and the odd select gates 232b, 232d, and 232f are connected to a control signal SB 2. When the page buffer 200 reads or loads data from or to the even bit lines BL [0], BL [2], and BL [4], the shield voltage selection gate 230a is turned on and the gate 230b is turned off. The control signal SB1 will turn off the even select gates 232a, 232c, and 232 e. The control signal SB2 will turn on the odd select gates 232b, 232d and 232f to bypass the shield voltage VSH to the odd bit lines BL [1], BL [3] and BL [5 ]. Similarly, when odd bit lines are read or loaded with data, even bit lines may be supplied with a shield voltage.

FIG. 25C shows another embodiment of a page buffer and bit line decoder circuit according to the present invention. In this embodiment, the bit line select gates 202a to 202f are all connected to the page buffer 200. The even and odd bit lines are coupled to a shield voltage VSH through select gates 232 a-232 f. When the page buffer 200 reads or loads data to the even bit lines BL [0], BL [2], and BL [4], the even select gates 232a, 232c, and 232e are turned off. The even bit line select gates 202a, 202c, and 202e may be sequentially turned on to read data from the even bit lines to the page buffer 200 or to load data from the page buffer 200 to the even bit lines. At the same time, the odd bit line select gates 202b, 202d, and 202f are turned off. The odd select gates 232b, 232d, and 232f are turned on to bypass the shield voltage VSH to the odd bit lines BL [1], BL [3], and BL [5 ]. Similarly, when odd bit lines are read or loaded with data, even bit lines may be supplied with a shield voltage.

In the previous embodiment, for example, as shown in FIG. 4A, the chip may contain multiple data latches to store multiple pages of data during programming and reading. However, embodiments with fewer data latches are possible.

FIG. 26A shows an exemplary embodiment of a circuit according to the present invention that requires only one data latch to perform the same operations described above using multiple data latches. In another embodiment, the circuit of FIG. 26A may be configured to not use data latches. In the circuit of FIG. 26A, four bit lines BL [0] to BL [3] are connected to a page buffer 506 through four bit line select gates 202a to 202 d. The bit line select gates are connected to signals BSG [0] through BSG [3 ]. It should also be noted that the array may use the even/odd bit line architecture shown in fig. 25A-25C. The unselected even or odd bit lines are supplied with a dc voltage to shield the bit lines from bit line coupling. For simplicity, the circuit shown in FIG. 26A shows only selected bit lines.

The data line 510 is connected to a biasing device 508. The bias device 508 is used to pre-charge the data line 510 and the selected bit line to bias. The gate of the BIAS device 508 is connected to a BIAS, or feedback circuit or comparator to improve the pre-power-up speed.

Device 507 is a load device. The gate of the loading device 507 is connected to a reference voltage VREF to generate the desired loading current for the sensing operation. In another embodiment, the loading device 507 may be implemented by an NMOS device. Furthermore, the loading device may include a plurality of different sized devices, such as a larger device for fast pre-power-up and a smaller device for data readout.

Assuming that word line 509 is selected for programming, bit lines BL [0] and BL [1] are loaded with 0V to program cell 0 and cell 1. Bit lines BL [2] and BL [3] are loaded with VDD to disable cell 2 and cell 3. According to the novel programming operation provided by the embodiments of the present invention, bit line data is sequentially loaded by sequentially turning on the bit line select gates 202a to 202d to store the bit line data with bit line capacitance.

After one programming pulse, program verification is performed to check the Vt of the programmed cell and determine the next program data. As an example, assume that cell 0 through cell 3 have four different cases. Assume that cell 0 is still a turn-on cell. This means that cell 0 has not yet been successfully programmed. The next data for BL [0] should be 0V to continue programming cell 0. Assume that cell 1 has been successfully programmed to the desired Vt, so it will become a disconnected cell during verify. This means that the next data for BL [1] should be changed to VDD to disable cell 1. Cell 2 and cell 3 are assumed to be on and off cells, respectively, since their current programming data is VDD, which means that they do not need to be programmed. The next data for BL [2] and BL [3] should be held at VDD to disable cell 2 and cell 3.

FIG. 26B illustrates a program verify operation for use with the circuit shown in FIG. 26A. This operation basically comprises three steps, namely: pre-power up bit line step 511, discharge bit line step 512, and read and update bit line data step 513. For step 511 (pre-powering up the bit lines), at time T0, VDD is supplied to BSG [0] to BSG [3] to turn on all of the bit line select gates 202 a-202 d. VREF is supplied with 0V to fully turn on the loading device 507 for fast pre-power up. BIAS voltage Vbias is supplied to BIAS. This condition pre-powers BL [0] to BL [1] from 0V to Vbias-Vt. Vt is the threshold voltage of the bias device 508. Meanwhile, BL [2] and BL [3] are held at VDD. Typically, the BIAS signal has a range of about Vt to VDD, and should be greater than Vt to turn on the BIAS device (e.g., device 508 shown in fig. 26A). The BL voltage is pre-powered up to the BIAS voltage minus the Vt of device 508 shown in fig. 26A.

For step 512 (discharge bit lines), at time T1, all of the bit line select gates BSG [0] to BSG [3] are turned off. The source select gate SSG 516 and the drain select gate DSG 515 of the selected string are turned on. The verify voltage and the bypass voltage are supplied to the selected word line 509 and other unselected word lines, respectively. 0V is supplied to the source line 518. This will turn on the cells (i.e., cell 0 and cell 2) to discharge BL [0] and BL [2], respectively. BL [0] will be discharged from Vbias-Vt to a voltage lower than Vbias-Vt. In contrast, BL [2] may still be above Vbias-Vt because the initial voltage of BL [2] is VDD. Due to the large bit line capacitance, it will take a long time to discharge BL [2] below Vbias-Vt using the on-cell current. BL [1] and BL [3] will remain at the pre-power-up voltages Vbias-Vt and VDD, respectively. Since cell 1 and cell 3 are off cells s, they do not discharge BL [1] and BL [3 ].

At time T2, source select gate 516 or drain select gate 515 is turned off to prevent cell 0 and cell 2 from discharging BL [0] and BL [2 ]. The bit line voltage will then be maintained by the large bit line capacitance. In another embodiment, source select gate SSG 516 and drain select gate DSG 515 are held high from T2 to T9. This will cause the on cells (i.e., cell 0 and cell 2) to continue discharging BL [0] and BL [2 ]. However, since the sensing time (T2-T9) is short, the current of cell 2 does not discharge BL [2] below Vbias-Vt before the end of verify.

At step 513 (sensing and updating bit line data), at time T2, a reference voltage VREF is supplied to VREF to control the loading current of the loading device 507. The loading current is preferably lower than the switch-on cell current. Then, in the interval between times T2 to T9, the bit line select gates BSG [0] to BSG [3] are sequentially turned on to connect the sense circuits to BL [0] to BL [3], respectively. The sense circuit will verify the bit line voltage and load the next data to the bit line according to the result.

At time T2, the select gate signal BSG [0] will turn on the bit line select gate 202a shown in FIG. 26A. This results in charge sharing between BL [0] and data line DL 510 and signal node SA 514. Because the capacitance of BL [0] is much larger than the capacitance of data lines 510 and SA514, both data lines 510 and SA514 will be pulled down to a voltage near BL [0] that is lower than Vbias-Vt in a short amount of time. The SA514 node is connected to the data buffer 506. The data buffer 506 will determine the verify data to be 1 based on the level of the SA.

At time T3, based on the verification result, the LOAD signal will go high to LOAD 0V back into BL [0 ]. BSG [0] will then go low to isolate BL [0] from the data line 510 and sense circuitry. As a result, cell 0 will be programmed again by the next program pulse because BL [0] is loaded with 0V.

In one embodiment, from time T2 to T4, BSG [0] is supplied with VDD + Vt. This allows the page buffer to load the full VDD to the bit line when the next data is VDD. Clearly, BSG [0] can be supplied with VDD, which only loads the bitlines to VDD-Vt. In another embodiment, BSG [0] may use a two-step pulse, where VDD is used for verify and VDD + Vt is used for load of the next data.

At time T4, BSG [1] will turn on the next bit line select gate 202b to connect the sensing circuit to BL [1] to verify the voltage of BL [1 ]. BL [1] is pre-powered up to Vbias-Vt in advance. Because the capacitance of the data line 510 is much less than the capacitance of BL [1], the result of charge sharing will cause the voltage of the data line 510 to become very close to the voltage of BL [1] (e.g., Vbias-Vt) which will turn the bias device 508 off. Therefore, the SA node 514 charges the load current of the loaded device 507 to full VDD. This indicates that the next data will be 1.

At time T5, the LOAD signal will go high to LOAD VDD into BL [1 ]. BSG [1] will then go low to isolate BL [1] from the page buffer circuit. As a result, cell 1 will be inhibited from the next programming because it has passed the program verify.

At time T6, BSG [2] will turn on the next bit line select gate 202c to verify the voltage of BL [2 ]. Because BL [2] is held at a voltage higher than Vbias-Vt, the biasing device 508 will be turned off. If the previous bit line pulls SA low, the SA node will be charged to full VDD by the loading current of device 507. This indicates that the next data will be 1.

At time T7, the LOAD signal will go high to LOAD VDD into BL [2 ]. BSG [2] will then go low to isolate BL [2] from the page buffer circuit. For the next program pulse, cell 2 will again be inhibited.

At time T8, BSG [3] will turn on the next bit line select gate 202d to verify the voltage of BL [3 ]. Because BL [3] remains at VDD, the bias device 508 will be turned off. If the previous bit line pulls SA low, the SA node will be charged to full VDD by the loading current of device 507. This indicates that the next data will be 1.

At time T9, the LOAD signal will go high to LOAD VDD into BL [3 ]. BSG [3] will then go low to isolate BL [3] from the page buffer circuit. For the next programming pulse, cell 3 will be inhibited again.

After the bit line is verified and loaded with the next data, the selected word line may be raised to the programming voltage, e.g., 20V, to perform the next programming pulse, as shown at time T3 in FIG. 5E.

It should be noted that during sensing step 513, the charge-shared data line 510 voltage may be slightly below Vbias-Vt if the previously selected bit line has an on cell. This may cause the biasing device 508 to turn on. If the selected bitline has an open cell, the load current of the load device 507 charges the bitline and data line to Vbias-Vt and pulls the SA node 514 to VDD. However, this may cause a delay. To address this issue, in another embodiment, VBIAS voltage may be lowered slightly during the sensing step 513, as shown by dashed line 517 in fig. 26B. This will prevent the biasing device 507 from being turned on by the slightly lower data line 510.

In another embodiment, the biasing device 508 may comprise two devices, one for pre-power-up and one for readout. The device used for sensing may have a longer channel length or a different Vt adjustment implant to make its Vt slightly higher. In another embodiment, the gates of the two biasing devices may be connected to different biases. The bias voltage for readout may be slightly lower than the bias voltage for pre-power-up.

Also, during sensing step 513, if the next data for the previously selected bit line is VDD, then the data line 510 is pulled up to VDD. If the next bit line has a cell turned on, this may cause the charge sharing voltage to become too high if the bit line capacitance is not high enough. To address this issue, in another embodiment, the data buffer 506 may apply a short pulse to discharge the data line 510 to 0V before the next bit line select gate is turned on after the previous bit line select gate is turned off, and then let the bias device 508 pre-charge the data line 510 to Vbias-Vt. This may provide the desired initial voltage to the data line 510 prior to each charge sharing. In another embodiment, a discharge device, shown as 505 in fig. 24A, may be connected to the data line 510 to perform the discharge.

The circuits and operating waveforms shown in fig. 26A-26B are examples that demonstrate one embodiment of the invention. It is well known that the circuitry and operating waveforms can be modified in many other ways. For example, the readout circuit shown in fig. 20A to 24B may be used instead of the readout circuit shown in fig. 26A. Such modifications and variations are within the scope of the present invention.

FIG. 26C illustrates an embodiment of a circuit implementation of the data buffer 506 in FIG. 26A. The circuit includes a data latch 520. The data latch 520 is reset by applying a RES pulse to turn on the NMOS 521. This pulls the DA node 525 down to 0V. The SA node of the preceding stage sense circuit is connected to PMOS 523. As depicted in FIG. 26B, for a bit line with a disconnected cell, the SA node is pulled up to VDD. This will turn off PMOS 523. For bit lines with turned cells on, the SA node is pulled down below Vbias-Vt. This will turn on PMOS 523. After the SA voltage is ready, a LATB pulse may be applied to turn on PMOS 522. If SA is low, it pulls up the DA node 525 to VDD. If SA is high, DA node 525 will remain at 0V. Thereafter, a LOAD pulse may be applied to LOAD the data of the latch 520 into the data line DL.

Note that the embodiment shown in fig. 26C is an exemplary circuit intended to minimize the circuit size. It is apparent that more complex circuitry (e.g., sense amplifier or comparator circuitry) may be used in place of the input stage formed by PMOSs 522 and 523. Such variations and modifications are to be considered within the scope of the present invention.

FIG. 26C illustrates another embodiment of a circuit implementation using the sensing circuit shown in FIG. 20A. In this embodiment, the biasing device 508 as shown in FIG. 26A is eliminated. The function of the biasing devices is performed by BSG [0] to BSG [3], as shown by the waveforms in FIG. 27B.

As previously described, program data is loaded into the bit lines and stored in the bit line capacitance during programming. During verify, the cell's data is verified directly from the bit line and the next program data is loaded back to the bit line. There is no need to store data in the page buffer or the data latch. This significantly reduces the need for a large number of data latches. For example, when eight bit line select gates BSG [0] to BSG [7] are used, the previous method shown in FIG. 4A requires eight data latches to store eight data for BL [0] to BL [7 ]. For the present embodiment shown in FIG. 26A, only one data latch would be needed since the program data is loaded into the bit lines and stored in the bit line capacitance, and no data latch would be needed at all if the input data were loaded directly into the bit lines. This may significantly reduce circuit size and data throughput, especially for products using only SLC single level cells, which may not have multiple bit data latches in the page buffer.

FIG. 27C illustrates another embodiment of a program verify operation according to the present invention using the embodiment of the page buffer 200 and the bit line select gates 202 a-202 n illustrated in FIG. 6F. A detailed embodiment of the page buffer 200 is shown in fig. 3C. For example, as illustrated in fig. 3C, the page buffer circuit 200 includes a bias device 306 and a pre-power-up device 303 connected to the SA node. Also shown are sense device 310, latch bypass gate 220, set device 311, reset device 312, and data latch 207 having Q and QB nodes. The above description of fig. 3C provides detailed circuit operation.

As illustrated in FIG. 27C, it will be assumed that four bit lines BL [0] to BL [3] as illustrated by 201a to 201d in FIG. 6F are used to perform a program verify operation. Assume that BL [0] and BL [1] are program bit lines and BL [2] and BL [3] are inhibit bit lines. The data stored in BL [0] and BL [1] are 0(0V), respectively, and the data stored in BL [2] and BL [3] are 1(VDD), respectively.

At time T0, VDD is supplied to signals BSG [0:3] to turn on the bit line select gates 202 a-202 d. Signal PREB supplies 0V to turn on pre-power-up device 303 to charge the SA node to VDD. The signal BIAS supplies the BIAS voltage Vbias. This charges the program bit lines BL [0] and BL [1] from 0V to Vbias-Vt of the bias device 306, while the inhibit bit lines BL [2] and BL [3] remain at VDD. In a preferred embodiment, Vbias may be slightly higher than Vt1+ Vt2, where Vt1 and Vt2 are the threshold voltages of the bias device 306 and the sense device 310. This allows the turned-on cell to quickly discharge the bit line voltage below the Vt of the sense device 310.

At time T1, a pulse is supplied to signal SET to SET the Q node of latch 207 to 0V.

At time T2, signals BSG [0:3] go low to turn off bit line select gates 202 a-202 d. The verify voltage VR is supplied to the selected Word Line (WL). Signal DSG goes high to turn on the drain select gate of the selected string. Assume that the selected cells on BL [0] and BL [2] are on cells (Vt < VR), and the cells on BL [1] and BL [3] are off cells (Vt > VR). Turning on the cells discharges the voltages of BL [0] and BL [2 ]. Because BL [0] and BL [2] have different initial voltages, after a period of time BL [0] is discharged below Vt, while BL [2] is above Vt and even Vbias-Vt.

At time T3, signal BSG [0] goes high to turn on bit line select gate 202a to couple BL [0] to page buffer 200. Since BL [0] is at a voltage lower than Vbias-Vt, the bias device 306 is turned on to pull the SA node of the page buffer down to the same voltage as BL [0 ]. The SA voltage turns off sensing device 310.

At time T4, a pulse is supplied to the signal RES to turn on the reset device 312. However, since the sensing device 310 is turned off by the voltage of the SA node, the latch 207 is not reset, and the Q node of the latch 207 maintains 0V.

At time T5, signals PGM, BIAS, and PREB are pulsed to update the program data on BL [0 ]. It loads data 0(0V) from the Q node of latch 207 to BL [0 ]. Thus, the program data on BL [0] is updated to 0 (0V). Because the cell on the programmed bit line BL [0] is an on cell, indicating that the cell has not been successfully programmed, it will be programmed again by the next program pulse.

At time T6, signal BSG [0] goes low to turn off the bit line select gate 202a of BL [0 ]. Signal BSG [1] goes high to turn on bit line select gate 202b of BL [1] to couple BL [1] to the page buffer. Because the cell on BL [1] is an off cell, the voltage of BL [1] remains at the pre-power-on voltage Vbias-Vt, which turns off the bias device 306. Accordingly, the SA node of the page buffer is pulled up to VDD to turn on the sensing device 310.

At time T7, a pulse is supplied to the signal RES to turn on the reset device 312. Because sense device 310 is turned on by the voltage of the SA node, reset device 312 resets the Q node of latch 207 to VDD.

At time T8, signals PGM, BIAS, and PREB are pulsed to update the program data on BL [1 ]. It loads data 1(VDD) from the Q node of latch 207 to BL [1 ]. To load VDD into BL [1], the levels of signals PGM, BIAS, and PREB may be VDD + Vt. Thus, the program data on BL [1] is updated from 0(0V) to 1 (VDD). Since the cell on programmed bit line BL [1] is an open cell, this indicates that the cell was successfully programmed. Therefore, it will be inhibited during the next program pulse.

At times T9 and T10, signals BSG [2] and BSG [3] go high to turn on bit line select gates 202c and 202d on BL [2] and BL [3], respectively. The foregoing operations from time T3 to time T6 are repeated to verify the cells and update the bit line data for BL [2] and BL [3], respectively. Because both BL [2] and BL [3] voltages are above Vbias-Vt, the biasing device 306 is turned off and the SA node is pulled up to VDD. Similar to BL [1], the Q nodes of latches 207 of BL [2] and BL [3] will be reset to data 1(VDD) by reset pulse RES and updated by PGM, BIAS and PREB pulses to charge BL [2] and BL [3] to data 1 (VDD). As a result, BL [2] and BL [3] that were originally disabled remain at the disable voltage VDD.

In the above embodiment, VDD is used as the inhibit voltage. In another embodiment, the inhibit voltage may be VDD-Vt. In this case, at time T8, when the pulses are applied to signals PGM, BIAS and PREB, the pulses may be at the VDD level, which charges BL to VDD-Vt.

FIG. 28A illustrates an exemplary embodiment of waveforms for a read operation. These waveforms are similar to the program verify waveforms shown in FIG. 26B, except that the step of loading the next data back to the bit line is eliminated. Also, the selected word line is supplied with a read voltage instead of a verify voltage. The read waveform illustrates how four cells, cell 0 through cell 3, are read sequentially. In this example, cell 0 and cell 2 are on cells s, and cell 1 and cell 3 are off cells s. During step 511 (pre-powering up bit lines), all bit lines BL [0] to BL [3] are pre-powered up to Vbias-Vt. During step 512 (discharging the bit lines), turning on the cells will discharge BL [0] and BL [1] to a voltage below Vbias-Vt. During step 513 (sensing), the bit line select gates BSG [0] to BSG [3] are sequentially turned on to connect the sensing circuit to BL [0] to BL [3 ]. This results in charge sharing between the capacitance of the data line 510 and the bit line. Since the capacitance of the data line 510 is much smaller than the bit line capacitance, the SA node 514 will be pulled up and down in a short amount of time.

FIG. 28B illustrates another embodiment of waveforms for a read operation used with the circuit embodiment shown in FIG. 17A. This waveform is similar to the verify waveform shown in FIG. 27B, except that the step of loading the next data back to the bit line is eliminated.

Fig. 29A shows a layout arrangement of a page buffer circuit of a conventional 3D NAND flash memory. The flash memory includes a 3D NAND flash memory sub-array 601. The sub-array 601 includes a plurality of cell strings, such as an equivalent circuit shown in fig. 17C. The bit lines are located at the top of the array 601 and extend in the Y direction. The page buffer 602 is connected to the bit lines through contacts 603a to 603 n. In an All Bit Line (ABL) design, the number of page buffers is the same as the number of bit lines. Each bit line is connected to one page buffer. In a Half Bit Line (HBL) design, the number of page buffers is half of the bit line. Each page buffer is connected to two bit lines. The circuit 604 is used for data paths, redundancy, page buffer drivers, word line drivers, etc. Page buffers 602 and circuitry 604 are located below the array 601 to reduce die size.

Fig. 29B shows a conventional array configuration with two adjacent sub-arrays 601a and 601B. It should be noted that the page buffers 602a and 602b are interleaved with the circuits 604a and 604b so that the circuits 604a and 604b can drive the page buffers 602b and 602a, respectively. The structure shown in fig. 29B is referred to as a "tile". A large memory array may be formed by arranging a plurality of tiles in the X and Y directions.

Fig. 30A shows an embodiment of a layout arrangement of page buffers and circuits for a 3D array according to the present invention. In the present embodiment, the 3D sub-array is divided into a plurality of sectors 601a to 601D. The bit lines between sectors are separated. The bit lines of sectors 601a to 601d are connected to page buffers 602a to 602d through contacts 603a to 603n, respectively. Contacts 603a through 603n may be located on the edges of sectors 601a through 601 d. The circuits 604a to 604d are circuits for data paths, redundancy, page buffer drivers, word line drivers, and the like.

For the conventional technique shown in fig. 29A, the number of bit lines is 1 KB. The 1Kb bit lines are connected to a 1Kb page buffer in 602 to perform program, verify, and read operations simultaneously. For the embodiment according to the present invention shown in fig. 30A, it is assumed that the sub-array is divided into 4 sectors as shown in 601a to 601 d. Each sector will contain a 1KB bit line, the length of each bit line being 1/4 the length of a conventional technology bit line.

It is assumed that the present invention has the same total number of page buffers of 1KB as the conventional technique. The page buffers are divided into 4 groups 602a to 602 d. Each group contains 256B page buffers. By using 4 bit line select gates, such as 202a through 202d shown in FIG. 27A, each set of 256B page buffers can be connected to 1KB bit line for each sector and perform simultaneous program, verify, and read operations on all bit lines. As a result, the present invention can simultaneously read and write to a total of 4KB bit lines. This increases data throughput by a factor of 4 significantly without increasing die size.

Also, since the bit line length of each sector is only 1/4 for the conventional circuit, the read and verify speed can be significantly improved. This reduces the bitline capacitance to about 1/4, thus greatly reducing bitline charge and discharge times.

In accordance with the present invention, the sub-array may be divided into any number of sectors. The more sectors are used, the more pages can be read and written simultaneously. For example, assume that the sub-array is divided into N sectors. The total page on which the read and write operations can be performed simultaneously becomes N times, so that the data throughput is increased by N times. In addition, the bit line length becomes 1/N, which increases the access speed by N times. A consideration of embodiments of the present invention is the addition of bit line select gates, which are very low and negligible.

FIG. 30B illustrates an exemplary embodiment of a tile formed from two adjacent sub-arrays as shown in FIG. 30A. The page buffers 602e through 602h and circuits 604e through 604h of the second sub-array may be interleaved with the page buffers and circuits of the first sub-array. Thus, the circuits 604a to 604d may drive the page buffers 602e to 602h, respectively, and the circuits 604e to 604h may drive the page buffers 602a to 602d, respectively.

Fig. 31A to 31B show an embodiment of a page buffer configuration according to the present invention. These embodiments are similar to fig. 30A to 30B except that layout arrangements of the page buffers 602a to 602d and the circuits 604a to 604d are different. Similar to the embodiment of fig. 30A-30B, the bit lines of sectors 601 a-601 d are connected to page buffers 602 a-602 d using contacts 603 a-603 n, respectively.

Although the embodiment in fig. 30A to 30B shows a 3D array structure, it will be apparent to those skilled in the art that the present invention can be implemented in a 2D array structure. In these 2D embodiments, the page buffers and circuitry are located to the sides of the sectors.

Fig. 32 illustrates an exemplary embodiment of a page buffer and bit line select gate structure according to the present invention. In the present embodiment, the page buffer 701 is connected to a plurality of array sectors 702a to 702d through data lines 703. The number of sectors may be any number. For clarity, it will be assumed that four sectors are used: sector 0 through sector 3. The bit lines for each sector are connected to data lines 703 through bit line select gates (e.g., 704 a-704 h and 705 a-705 h). It will also be assumed that eight bit line select gates are used, e.g., BSG0[0] through BSG0[7] and BSG3[0] through BSG3[7 ]. For a 3D array architecture, bit line select gates (e.g., 704 a-704 h and 705 a-705 h), page buffers 701, and data lines 703 may be located below array sectors 702a and 702D.

The divided sector structure in the present embodiment provides a number of advantages. First, since the data line 703 spacing is much larger than the bit line spacing, the total bit line capacitance will be 1/8 bit line length capacitance plus the data line capacitance. As a result, the total bit line capacitance is much smaller than conventional arrays. This will significantly improve the pre-charge and discharge speed of the bit lines in read and verify operations.

Second, the page buffer 701 may load different data to bit lines in the multiple sectors 702 a-702 d to perform a multi-page program and verify operation using the previously described operations. This will significantly increase the programming data throughput.

Third, the page buffer 701 may simultaneously perform pre-power-up and discharge operations on bit lines in the plurality of sectors 702a to 702d using the previously described operations. This will significantly increase the read data throughput. Although the length of the data line 703 is longer than the data line 510 of the previous embodiment shown in FIG. 26A, the read and verify operations described in FIG. 26A will still operate for this embodiment because the capacitance of the data line 703 is relatively smaller than the bit line capacitance. However, since the capacitance of the data line 703 is large, the speed may be slow.

Fourth, the bit line capacitances of the plurality of sectors may be used as a data buffer to store a plurality of pages of data using the waveforms shown in fig. 11B to 11C. For example, when programming data to a selected page in sector 0, the next three pages of data can be input and stored in the bitlines of sector 1, sector 2, and sector 3. In another embodiment, the data stored in sector 1, sector 2, and sector 3 may be programmed into the page in sector 0 using the TLC three-layer cell mode.

For the embodiments shown in fig. 26A, 27A, and 32, the program data may be stored directly in the bit line capacitance. This reduces the number of data latches required for the page buffer of each bit line. Therefore, more page buffers can be packaged within the chip to increase read and write data throughput. However, during "program suspend," if the requested data is located in a sector during programming, the data stored in the bit lines may need to be moved to other unselected sectors before a read operation can be performed. After the read operation is complete, data may be read from the unselected sectors and reloaded into the selected sectors to continue the programming operation.

For this reason, one sector may be set aside when multi-sector programming is performed on all sectors in a plane or group. Thus, when the system issues a programming suspension, the data for the selected sector may be transferred to the remaining sectors. After the requested data is read from the selected sector, the data stored in the remaining sectors may be transferred back to the selected sector to continue programming.

Fig. 33A shows another embodiment of a page buffer and bit line select gate structure according to the present invention. In the present embodiment, the page buffer 820 is connected to the first group of bit lines 821a to 821n through the bit line select gates 823a to 823 n. The page buffer 820 is connected to a second set of bit lines 822a through 822n through bit line select gates 824a through 824 n.

Assuming that page 825 in first bit line group 821 a-821 n is selected for programming, second bit line group 822 a-822 n may be used to store programming data. The multiple page programming can be performed by using the following steps. First, input data D [0] to D [ N ] are sequentially loaded into the second bit line groups 822a to 822N by using the operations described in fig. 11A to 11C. The data will be held by the bit line capacitance. Next, the data held by the second bit line group may be sequentially read by the page buffer 820 using the operation described in fig. 11D and loaded to the first bit line groups 821a to 821n by using the operations described in fig. 5A to 5E to program the selected page 825.

After one program pulse, a program verify operation can be performed by using the operations described in fig. 7A to 7D to read data from the program cells in the selected page 825. During the time interval between T4 through T6 of fig. 7A through 7D, the data of the first set of bitlines 821a through 821n may be compared with the input data stored in the second set of bitlines 822a through 822n to generate the next program data, and the next program data is loaded back into the first set of bitlines 821a through 821 n. The next programming pulse is then applied.

The program and program verify operations may be alternately repeated until the data read from the selected page 825 is equal to the input data stored in the second set of bit lines 822 a-822 n. Then, the programming operation is completed. Data stored in first bit line groups 821a through 821n and second bit line groups 822a through 822n may be cleared.

Similarly, when the selected page is located in the second set of bit lines 822a through 822n, input data may be loaded to the first set of bit lines 821a through 821n and stored by the bit line capacitance. The input data may be used to verify program data of a selected page in the second bit line group 822a through 822 n.

In another embodiment, when the input data is loaded, the bit line select gates 823a to 823n and 824a to 824n may be sequentially turned on together to load the input data to the first and second bit line groups 821a to 821n and 822a to 822n because the first program data may be the same as the input data.

During a read operation, the operations described in fig. 7A-7D may be applied to pre-charge and discharge the first set of bit lines 821 a-821 n in parallel. Then, the bit line select gates 823a to 823n may be sequentially turned on to read out data of the bit lines 821a to 821n to the page buffer 820. The embodiment shown in fig. 33A may also be applied to the programming of multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), or any other level cells.

Fig. 33B shows an embodiment configured for MLC programming. It will be assumed that page 825 in first bit line group 821a through 821n is selected. A first page (upper page) of input data may be sequentially loaded onto even bit lines, e.g., 822a, 822 c. A second page (lower page) of input data may be sequentially loaded onto the odd bit lines, e.g., 822b, 822 d.

Then, the upper page data stored in the even bit lines 822a and the lower page data stored in the odd bit lines 822b are sequentially read to the page buffer 820. The page buffer 820 may include two data latches to store two bits of data. The page buffer 820 determines program data of a threshold voltage level (Vt) of the first cell according to the two-bit data and then loads the program data to the first even bit lines 821a of the first bit line groups 821a through 821 n.

Then, next program data is determined from data stored in the bit lines 822c and 822d of the second bit line group and then loaded to the second even bit line 821c of the first bit line group. This operation is repeated until all the program data is loaded to the even bit lines 821a, 821 c. Then, a program pulse is applied to program the even cells on the selected word line 825.

During program verification, the two-bit data stored in the second bit line group 822a to 822n is sequentially read to the page buffer 820 to be compared with the data read from the selected page 825 to determine the next program data. The next program data is loaded back to the even bit lines of the first set of bit lines 821 a-821 n. The next programming pulse will then be applied. These operations are repeated until all three Vt levels for the MLC are successfully programmed, and then the programming operation is completed.

Thereafter, data of the next upper and lower pages may be loaded to even bit lines and odd bit lines of the second bit line groups 822a through 822n, respectively. The above operations are applied to program data into the odd bitlines 821b, 821d, 821n of the first group of bitlines.

The even bit lines and the odd bit lines of the first bit line groups 821a through 821n belong to two pages. During a read operation of reading an even bit line page, a first read voltage is supplied to a word line of the selection page 825 to read data of an upper page by using the operations described in fig. 7A to 7D. Data is sequentially stored to even bit lines of the second bit line groups 822a through 822 n.

Next, a second read voltage is supplied to the word line of the selected page 825 to read the data of the lower page by using the operations described in fig. 7A to 7D. The upper page data stored in the even bit lines of the second bit line group 822a to 822n may be read to the page buffer 820 to be compared with the data stored in the first bit line group to determine the data of the lower page. The data of the lower page is then stored in the odd bit lines of the second bit line group 822a through 822 n.

Next, a third read voltage is supplied to the word line of the selected page 825 to read the data of the lower page again by using the operations described in fig. 7A to 7D. The upper page data stored in the even bit lines of the second bit line groups 822a to 822n and the previously read lower page data stored in the odd bit lines of the second bit line groups 822a to 822n may be read to the page buffer 820 to be compared with the data stored in the first bit line group to determine the data of the lower page. The data of the lower page is then stored in the odd bit lines of the second bit line group 822a through 822 n.

Accordingly, when a program operation and a read operation are performed on the second bit line groups 822a to 822n, the first bit line groups 821a to 821n may be used to store input data and output data, respectively.

Fig. 33C shows another embodiment of a TLC programming application. The operation is similar to that shown in fig. 33B, except that three input pages (i.e., upper, middle, and lower pages) of the TLC unit are loaded into 822a, 822B, 822c to 822l, 822m, and 822n, respectively. The page buffer 820 includes three data latches to store three-bit data read from a second set of bit lines (e.g., bit lines 822a, 822b, and 822 c). The page buffer 820 determines program data according to the three-bit data and loads the program data to the first bit line group. As a result, data stored in the second set of bit lines 822a, 822b, and 822c is programmed to the first set of bit lines 821 a. During a read operation, three bits of data read from a cell on the first set of bit lines 821a will be stored in the second set of bit lines 822a, 822b, and 822c, respectively. Since the TLC programming and reading operations are similar to the MLC operation described in fig. 33B, the detailed operations will not be repeated.

The embodiment shown in fig. 33A-33C may perform a "program suspend" function. For example, assume that page 825 is under programming. Input data is stored in the second bit line group 822a through 822 n. If the system wants to read another page of the first set of bit lines 821 a-821 n, the program operation may be suspended. The program data in the first group of bit lines 821 a-821 n is cleared, and a read operation is performed using the operations described in fig. 7A-7D to read data from the selected page. After the read operation is complete, the programming operation may resume. The input data stored in the second bit line group 822a to 822n may be read to again generate program data for the first bit line group 821a to 821 n.

On the other hand, if the read page is located in the second bit line groups 822a to 822n, the data of the first bit line groups 821a to 821n may be cleared. Data stored in the second set of bit lines 822a through 822n may be read and transferred to the first set of bit lines 821a through 821 n. Thereafter, the selected page in the second bit line groups 822a through 822n is read. After the read operation is completed, the data stored in the first bit line groups 821 a-821 n may be transferred back to the second bit line groups 822 a-822 n. The programming operation may then resume.

The embodiments shown in fig. 33A to 33C may also perform a "simultaneous read/write" or "read while write" operation. It is assumed that the first bit line group 821a to 821n is performing a program operation using the method described in fig. 26A to 28B. This method stores input data in a selected bit line and directly updates data in the bit line during program verify. It does not require the input data to be stored at another location. Accordingly, when programming the first bit line groups 821 a-821 n, the second bit line groups 822 a-822 n may simultaneously perform a read operation using the operations described in fig. 7A-7D.

The embodiment shown in fig. 33A-33C may also perform a "data folding" operation that converts data stored in SLC pages to MLC or TLC pages. This mode is used to improve the programming data throughput. During sequential write operations, the system may write data using SLC mode. This significantly reduces the writing time. During idle times, the data stored in the SLC page is then read and reprogrammed to other pages using MLC or TLC modes. Thereafter, the SLC page is erased. This may increase data storage density.

Referring again to FIG. 33C, assume that page 826 is an SLC page. To transfer data from the SLC page 826 to the TLC page 825, the data of the SLC page 826 is read by using the operations described in figures 7A-7D. The second set of bit lines 822 a-822 n are pre-powered up and discharged by the cells on the SLC page 826. Then, data of the second group of bit lines 822a to 822n is sequentially read through the page buffer 820 by using the MLC and TLC programming operations described in fig. 33B to 33C to determine program data of the TLC page 825. For example, the data of the second bit lines 822a, 822b and 822c is used for determining the program data of the first group 821 a. As a result, the data stored in the SLC page 826 is programmed to the 1/3 bit lines, e.g., bit lines 821a, 821 d.

Thereafter, the next SLC page in the second set of bit lines 822a through 822n may be read and the above operations repeated to program data to the next 1/3 bit line of the TLC page 825, e.g., bit lines 821b, 821 e. Thereafter, a third SLC page in the second set of bitlines 822a through 822n may be read programmed to the 1/3 bitlines below the TLC page 825, such as bitlines 821c, 821f,.. or 821 n.

FIG. 34A shows page buffers and bit line connections for a conventional 3D NAND flash memory. Metal bit lines 901a to 901D extend on top of the 3D cell array. The 3D cell is not shown in fig. 34A, but the detailed 3D array structure can be seen in fig. 10D, 10E and 17C. Page buffer circuits 902a to 902D are located below the 3D array. Bit lines 901a to 901d connect page buffers 902a to 902d through vertical contacts 903a to 903 d.

Although the embodiment in fig. 34A shows the pitch of the page buffers 902a to 902d in the X direction to be four times the pitch of the bit lines 901a to 901d, this figure is merely an example for illustrative purposes. The actual scale is determined by the actual layout dimensions and technology. For example, if the X pitch of the page buffers 902a to 902d is 32 times the X pitch of the bit lines 901a to 901d, the number of page buffers along the Y direction will become 32 instead of 4.

FIG. 34B illustrates an embodiment of a page buffer and bit line connections according to the present invention. This embodiment shows bit line select gates 904 a-904 d. The bit line select gate 904a connects the bit lines 901a to 901d to the page buffer 902 a. The bit line select gate 904d connects the bit lines 901m to 901p to the page buffer 902 d. By using this structure, the number of bit lines that can be read and written simultaneously increases by a factor of 4. This improves data throughput by a factor of 4.

Also, because the bit line length is reduced to 1/4, the bit line capacitance is reduced to 1/4. Therefore, the bit line discharge time, which is dominant in the read time of the read operation and the program verify operation, can be roughly reduced to about 1/4. If the X pitch of the page buffer is 32 times that of the bit lines, data throughput can be increased by a factor of 32. The read and program verify times can be roughly reduced to about 1/32.

Fig. 34C shows another embodiment of the page buffer and bit line connection of the embodiment shown in fig. 33A to 33C. In the present embodiment, a first group of bit lines 901a to 901d is connected to a page buffer 902a through a bit line select gate 904 a. A second group of bit lines 901e through 901h are connected to a page buffer 902a through a bit line select gate 904 b. The bit line length for this embodiment is 1/2 the bit line length for the embodiment shown in FIG. 34B.

Fig. 35 shows an exemplary Vt distribution of a three-layer cell TLC. As shown, the cells have eight Vt levels, Vt 0-Vt 7, representing three bits of data, D0-D2. The D0 through D2 bits of a cell may belong to three pages: page 0 through page 2. These three pages of data can be read independently.

As illustrated in fig. 35, black bars indicate word line voltage levels for reading respective bits. To read the D0 bit of the cell, voltages VR1 and VR5 are sequentially supplied to the selected word line. The unselected word lines are supplied with a bypass voltage VPAS higher than Vt7 to turn on all other unselected cells on the NAND cell string.

When VR1 is applied, the Vt0 cell will turn on and the Vt 1-Vt 7 cells will turn off. When VR5 is applied, the Vt 0-Vt 4 cells will turn on and the Vt 5-Vt 7 cells will turn off. Then, the control logic performs an exclusive or (XOR) function on the two data read out by VR1 and VR5 to determine the D0-bit data.

Similarly, to read the D1 bit, voltages VR2, VR4, and VR6 are supplied to the selected word line in sequence. The control logic performs an exclusive-or function on the three data read by VR2, VR4, VR6 to determine the D1-bit data.

Similarly, to read D2 bit, voltages VR3 and VR7 are supplied to the selected word line in sequence. The control logic performs an exclusive or function on the two data read by VR3 and VR7 to determine the D2 bits of data.

In an embodiment, the page buffer has three data latches to store two data read out for the D0 and D2 bits and three data read out for the D1 bit. Thus, the data stored in the data latches may be used to perform an exclusive-or function to generate the final data of the D0-D2 bits.

The data allocation shown in FIG. 35 is exemplary and not limiting, as there are many other ways to allocate the D0 through D2 bits. The various embodiments may be adapted or modified to accommodate virtually any data distribution. In an embodiment, the TLC cell may be read by using one data latch in the page buffer.

FIG. 36 shows an embodiment of a unit latch page buffer circuit according to the present invention. A data latch 918 (comprising two inverters with Q and QB nodes) stores data in the Q node. The biasing device 910 is connected to the bit line BL. Pre-power-up device 911 is connected to sense node SA. A latch bypass gate 912 is also included. A reset device 913 and a set device 914 are provided for latch 918. The gate of sensing device 915 is connected to the SA node.

FIG. 37A illustrates a method for reading the D0 bit using the unit latch page buffer shown in FIG. 36. In various embodiments, a control unit or state machine located on the same integrated circuit as the memory array generates the various control signals shown in fig. 36 and 41A. In step 920a, the Q node of data latch 918 is reset to data 1(VDD) by turning on devices 913 and 915, as shown by dashed line 916. The sense device 915 turns on by turning on the pre-power-up device 911 to pull the SA node up to VDD. In step 920b, VR1 is supplied to the selected word line to read the cells coupled to the Bit Line (BL). If the cell is an off cell, the sense node SA will be pulled high and the sensing device 915 will be turned on, as indicated by the dashed line 919. In step 920c, a SET pulse will be applied to the SET device 914 to SET (or flip) the Q node of the latch to data 0(0V), as shown by dashed line 917. If the cell is a turned-on cell, sense node SA will be pulled low and sense device 915 will be turned off, as indicated by dashed line 919, so the Q node of the latch will remain at DATA 1 (VDD). Referring to FIG. 37D, as shown in STEP 1, when voltage VR1 is applied to the selected word line, the Vt0 cell will turn on, while the Vt 1-Vt 7 cell will turn off. Thus, the previously described operation sets the latches of the Vt0 cell to DATA 1 and the latches of the Vt 1-Vt 7 cell to DATA 0.

Referring again to FIG. 37A, in step 920d, VR5 is supplied to the selected word line to read the cell. If the cell is an off cell, sense node SA will be pulled high and sense device 915 will be turned on. A RES pulse will be applied to reset device 913 to reset (or flip) the Q node of the latch to data 1(VDD), as shown in step 920 e. If the cell is an on cell, sense node SA will be pulled low and sense device 915 turned off, so the data at the Q node will remain unchanged. Referring again to FIG. 37D, as shown in STEP 2, when voltage VR5 is applied to the selected word line, the Vt 0-Vt 4 cells will turn on, while the Vt 5-Vt 7 cells will turn off. Thus, the previously described operation resets the latches of the Vt 5-Vt 7 cells to DATA 1, while the data of Vt 0-Vt 4 remain unchanged. As a result, the D0 bit data shown in fig. 35 is successfully read by using a single data latch.

FIG. 37B illustrates an exemplary method for reading the D1 bit using the single latch page buffer shown in FIG. 36. In step 921a, the Q node of data latch 918 is reset to data 1(VDD) by turning on devices 913 and 915, as shown by dashed line 916. In step 921b, VR2 is supplied to the selected word line to read the cell. If the cell is an off cell, sense node SA will be pulled high and sense device 915 will be turned on. A SET pulse will be applied to the SET device 914 to SET the Q node of the latch to data 0(0V), as shown in step 921 c. If the cell is a turned-on cell, sense node SA will be pulled low and sense device 915 will be turned off, so the Q node of the latch will remain at DATA 1 (VDD). Referring to FIG. 37E, as shown in STEP 1, when VR2 is applied to the selected word line, the Vt0 and Vt1 cells will be on, while the Vt 2-Vt 7 cells will be off. Thus, the previously described operation sets the latches for the Vt0 and Vt1 cells to DATA 1 and the latches for the Vt 2-Vt 7 cells to DATA 0.

Referring again to FIG. 37B, in step 921d, VR4 is supplied to the selected word line to read the cell. If the cell is an off cell, sense node SA will be pulled high and sense device 915 will be turned on. A RES pulse will be applied to reset device 913 to reset the Q node of the latch to data 1(VDD), as shown in step 921 e. If the cell is an on cell, sense node SA will be pulled low and sense device 915 turned off, and the data at node Q will remain unchanged. Referring again to FIG. 37E, as shown in STEP 2, when VR4 is applied to the selected word line, the Vt 0-Vt 3 cells will turn on, while the Vt 4-Vt 7 cells will turn off. Thus, the previously described operation resets the latches of the Vt 4-Vt 7 cells to DATA 1 while the data of Vt 0-Vt 3 remain unchanged.

Referring again to FIG. 37B, in step 921f, VR6 is applied to the selected word line to read the cell. If the cell is an off cell, sense node SA is pulled high and will turn on sense device 915. A SET pulse will be applied to the SET device 914 to SET the Q node of the latch to data 0(0V), as shown in step 921 g. If the cell is an on cell, sense node SA will be pulled low and sense device 915 turned off, and the data at node Q will remain unchanged. Referring to FIG. 37E, as shown in STEP 3, when VR6 is applied to the selected word line, the Vt 0-Vt 5 cells will turn on, while the Vt 6-Vt 7 cells will turn off. Thus, the previously described operation resets the latches of the Vt 6-Vt 7 cells to DATA 0, while the data of Vt 0-Vt 5 remain unchanged. As a result, the D1 bit data shown in fig. 35 is successfully read by using a single data latch.

FIG. 37C illustrates an exemplary method for reading the D2 bit using the single latch page buffer shown in FIG. 36. The operation is substantially the same as fig. 37A except that the word line voltages applied in steps 922b and 922d are VR3 and VR7, respectively. For simplicity, the description can be made with reference to fig. 37A, and the description is omitted here.

FIG. 38A illustrates an embodiment of waveforms illustrating a signal to read D0 bits using the single latch page buffer circuit shown in FIG. 36, in accordance with the present invention. The waveforms from time T1 to T5 illustrate the operations of steps 920a to 920c shown in fig. 37A. The waveforms from time T5 to T8 illustrate the operation of steps 920d and 920e in FIG. 37A.

At time T1, the PREB signal goes low to turn on the pre-power-up device 911. This will pull the SA node high and turn on the sensing device 915. The RES pulse goes high to reset the Q node of the latch to data 1 (VDD). At the same time, the BIAS signal goes high to VDD or Vpre to pre-power up the bit lines BL to VDD-Vt or Vpre-Vt. Vt is the threshold voltage of the biasing device 910.

At time T2, the PREB signal goes high to VDD to turn off the pre-power device 911 or to voltage Vref to provide the load current from the pre-power device 911. The loading current may be lower than the current to turn on the cell. The selected word line WL is supplied with a first read voltage VR 1. This will turn on the Vt0 cell and begin discharging the bit line BL as shown. The Vt 1-Vt 7 cells will remain open so their bit lines will not discharge. The BIAS voltage is lower than the voltage Vbias. This will turn off the biasing device 910.

When the bit line discharges below Vbias-Vt, the biasing device 910 will turn on to discharge the SA node, as shown at time T3. In another embodiment, the BIAS signal goes to 0V at time T2 to turn off the BIAS device 910 and goes to Vbias or VDD at time T3 to turn on the BIAS device 910. This will discharge the SA node to the BL voltage. In another embodiment, the voltage Vbias-Vt is designed to be lower than the threshold voltage of sensing device 915. Thus, for the on cell, the sense device 915 would be turned off. Conversely, for an off cell, the BL and SA nodes will remain high, and therefore sense device 915 is turned on. At time T4, a SET pulse is applied to the SET device 914 to SET the data latch Q of the open cell to data 0 (0V). The data latch of the on cell will remain at data 1 (VDD). Steps 920a to 920c shown in fig. 37A are completed.

At time T5, the PREB signal goes low again to turn on pre-power-on device 911. The BIAS signal goes to VDD or Vpre to pre-power up the bitlines to VDD-Vt or Vpre-Vt. At time T6, the PREB signal goes high to VDD to turn off the pre-power device 911 or to voltage Vref to provide the load current from the charging device 911. The selected word line WL is supplied with a second read voltage VR 5. This will turn on the Vt 0-Vt 4 cells and begin discharging the bit lines. The Vt 5-Vt 7 cells will remain open so their bit lines will not discharge.

When the bit line discharges below Vbias-Vt, the biasing device 910 will turn on to discharge the SA node, as shown at time T7. In another embodiment, the BIAS signal goes to 0V at time T6 to turn off the BIAS device 910 and goes to Vbias or VDD at time T7 to turn on the BIAS device 910. This will discharge the SA node to the BL voltage and turn off sense device 915. For off cells, both the BL and SA nodes will remain high, so device 915 is turned on. At time T8, a RES pulse is applied to the reset device 913 to reset the data latch Q of the off cell to data 1 (VDD). The data latch of the turned-on cell will remain unchanged. Steps 920d to 920e shown in fig. 37A are completed.

FIG. 38B is an embodiment of waveforms illustrating signals for reading the D1 bit using the single latch page buffer circuit shown in FIG. 36. Operation is similar to reading the D0 bit, except that three voltages VR2, VR4, and VR6 are sequentially supplied to the selected word line. During the time intervals T1 to T5, steps 921a to 921c in fig. 37B are performed. During time intervals T5-T9, steps 921 d-921 e in FIG. 37B are performed. During the time intervals T9 to T12, steps 921f to 921g in fig. 37B are performed.

Fig. 39 shows another embodiment of the page buffer circuit according to the present invention. The illustrated page buffer includes three data latches 918 a-918 c. The three data latches store three data Q [0] to Q [2 ]. The data latches are reset and set by signals R0 through R2 and S0 through S2, respectively. The page buffer circuit is connected to three bit lines BL [0] to BL [2] through bit line select gates 924a to 924 c.

During programming, signals P0 through P2 and BSG [0] through BSG [2] are sequentially turned on to apply program data from Q [0] through Q [2] to bit lines BL [0] through BL [2], respectively.

During a read operation, signals BSG [0] to BSG [2] are sequentially turned on to connect bit lines BL [0] to BL [2] to the sense node SA, respectively. Sense node SA will turn device 915 on or off depending on the voltages of BL [0] to BL [2 ]. The reset and set pulses R0 through R2 and S0 through S2 will be applied to reset or set the corresponding data latches, respectively.

FIG. 40 shows an embodiment of waveforms illustrating signals to read bit D0 from bit lines BL [0] to BL [2] using the page buffer circuit shown in FIG. 39. Operation is similar to FIG. 38A, except that during times T1-T2, BSG [0] to BSG [2] are turned on together to pre-power BL [0] to BL [2 ]. During time T2-T3, a first read voltage VR1 is supplied to the selected word line. BSG [0] to BSG [2] are turned off to allow BL [0] to BL [2] to be discharged simultaneously from the turned-on cells. During times T3-T5, BSG [0] to BSG [2] are sequentially turned on to connect BL [0] to BL [2] to the SA node, respectively. Corresponding set pulses S0 through S2 are applied to set the data latches Q [0] through Q [2] of the open cells to data 0 (0V). As a result, steps 920a to 920c shown in fig. 37A are completed.

From time T5 to T6, BSG [0] to BSG [2] are turned on to pre-power BL [0] to BL [2] again. During times T6-T7, a second read voltage VR5 is supplied to the selected word line. BSG [0] to BSG [2] are turned off to allow BL [0] to BL [2] to be discharged simultaneously from the turned-on cells. During times T7-T8, BSG [0] to BSG [2] are sequentially turned on to connect BL [0] to BL [2] to the SA node, respectively. Corresponding reset pulses R0 through R2 are applied to reset the data latches Q [0] through Q [2] of the open cells to data 1 (VDD). As a result, steps 920d and 920e shown in fig. 37A are completed.

In an embodiment, operations similar to those shown in FIG. 40 may be applied to read the D1 and D2 bits from BL [0] to BL [2 ]. When reading the D1 bit, as shown in fig. 38B, three voltages VR2, VR4, and VR6 may be sequentially supplied to the selected word line. When reading the D2 bit, the operation is similar to fig. 40, except that the voltages VR3 and VR7 are sequentially supplied to the selected word line.

By using the novel methods and apparatus described herein, the number of data latches in the page buffer can be reduced to 1/3 while maintaining the same data throughput. This allows the array to have more "planes" to further increase data throughput and reduce read latency due to shorter bit line lengths resulting in shorter bit line discharge times.

It should be noted that although the embodiments exemplify TLC, the same method can be applied to any number of multi-layer cells, e.g., MLS, QLC, etc. For example, for an MLC, the page buffer may contain two data latches to read from two bit lines simultaneously. For QLC, the page buffer may contain four data latches to read data from four bit lines simultaneously.

FIG. 41A illustrates an exemplary alternative embodiment of the page buffer circuit shown in FIG. 36 implemented using complementary logic. In this embodiment, the set and reset devices 933, 934 and 935 change from NMOS transistors to PMOS transistors and the power level connected to device 935 changes from 0V to VDD. Thus, the operation of the circuit will become to flip the latch 938 using the on cell condition instead of the off cell condition.

Fig. 41B to 41D show exemplary methods and diagrams associated with the operation of the page buffer circuit shown in fig. 41A.

Fig. 41B illustrates an exemplary method for reading D1 bits using the page buffer circuit shown in fig. 41A. In this embodiment, the selected word line voltage is changed from ramping up to ramping down from VR6, VR4 to VR2 as shown in steps 941b, 941d, and 941 f.

In step 941a, the latch is reset to data 0 by turning on devices 933 and 940. Device 940 pulls the SA node to 0V to turn on device 935 to pull node QB to VDD.

In step 941b, a read voltage VR6 is supplied to the selected word line. If the cell is a turned-on cell, it will discharge the bit line and sense node SA as shown by dashed line 939. When sense node SA discharges below VDD-Vt, device 935 will be turned on.

In step 941c, a SETB pulse is applied to device 934 to set the Q node of the latch to data 1 (VDD). If the cell is a disconnected cell, the sense node SA will be pulled high to VDD, which will turn off the device 935, so the Q node of the latch will remain at DATA 0 (0V).

Referring to FIG. 41D, as shown in STEP 1, when VR6 is applied to the selected word line, the Vt 0-Vt 5 cells will turn on, while the Vt 6-Vt 7 cells will turn off. Thus, the latch data for Vt 0-Vt 5 will be set to 1, while the latch data for Vt6 and Vt7 will remain at 0.

In step 941d, VR4 is supplied to the selected word line. Turning on the cell will discharge the bitline and sense node SA below VDD-Vt to turn on device 935, while turning off the cell's sense node SA will be pulled up to VDD to turn off device 935.

In step 941e, a RESB pulse is applied to device 933 to reset the Q-node of the on cell of the latch to data 0(0V) while the Q-node of the off cell of the latch remains unchanged.

Referring to FIG. 41D, as shown in STEP 2, when VR4 is applied to the selected word line, the Vt 0-Vt 3 cells will turn on, while the Vt 4-Vt 7 cells will turn off. Thus, the latch data of Vt 0-Vt 3 will be set to 0, while the latch data of Vt 4-Vt 7 will remain unchanged.

In step 941f, VR2 is supplied to the selected word line. Turning on the cell will discharge the bitline and sense node SA below VDD-Vt to turn on device 935, while turning off the cell's sense node SA will be pulled up to VDD to turn off device 935.

In step 941g, a SETB pulse is applied to device 934 to reset the Q-node of the on cell of the latch to data 1(VDD) while the Q-node of the off cell of the latch remains unchanged.

Referring to FIG. 41D, as shown in STEP 3, when VR2 is applied to the selected word line, the Vt0 and Vt1 cells will be on, while the Vt 2-Vt 7 cells will be off. Thus, the latch data for Vt0 and Vt1 will be set to 1, while the latch data for Vt2 to Vt7 will remain unchanged.

As a result, the D1 data shown in fig. 35 was successfully read by using a single data latch. Also, similar operations may be used to read the D0 and D2 bits. For simplicity, the detailed operations for reading the D0 and D2 bits are not described here.

Fig. 41C shows a waveform diagram for reading D1 bits used with the circuit of fig. 41A in the present embodiment. The waveforms in fig. 41C are similar to those shown in fig. 38B, except that the word line voltages are ramped down from VR6, VR4 to VR2 instead of ramping up, and the data latches are initially reset to data 0(0V) instead of data 1 (VDD). Also, a DIS signal of the control device 940 is shown in fig. 41A. The page buffer circuit shown in fig. 41A is applicable to a page buffer circuit implementing a 3-bit data latch, as shown in fig. 39, and operates by using a ramp down instead of a ramp up of the word line voltage on the waveform shown in fig. 40.

Fig. 42A to 42B show graphs providing word line voltage levels for reading various types of multi-layered cells using a unit latch according to the present invention. For example, fig. 42A shows a diagram for reading a multi-level cell (MLC). Fig. 42B shows a diagram for reading a four-layer cell (QLC). The black bars indicate the word line voltage levels used to read the individual bits. For example, referring to fig. 42A, to read D0, the word line voltage VR2 is used, while to read D1, the word line voltages VR1 and VR3 are used.

When reading data, bits D0, D1, D2 are read independently. For example, if the system only needs to read D2 data from the cells shown in FIG. 35, then the D2 data is read using the operations shown and described with reference to FIG. 37C. The data of D0 and D1 were not read. Thus, a general process flow may be implemented to read any one or more data bits with the word line voltage levels shown.

It should be noted that the data allocation of the multi-level cells is not limited to one configuration. Thus, read operations are configured according to data allocation.

Fig. 42C-42F show four exemplary configurations for assigning D0-D2 to TLC. It is assumed that the page buffer circuit shown in fig. 36 is used to realize the TLC reading operation. A configuration is shown in FIG. 42C, where D0-D1 data of Vt0 is assigned a 1. Thus, data can be read by setting the initial data of latch 918 to 1, applying a ramping word line voltage, and then toggling the data of the off cell for each word line voltage level. The ramped word line voltages for reading D0 are VR3, VR 7; the ramped word line voltages for reading D1 are VR2, VR4, VR 6; the ramped word line voltages for reading D2 are VR1, VR 5.

FIG. 42D shows a configuration where D0-D1 data of Vt0 is assigned a 0. Thus, data can be read by setting the initial data of latch 918 to 0, applying a ramping word line voltage, and then toggling the data of the off cell for various word line voltage levels. The ramping word line voltage is the same as in fig. 42C.

FIG. 42E shows another configuration in which D0-D1 data of Vt7 is assigned a 1. Thus, data can be read by setting the initial data of latch 918 to 1, applying a ramp down wordline voltage, and then toggling the data of the on cell for each wordline voltage level. The ramped word line voltage for reading D0 is VR7, then VR 3; the ramped word line voltage for reading D1 is VR6, VR4, then VR 2; the ramped word line voltage for reading D2 is VR5, then VR 1.

FIG. 42F shows a configuration in which D0-D1 data of Vt7 is assigned a 0. Thus, data can be read by setting the initial data of latch 918 to 0, applying a ramp down wordline voltage, and then toggling the data of the on cell for each wordline voltage level. The ramping word line voltage is the same as in fig. 42E.

FIG. 43 illustrates an exemplary method 4300 for reading bits in a multi-level cell using a unit latch according to the present invention. For example, the method is suitable for reading a multi-level cell using the unit latch circuit shown in fig. 36.

At block 4302, one or more bits to read from the multi-layer cell are identified. For example, the bits D0, D1, and D2 as illustrated in fig. 35 are identified as to be read.

At block 4304, word line voltage levels to be used for reading the respective identified bits are identified. For example, the word line voltage level shown in fig. 35 is identified to read the bits D0, D1, and D2. For example, to read D0, word line voltage levels VR1 and VR5 are identified. To read D1, word line voltage levels VR2, VR4, and VR6 are identified, and to read D2, word line voltage levels VR3 and VR7 are identified.

At block 4306, a bit to be read is selected. For example, the bit D0 is selected for reading.

At block 4308, a first word line voltage level is selected for reading the selected bit. For example, word line voltage level VR1 is selected to read bit D0, as illustrated in FIG. 35.

At block 4310, the latch output of the unit latch is set to an initial level. For example, as shown in fig. 36, the Q output of latch 918 is set to an initial value of 1.

At block 4312, the selected word line level is applied to the cell. For example, word line voltage level VR1 is applied to read the cell.

At block 4314, if the cell is determined to be a broken cell, the output of the cell is read out and the latch is flipped. For example, as illustrated in fig. 36, the output of the cell is read out at the SA node. If the cell is a disconnect cell, the Q output of the latch is flipped. For example, the Q output of latch 918 is flipped to a value of 0 by the RES signal. It should also be noted that in another embodiment, the latch circuit may be implemented using complementary logic as shown in FIG. 41A, and in this case, the latch is flipped when the cell is a turned-on cell.

At block 4316, it is determined whether there are more word line voltage levels to apply to the cell to read the selected bit. If there are more word line voltage levels to apply, the method proceeds to block 4318. If there are no more word line voltage levels to apply, the method proceeds to block 4320. In this example, to read D0, the next word line voltage level VR5 would be applied to the cell. The method then proceeds to block 4318 to apply the voltage level to the cell and process the read result.

At block 4318, the next word line voltage level to apply is selected. The method then proceeds to block 4312. It should be noted that when the method returns to block 4314, if the cell is a disconnect cell, the Q output of latch 918 is again flipped to a value of 1 by the SET signal. Thus, each adjustment flips (or switches) the output of latch 918.

At block 4320, a latch holds the value of the data bit. For example, latch 918 holds the value of the selected data bit because no more word line voltage levels are applied to the cell.

At block 4322, it is determined whether there are more data bits to read from the cell. If there are more data bits to read, the method proceeds to block 4306. If there are no more data bits to read, the method ends. For example, to read the D1 bits, the method proceeds to block 4306 to select the bit to read. The above operation is performed again to read the D1 bit. The method will again return to block 4306 to again perform the operations described above to read D2 bits. After reading bit D2, the method ends.

Thus, method 4300 operates to read bits in a multi-level cell using a unit latch according to the present invention. It should be noted that the operations provided are exemplary, and additions, deletions, alterations, and/or modifications are within the scope of the embodiments.

In various exemplary embodiments, methods and apparatuses are provided for storing program and read data using bit line capacitances and loading and reading data using page buffers to increase data throughput. However, since the bit line capacitance takes time to charge and discharge, the I/O bus may use a slower clock rate to ensure that the data is loaded correctly when the data is loaded directly into the bit line capacitance. This may slow down the I/O bus speed.

Fig. 44A-44B illustrate an exemplary array structure and data loading and output sequence in accordance with the present invention.

Fig. 44A shows an exemplary architecture including the memory cell array 101 and the page buffer block 103 including the page buffers 207a to 207 m. The architecture also includes bit line select gates 106 that connect the page buffer to bit lines BLa [0: n ] through BLm [0: n ]. An I/O bus 600 having a bandwidth from 8 bits to 64 bits is shown.

FIG. 44B shows a data loading sequence for the circuit shown in FIG. 44A. The bit line select gate signals BSG [0: n ] are sequentially turned on to load data from I/O bus 600 to BLA [0] to BLm [ n ], respectively. During time T1, signal BSG [0] goes high to select BLa [0] through BLm [0] to be coupled to page buffers 207a through 207m, respectively. Data is sequentially loaded from the I/O bus 600 to PAGE buffers 207a to 207m, and then to BLA [0] to BLm [0], defined as Page [0 ]. Assuming a 4KB page buffer, the I/O bus width is 1 byte. Also assume that the I/O bus clock period is 10 ns. The 4KB data is loaded from the I/O bus 600 into the 4KB page buffer 106, then from the first byte of data to the last byte into BLA [0] to BLm [0 ]. Each byte takes 10ns, so the time interval T1 to load a 4KB page would be 40 microseconds (us). This time is far enough for loading the first byte of data into the bit line. However, the last byte of data is only 10ns to load onto the bit line before signal BSG [0] goes low. This may not have enough time to load the last byte of data into the high capacitance bit line and thus the load data operation may fail.

For the output data, the same waveform as that shown in fig. 44B may be used. During the time interval T1, signal BSG [0] selects BLa [0] through BLm [0] to connect to page buffers 207a through 207 m. At the same time, the I/O bus outputs data from the page buffers 207a to 207 m. Similarly, the read data from the bit line to the I/O bus is only 10ns for the last byte. The short time to read the last byte may not be sufficient and thus the output data operation may fail.

To solve the above problem, one solution is to delay the time that BSG [0] goes low. However, this reduces the I/O speed and is therefore not preferred. Another technique is to add additional data registers, shown as 104a through 104d in fig. 1A. However, this increases the die size.

Fig. 45A to 45C show an exemplary array structure and data loading and output sequence according to the present invention.

FIG. 45A illustrates an exemplary architecture according to the present invention. ARRAY 101 is divided into two subarrays, ARRAY 1101 a and ARRAY 2101 b. ARRAY1 and ARRAY2 are connected to page buffer blocks 103a and 103b through bit line select gate blocks 106a and 106b, respectively. The bit line select gate blocks 106a and 106b are connected to different select gate signals BSG1[0: n ] and BSG2[0: n ], respectively. The page buffer blocks 103a and 103b are connected to the I/O bus 600.

FIG. 45B illustrates an exemplary data loading sequence for use with the architecture shown in FIG. 45A. Signals BSG1[0: n ] and BSG2[0: n ] are interleaved as shown. The I/O bus 600 alternately loads data to the page buffer blocks 103a and 103 b. For example, during time interval T1, the I/O bus loads the first page data (PG1[0]) into the first page buffer block 103 a. Then, the page buffer 103a loads data to the bit line selected by BSG1[0 ]. During time interval T2, the I/O bus loads the second page data (PG2[0]) into the second page buffer block 103 b. Meanwhile, since the signal BSG1[0] is always high, the first page buffer block 103a continues to load the first page data to the bit line selected by BSG1[0 ]. As a result, the problem of insufficient load time of the last data byte shown in fig. 44A to 44B is eliminated.

Assume that page buffer blocks 103a and 103b are each 2KB page buffers. At the same I/O bandwidth and clock rate as the example shown in fig. 44A-44B, the length of time interval T2 is 20 microseconds (us), which is far enough for loading the last byte of the first page buffer 103a onto the bit line. As a result, the load time problem shown in fig. 44A to 33B is solved. Also, the clock rate of the I/O bus may be increased to increase the data transfer rate.

FIG. 45C shows the data output sequence of the embodiment shown in FIG. 45A. During time interval T3, signal BSG1[0] goes high to select the bit line in ARRAY1 to connect to first page buffer block 103a to read the first page data (PG1[0 ]). During time interval T4, signal BSG2[0] goes high to select the bit lines in ARRAY2 to connect to the second page buffer block 103b to read the second page data (PG2[0 ]). During the same time interval T4, the I/O bus outputs the first page data from the page buffer block 103 a.

With the same I/O bandwidth and clock rate shown in FIG. 45B, the T3 time period is 20 microseconds (us) long, which is sufficient to read data from the bit lines to the page buffer. As a result, the problem of the output operation shown in fig. 44B is solved. Also, the clock rate of the I/O bus may be increased to increase the data transfer rate.

Fig. 46A to 46C show an exemplary array structure and data loading and output sequence according to the present invention.

FIG. 46A illustrates another embodiment of an exemplary architecture according to the present invention. In this embodiment, the ARRAY is further divided into four sub-ARRAYs, ARRAY 1101 a through ARRAY 4101 d. The four sub-arrays are connected to four page buffer blocks 103a to 103d through four bit line select gate blocks 106a to 106d, respectively. The bit line select gate blocks 106 a-106 d are controlled by four sets of select gate signals BSG1[0: n ] and BSG4[0: n ], respectively.

FIG. 46B illustrates a data loading sequence for use with the architecture shown in FIG. 46A. The sets of select gate signals BSG1[0: n ] through BSG4[0: n ] for bit line select gate blocks 106 a-106 d are staggered as shown. During the time interval T1, the first page data is loaded to the first page buffer block 103 a. During time interval T2, the first page of data continues to be loaded onto the bit line selected by signal BSG1[0 ]. The time intervals T1 and T2 are 10 microseconds (us) and 30 microseconds (us), respectively, according to the I/O width and clock rate shown in fig. 44B. Thus, for this embodiment, the data has more time to load into the bit line capacitance. In addition, the I/O clock rate can be further increased to increase the data transfer rate.

FIG. 46C shows an output data sequence for use with the architecture shown in FIG. 46A. During time interval T3, the first page data is read from the bit line selected by BSG1[0] to first page buffer block 103 a. During time interval T4, the first page data is output from page buffer block 103a to the I/O bus. Time intervals T3 and T4 are 30 microseconds (us) and 10 microseconds (us), respectively. Therefore, for this embodiment, there is more time for data to be read from the bit lines to the page buffer. In addition, the I/O clock rate can be further increased to increase the data transfer rate. In various exemplary embodiments, the number of sub-arrays used is not limited, for example, the number of sub-arrays may be 2, 4, 8, 16, or any suitable number.

In various example embodiments, during a program operation, program data is loaded to a plurality of bit lines and stored in bit line capacitances to perform the program operation. If the inhibit Voltage (VDD) on the bit line leaks below VDD-Vt, the Drain Select Gate (DSG) of the selected string may be turned on, causing the inhibit voltage (8V) stored in the channel of the string to leak to the bit line. As a result, the inhibited cells may be accidentally programmed.

Referring to fig. 5A, the time interval of the program pulse (Tpgm) is about 10us to 30 us. The bit line capacitance is about 1pF to 5 pF. If the leakage current is higher than 20nA, it may leak the bitline voltage from VDD to below VDD-Vt during the program pulse interval. Typically, the junction leakage current of the bit line is much less than 20 nA. However, when the bit line length is reduced, the bit line capacitance is reduced, and the margin becomes small.

To address this issue, a "refresh" operation may be performed to maintain the bit line voltage. Referring to the circuit shown in FIG. 6F, during a program operation, program data is stored in the bit line capacitances 206a through 206 n. To maintain the voltages of the bit line capacitances 206a to 206n, a refresh operation may be performed to sequentially turn on the bit line select gates 202a to 202n to connect the page buffer 200 to the bit lines 201a to 201n, respectively, so as to sense the selected bit line voltages and restore the voltages to the full VDD or 0V level using the sense amplifier 208.

Fig. 47A to 47B illustrate embodiments of waveforms for a refresh operation according to the present invention. The supplied waveforms are discussed with reference to the detailed page buffer circuit shown in fig. 3C.

Fig. 47A shows an operation for refreshing the bit line storing the inhibited data 1 (VDD). Assume that the Bit Line (BL) has leakage and the voltage drops to VDD-dV, where dV is the angle junction (delta) voltage below Vt. At time T0, 0V is supplied to both the preboot and BIAS signals to turn on the pre-power-up device 303 and turn off the BIAS device 306 to charge the SA node to VDD. At time T1, a SET pulse is applied to SET the Q node of latch 207 to 0V. At time T2, Vbias is supplied to the BIAS signal to turn on BIAS device 306 for sensing the BL voltage. PREB is supplied with Vref to limit the pull-up current of pre-power-up device 303. Because the BL voltage is higher than Vbias-Vt, the biasing device 306 is turned off, while the SA node holds VDD to turn on the sensing device 310. At time T3, a RES pulse is applied to turn on the reset device 312. This resets the Q node of latch 207 to VDD because sense device 310 is turned on. At time T4, the VDD + Vt pulse is supplied to the PGM, BIAS, and PREB signals. This will turn on the bypass gate 220 and the biasing device 306, respectively, and turn off the pre-power-up device 303. BL will be charged from VDD-dV to VDD by the Q node of latch 207. Thus, the refresh operation of the selected bit line is completed. At time T5, the current bit line select gate (BSG) is turned off and the next bit line select gate (BSG) may be turned on to repeat the operations at times T0 through T5 to refresh the next bit line.

Fig. 47B shows an operation for refreshing the bit line storing the program data 0 (0V). Assume that the Bit Line (BL) has leakage and the voltage increases to dV, where dV is the corner-to-corner (delta) voltage below Vt. At time T0, 0V is supplied to both the preboot and BIAS signals to turn on the pre-power-up device 303 and turn off the BIAS device 306 to charge the SA node to VDD. At time T1, a SET pulse is applied to reset the Q node of latch 207 to 0V. At time T2, Vbias is supplied to BIAS to turn on BIAS device 306 for sensing the BL voltage. PREB is supplied with Vref to limit the pull-up current of pre-power-up device 303. Since the BL voltage is lower than Vbias-Vt, the biasing device 306 is turned on and pulls the SA node down to the same voltage as BL. Since the SA voltage is below Vt, it turns off sensing device 310. At time T3, a RES pulse is applied to turn on the reset device 312. However, because sensing device 310 is turned off, the Q node of latch 207 will remain at 0V. At time T4, the VDD + Vt pulse is supplied to the PGM, BIAS, and PREB signals. This will turn on the bypass gate 220 and the biasing device 306, respectively, and turn off the pre-power-up device 303. BL will be discharged from dV to 0V by the Q node of latch 207. As a result, the refresh operation of the selected bit line is completed. At time T5, the current bit line select gate (BSG) is turned off and the next bit line select gate (BSG) may be turned on and the operations at times T0 through T5 are repeated to refresh the next bit line.

In the above embodiment, VDD is used as the inhibit voltage. In another embodiment, the inhibit voltage may be VDD-Vt. In this case, at time T4, when the pulses are applied to signals PGM, BIAS and PREB, the pulses may be at the VDD level, which charges BL to VDD-Vt.

Fig. 47A to 47B illustrate an embodiment of a refresh operation according to the present invention. The frequency of the refresh operation depends on the bitline capacitance and bitline leakage current. The refresh operation may be repeatedly performed during the entire program pulse to refresh all selected bit lines.

While exemplary embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, that changes and modifications may be made without departing from exemplary embodiments and their broader aspects. Therefore, the appended claims are intended to encompass within their scope all such changes and modifications as are within the true spirit and scope of the exemplary embodiments of this invention.

Claims (19)

1. A method for programming a NAND flash memory, wherein the NAND flash memory includes a string of memory cells coupled to a bit line and a word line, the method comprising:

programming the selected memory cell by applying a program voltage to the selected bit line and applying an inhibit voltage to the unselected bit line;

the programming operation is verified by:

pre-powering up the selected bit line with a bias voltage level while the unselected bit lines maintain the inhibit voltage;

applying a verify voltage to a selected word line coupled with the selected memory cell;

discharging the selected bit line coupled to a turned-on cell for a first time interval;

sensing a sense voltage level on the selected bit line;

applying an inhibit voltage level to the selected bit line when the sensed voltage level is above a threshold level, and applying the program voltage to the selected bit line when the sensed voltage level is equal to or below the threshold level; and

repeating the sensing and applying voltage operations for each of the selected bit lines;

reprogramming a portion of the selected memory cells coupled to a bit line to which the program voltage is applied; and

repeating the verifying and the reprogramming operations until all of the selected memory cells are programmed.

2. The method of claim 1, wherein the programming voltage is 0 volts and the inhibit voltage is one of VDD or VDD-Vt.

3. The method of claim 1, wherein the bias voltage level is in a range of Vt to VDD.

4. The method of claim 1, wherein the first time interval is in a range of 1 microsecond to 30 microseconds.

5. The method of claim 1, wherein the pre-power-up operation comprises:

enabling a select gate of the bit line to selectively enable and disable the bit line;

applying the bias voltage to the selected bit line; and

the select gates are disabled to store bias voltages using bit line capacitances of the selected bit lines, respectively.

6. The method of claim 1, wherein the read out operation comprises:

enabling a select gate associated with the selected bit line; and

the selected bit line is coupled to a sensing device to determine the sensing voltage.

7. The method of claim 1, wherein the applying voltage operation comprises:

enabling a select gate associated with the selected bit line;

applying the inhibit voltage level to the selected bit line when the sensed voltage level is above the threshold level and applying the program voltage to the selected bit line when the sensed voltage level is equal to or below the threshold level; and

disabling the select gate associated with the selected bit line to store the applied voltage using a bit line capacitance.

8. A method for operating a NAND flash memory, the method comprising:

pre-powering up a selected bit line of a selected memory cell with a bias voltage level while unselected bit lines maintain an inhibit voltage;

applying a verify voltage to a selected word line coupled with the selected memory cell;

discharging the selected bit line coupled to a turned-on cell for a first time interval;

sensing a sense voltage level on the selected bit line;

applying an inhibit voltage level to the selected bit line when the sensed voltage level is above a threshold level, and applying a program voltage to the selected bit line when the sensed voltage level is equal to or below the threshold level; and

the sensing and applying voltage operations are repeated for each of the selected bit lines.

9. The method of claim 8, further comprising: programming the selected memory cell prior to the pre-power-up operation.

10. The method of claim 8, further comprising: after the sensing and applying voltage operations are completed, a portion of the selected memory cells coupled to the bit lines to which the program voltage is applied are reprogrammed.

11. A method for reading a multi-level cell NAND flash memory, wherein the NAND flash memory includes a string of memory cells coupled to a bit line and a word line and a separate bit data latch coupled to the bit line, the method comprising:

by performing the operations of:

applying a selected word line voltage level to the cell to sense an output of the cell;

flipping the latch to a first data value when the output indicates that the cell is a disconnected cell; and

repeating the applying and the flipping operations until all word line voltages are applied to the cell such that the value of the bit is stored in the latch;

to read the bits of the cells; and

the read operation is repeated for each bit of the cell to be read.

12. The method of claim 11, further comprising: initializing the latch to a second data value prior to the applying operation.

13. The method of claim 12, wherein the first data value is 0 volts and the second data value is VDD.

14. The method of claim 12, wherein the first data value is VDD and the second data value is 0V.

15. The method of claim 12, wherein the flipping operation further comprises: holding the latch unchanged when the output indicates that the cell is a turned-on cell.

16. The method of claim 12, wherein the single bit data latch is implemented using complementary logic, and wherein the flip operation comprises: when the output indicates that the cell is a turn-on cell, the latch is inverted to the first data value.

17. The method of claim 16, wherein the first data value is 0 volts and the second data value is VDD.

18. The method of claim 16, wherein the first data value is VDD and the second data value is 0V.

19. The method of claim 16, wherein the flipping operation further comprises: holding the latch unchanged when the output indicates that the cell is a broken cell.

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