CN113489565B - Multi-channel service shared channel transmission system based on synchronous time division multiplexing system - Google Patents
Multi-channel service shared channel transmission system based on synchronous time division multiplexing system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
Abstract
The invention discloses a multichannel service shared channel transmission system based on a synchronous time division multiplexing system, wherein each service end is communicated with a transmission channel through a matched FPGA and CPU; the FPGA monitors service data through the RTP of the serial port end, codes each serial port end of the FPGA to realize service coding, and further, the receiving and transmitting data of the FPGA corresponds to the RTP of the serial port end through the identification of the coding; the CPU is communicated with the FPGA through the AD bus, so that dynamic time division multiplexing of multiple paths of services and dynamic adjustment of time slot bandwidth of a transmission channel are realized according to dynamic control signals sent by the FPGA, and synchronous time division multiplexing of the transmission channel is further realized. The invention provides a multichannel service shared channel transmission system based on a synchronous time division multiplexing system, which can integrate voice, data service and Ethernet service in a synchronous transmission channel with any rate, realize multi-service integrated transmission and bandwidth sharing and improve the integration level of the communication system and the utilization rate of transmission information channel bandwidth.
Description
Technical Field
The invention relates to a management system used in the case of synchronous time division multiplexing technical data transmission. More particularly, the present invention relates to a multiple service shared channel transmission system based on a synchronous time division multiplexing system for use in synchronous time division multiplexing service transmission channel sharing to improve the utilization of transmission line bandwidth.
Background
A synchronous communication device constructed based on synchronous time division multiplexing technology is characterized in that a certain time slice of a transmission channel is fixedly occupied by one path of service signal, the transmission capacity of the communication device is often limited by the rate of the transmission channel, the rate of the transmission channel is limited by the limit rate of an electronic device and basically reaches the limit transmission rate of a TDM technical system, and thus the service capacity of the TDM technical system device is limited. With the increasing demands of service IP and large-granularity, the existing carrier network based on the synchronous transmission system is difficult to be compatible with the requirements of multi-service integrated transmission of traditional communication services such as voice, data and the like, video, images and large-granularity data/IP services such as ethernet and the like. Therefore, the comprehensive adaptability of the existing communication system to services such as IP (Internet protocol) and large granularity is improved, the bandwidth utilization efficiency of the synchronous transmission channel is improved, and the research on the synchronous time division multiplexing channel sharing technology is very necessary.
In the synchronous time division multiplexing transmission system, the service transmission fixedly occupies the time slot of the transmission channel, no matter whether the service transmission exists or not, the time slot bandwidth corresponding to the transmission channel is always occupied, and the resource waste of the transmission bandwidth is caused. How to realize the synchronous time division multiplexing service sharing transmission channel is the problem which is mainly solved by the invention.
Disclosure of Invention
It is an object of the present invention to address at least the above problems and/or disadvantages and to provide at least the advantages described below.
The invention also aims to provide a multichannel service shared channel transmission system based on the synchronous time division multiplexing system, wherein the FPGA and the CPU realize the dynamic time division multiplexing of the service multichannel and the dynamic adjustment of the time slot bandwidth of the transmission channel through a service interface state detection device and a service stream coding mechanism. The real-time shared transmission channel of the wide and narrow band service is ensured, and the transmission bandwidth is maximally utilized by the wide band service.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided a multiple service shared channel transmission system based on a synchronous time division multiplexing system, wherein each service terminal is connected to a transmission channel through a matched FPGA and CPU;
the FPGA monitors service data through the serial port RTP on the FPGA, codes each serial port end of the FPGA to realize service coding, and further, the receiving and transmitting data of the FPGA corresponds to the serial port RTP through the identification of the coding;
the CPU is communicated with the FPGA through the AD bus, so that dynamic time division multiplexing of multiple paths of services and dynamic adjustment of time slot bandwidth of a transmission channel are realized according to dynamic control signals sent by the FPGA, and synchronous time division multiplexing of the transmission channel is further realized.
Preferably, when the service end sends data, the data processing flow of the FPGA includes:
the FPGA receives service data through each serial port RTP, converts the received service data into corresponding synchronous serial codes and simultaneously generates corresponding transmission control signals;
the method comprises the steps that a sending control module TDC on an FPGA is used for comprehensively processing sending control signals received from each serial port end to form a corresponding dynamic control signal to be sent to a CPU, and further a multiplexing control signal is built to realize dynamic control of a multiplexing unit, and coding identification of service flows on each serial port end in a system is completed to generate corresponding service code flows;
dynamically multiplexing each service code stream into high-speed synchronous serial data stream to a framing/de-framing module FAMER according to multiplexing control signals received from a CPU (Central processing Unit) through a multiplexing module MUX (micro-processing Unit) on the FPGA;
the framing/de-framing module FAMER carries out framing processing and business coding information stream insertion on the received high-speed serial data stream according to the line requirement of a transmission channel so as to realize the transmission of business data through the output of the transmission channel.
Preferably, when the service end receives data, the data processing flow of the FPGA includes:
signal frame decoding is carried out on the data from the transmission channel through a framing/frame decoding module FAMER on the FPGA, and the extraction of service coding information, the extraction of service data and the conversion of code streams are completed;
processing the code stream identification signal received from the framing/de-framing module FAMER through a receiving control module RDC on the FPGA, and decomposing the code stream identification signal to obtain a receiving control signal and a de-multiplexing control signal matched with each service end;
the high-speed serial data stream sent from the framing/de-framing module FAMER is decomposed into serial service data stream by a de-multiplexing module DMUX on the FPGA, and the serial service data stream is sent to a serial port RTP;
and receiving corresponding service control signals from a receiving control module RDC through a serial port RTP on the FPGA, and converting the received serial service data stream into user service.
Preferably, after the FPGA monitors service data through the serial port RTP, bandwidth is calculated according to the service data and sent to the CPU;
and the CPU configures the multiplexing/demultiplexing strategy of the FPGA and manages the switching of the working states of the channels according to the received transmission bandwidth requirement and by combining a transmission channel time slot bandwidth slicing mechanism.
Preferably, each interface uses 1 byte as a transmission control signal, and each transmission control signal includes a service type code and an occupied bandwidth number;
wherein, bit 0-bit 4 in the corresponding byte of the control signal represents the bandwidth number required by the service, and bit 5-bit 7 represent the service type code;
when the control byte is b00000000, it indicates that the corresponding interface has no data.
Preferably, the integrated processing procedure for integrating the plurality of transmission control signals into a corresponding dynamic control signal includes: and taking a frame synchronization signal of the system as a start bit, starting from a first path of interface of the system, and combining control signals corresponding to the interfaces into a path of serial code stream in a byte-interleaved mode to serve as dynamic control signals of a system transmitting end.
Preferably, a combining process of dynamically combining each service code stream into a high-speed synchronous serial data stream is configured to include identification of a transmission control signal and service data stream multiplexing;
the method comprises the steps that a transmission control signal is identified and configured to reject non-transmission data service, and transmission bandwidth is allocated to the rest service in a system;
the service data stream multiplexing is configured to combine the service data streams to be transmitted into a high-speed synchronous serial data stream by adopting a byte interleaving mode.
Preferably, the framing processing and service coding information stream inserting method comprises the following steps: the system framing process is the same as the original synchronous framing mode, and the service coding information stream is synchronously inserted into the overhead bits of the frame signal for transmission.
Preferably, the method for configuring the transmission channel time slot bandwidth slicing mechanism comprises the following steps: and slicing the transmission channel by taking the service transmission bandwidth with the minimum bandwidth requirement in the multichannel service shared channel transmission system as a reference, and adjusting the transmission bandwidths of the rest services to be integer multiples of the reference transmission bandwidth.
The invention at least comprises the following beneficial effects: firstly, the FPGA and the CPU in the transmission system realize the dynamic time division multiplexing of the service multipath and the dynamic adjustment of the time slot bandwidth of the transmission channel through the service interface state detection device and the service stream coding mechanism. The real-time shared transmission channel of the wide and narrow band service is ensured, and the transmission bandwidth is maximally utilized by the wide band service.
Secondly, the transmission system of the invention can integrate voice, data service and Ethernet service in synchronous transmission channels with arbitrary speed, realize multi-service integrated transmission and bandwidth sharing, and improve the integration level of the communication system and the utilization rate of transmission information channel bandwidth.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
FIG. 1 is a functional block diagram of an FPGA in data communication with a CPU in one embodiment of the invention;
FIG. 2 is a block diagram of the FPGA data processing flow in another embodiment of the invention.
Detailed Description
The present invention is described in further detail below with reference to the drawings to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
Fig. 1 shows an implementation form of a multi-channel service shared channel transmission system based on a synchronous time division multiplexing system according to the present invention, where each service end 9 communicates with a transmission channel 10 through a matched FPGA 1 and CPU 2, and a service end serial port includes voice, data service and ethernet service ports;
the FPGA monitors service data through a serial port RTP 3 on the FPGA, codes each serial port end of the FPGA to realize service coding, and further, the receiving and transmitting data of the FPGA corresponds to the serial port RTP through the identification of the coding;
the CPU is communicated with the FPGA through the AD bus, so that dynamic time division multiplexing of multiple paths of services and dynamic adjustment of time slot bandwidth of a transmission channel are realized according to dynamic control signals sent by the FPGA, and synchronous time division multiplexing of the transmission channel is further realized. Specifically, the multichannel service shared channel transmission system based on the synchronous time division multiplexing system mainly comprises an FPGA and a CPU, and is realized by adopting a service coding and service channel excitation mode. Specifically, in this scheme, the CPU functions are: the functions of service type management, multiplexing/demultiplexing strategy configuration, transmission channel time slot bandwidth slicing mechanism configuration, channel working state management and the like are realized through the communication of the AD bus and the FPGA. FPGA functions: (1) the service receiving and transmitting processing module, namely a service serial port RTP 3, mainly completes the conversion from user service to synchronous serial code stream, generates a transmission control signal and calculates service bandwidth, and converts the received serial signal code stream into user service according to the received service control signal; (2) the transmission control module TDC 4 synthesizes the transmission control signals received by the service processing units into a dynamic control signal to control the dynamic multiplexing unit, and simultaneously completes the code identification of the service flows in the system; (3) the receiving control module RDC 7 processes the code stream identification signal received from the transmission line to decompose the receiving control signal and the demultiplexing control signal of each service unit; (4) the multiplexer MUX 5 dynamically multiplexes each service code stream into a high-speed synchronous serial data stream to a framing unit according to the multiplexing control signal; (5) a demultiplexer (also called as a splitter) DMUX 8 splits the high-speed serial data stream sent from the de-framing unit into serial service data streams according to the received service de-multiplexing control signal, and sends the serial service data streams to the service processing unit; (6) the framing/de-framing processing module FAMWR 6 carries out framing processing and business coding information stream insertion on the high-speed serial data stream sent by the multiplexing unit according to line requirements, and carries out signal de-framing from the receiving channel to finish business coding information extraction and business data extraction and code stream conversion. The FPGA is the key of realizing the synchronous time division multiplexing channel sharing technology, and the data processing flow is shown in figure 2, so the FPGA and the CPU in the scheme realize the dynamic time division multiplexing of service multiplexing and the dynamic adjustment of the time slot bandwidth of a transmission channel through a service interface state detection device and a service stream coding mechanism, ensure the real-time sharing of the transmission channel of wide and narrow-band services, and the wide-band service maximally utilizes the transmission bandwidth.
As shown in fig. 1, in another example, when data is sent by a service end, a data processing flow of the FPGA includes:
the FPGA receives service data through each serial port RTP 3 on the FPGA, converts the received service data into corresponding synchronous serial codes and simultaneously generates corresponding transmission control signals;
the method comprises the steps that a sending control module TDC 4 on an FPGA is used for comprehensively processing sending control signals received from each serial port end to form a corresponding dynamic control signal to be sent to a CPU, and further a multiplexing control signal is built to realize dynamic control of a multiplexing unit, and coding identification of service flows on each serial port end in a system is completed to generate corresponding service code flows;
through multiplexing module MUX 5 on FPGA, according to multiplexing control signal received from CPU, dynamically multiplexing each service code stream into high-speed synchronous serial data stream to framing/deframer module FAMER;
the framing/de-framing module FAMER 6 carries out framing processing and business coding information stream insertion on the received high-speed serial data stream according to the line requirement of a transmission channel so as to realize the transmission of business data through the output of the transmission channel. Compared with the data processing flow in the prior art, the data processing flow of the FPGA during data transmission by adopting the scheme has the beneficial effects that the maximized integration of the user service data flow and the utilization capacity of the transmission bandwidth of the broadband service maximized line are adopted, and the bandwidth of the service data flow in the transmission line is reasonably distributed.
As shown in fig. 1, in another example, when the service end receives data, the data processing flow of the FPGA includes:
signal frame decoding is carried out on the data from the transmission channel through a framing/frame decoding module FAMER 6 on the FPGA, and the extraction of service coding information, the extraction of service data and the conversion of code streams are completed;
processing the code stream identification signal received from the framing/de-framing module FAMER through a receiving control module RDC 7 on the FPGA, and decomposing the code stream identification signal to obtain a receiving control signal and a de-multiplexing control signal matched with each service end;
the high-speed serial data stream sent from the framing/de-framing module FAMER is decomposed into serial service data stream by a de-multiplexing module DMUX 8 on the FPGA, and the serial service data stream is sent to a serial port RTP;
and receiving corresponding service control signals from a receiving control module RDC through a serial port RTP 1 on the FPGA, and converting the received serial service data stream into user service.
In another example, after the FPGA monitors service data through the serial port RTP, calculating bandwidth according to the service data and sending the bandwidth to the CPU;
and the CPU configures the multiplexing/demultiplexing strategy of the FPGA and manages the switching of the working states of the channels according to the received transmission bandwidth requirement and by combining a transmission channel time slot bandwidth slicing mechanism.
Each interface adopts 1 byte as a transmission control signal, and each transmission control signal comprises a service type code and an occupied bandwidth number;
wherein, bit 0-bit 4 in the corresponding byte of the control signal represents the bandwidth number required by the service, and bit 5-bit 7 represent the service type code;
when the control byte is b00000000, it indicates that the corresponding interface has no data.
In another embodiment, the process of integrating the plurality of transmission control signals into a corresponding dynamic control signal includes: and taking a frame synchronization signal of the system as a start bit, starting from a first path of interface of the system, and combining control signals corresponding to the interfaces into a path of serial code stream in a byte-interleaved mode to serve as dynamic control signals of a system transmitting end.
In another embodiment, a combining process for dynamically combining the respective traffic streams into a high-speed synchronous serial data stream is configured to include identification of a transmission control signal and traffic stream multiplexing;
the method comprises the steps that a transmission control signal is identified and configured to reject non-transmission data service, and transmission bandwidth is allocated to the rest service in a system;
the service data stream multiplexing is configured to combine the service data streams to be transmitted into a high-speed synchronous serial data stream by adopting a byte interleaving mode.
In another embodiment, the framing processing and service coding information stream inserting method is as follows: the framing process of the system is the same as the original synchronous framing mode (such as PCM, SDH, etc.), and the service coding information stream is synchronously inserted into the overhead bits of the frame signal for transmission.
In another embodiment, the method for configuring the transmission channel slot bandwidth slicing mechanism is as follows: and slicing the transmission channel by taking the service transmission bandwidth with the minimum bandwidth requirement in the system as a reference, and adjusting the transmission bandwidths of the rest services to be integer multiples of the reference transmission bandwidth.
The above embodiments are merely illustrative of a preferred embodiment, but are not limited thereto. In practicing the present invention, appropriate substitutions and/or modifications may be made according to the needs of the user.
The number of equipment and the scale of processing described herein are intended to simplify the description of the present invention. The application, modification and variation of the multiple traffic shared channel transmission system based on the synchronous time division multiplexing system of the present invention will be apparent to those skilled in the art.
Although embodiments of the invention have been disclosed above, they are not limited to the use listed in the specification and embodiments. It can be applied to various fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art. Therefore, the invention is not to be limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (7)
1. A multichannel service shared channel transmission system based on a synchronous time division multiplexing system is characterized in that each service end is communicated with a transmission channel through a matched FPGA and a CPU;
the FPGA monitors service data through the serial port RTP on the FPGA, codes each serial port end of the FPGA to realize service coding, and further, the receiving and transmitting data of the FPGA corresponds to the serial port RTP through the identification of the coding;
the CPU is communicated with the FPGA through the AD bus, so that dynamic time division multiplexing of multiple paths of services and dynamic adjustment of time slot bandwidth of a transmission channel are realized according to dynamic control signals sent by the FPGA, and synchronous time division multiplexing of the transmission channel is further realized;
when the service end sends data, the data processing flow of the FPGA comprises:
the FPGA receives service data through each serial port RTP, converts the received service data into corresponding synchronous serial codes and simultaneously generates corresponding transmission control signals;
each interface adopts 1 byte as a transmission control signal, and each transmission control signal comprises a service type code and an occupied bandwidth number;
the method comprises the steps that a sending control module TDC on an FPGA is used for comprehensively processing sending control signals received from each serial port end to form a corresponding dynamic control signal to be sent to a CPU, and further a multiplexing control signal is built to realize dynamic control of a multiplexing unit, and coding identification of service flows on each serial port end in a system is completed to generate corresponding service code flows;
the integrated processing procedure for integrating a plurality of transmission control signals into a corresponding dynamic control signal includes: taking a frame synchronizing signal of a system as a starting bit, starting from a first path of interface of the system, combining a path of serial code stream by a byte-interleaved mode from a transmission control signal corresponding to each interface, and taking the serial code stream as a dynamic control signal of a system transmitting end;
dynamically multiplexing each service code stream into high-speed synchronous serial data stream to a framing/de-framing module FAMER according to multiplexing control signals received from a CPU (Central processing Unit) through a multiplexing module MUX (micro-processing Unit) on the FPGA;
the framing/de-framing module FAMER carries out framing processing and business coding information stream insertion on the received high-speed serial data stream according to the line requirement of a transmission channel so as to realize the transmission of business data through the output of the transmission channel.
2. The system for transmitting multiple channels of service sharing based on synchronous time division multiplexing system as claimed in claim 1, wherein the data processing flow of the FPGA when the service side receives data comprises:
signal frame decoding is carried out on the data from the transmission channel through a framing/frame decoding module FAMER on the FPGA, and the extraction of service coding information, the extraction of service data and the conversion of code streams are completed;
processing the code stream identification signal received from the framing/de-framing module FAMER through a receiving control module RDC on the FPGA, and decomposing the code stream identification signal to obtain a receiving control signal and a de-multiplexing control signal matched with each service end;
the high-speed serial data stream sent from the framing/de-framing module FAMER is decomposed into serial service data stream by a de-multiplexing module DMUX on the FPGA, and the serial service data stream is sent to a serial port RTP;
and receiving corresponding service control signals from a receiving control module RDC through a serial port RTP on the FPGA, and converting the received serial service data stream into user service.
3. The system for transmitting multiple channels of service sharing channel based on synchronous time division multiplexing system according to claim 1, wherein said FPGA calculates bandwidth according to service data and sends it to CPU after monitoring service data through serial port RTP;
and the CPU configures the multiplexing/demultiplexing strategy of the FPGA and manages the switching of the working states of the channels according to the received transmission bandwidth requirement and by combining a transmission channel time slot bandwidth slicing mechanism.
4. The multi-channel service shared channel transmission system based on synchronous time division multiplexing system as claimed in claim 1, wherein bits 0 to 4 in the corresponding bytes of the transmission control signal represent the number of bandwidths required by the service, and bits 5 to 7 represent the type code of the service;
when the control byte is b00000000, it indicates that the corresponding interface has no data.
5. The multiple service shared channel transmission system based on the synchronous time division multiplexing system as recited in claim 1, wherein the combining process of combining each service code stream into a high-speed synchronous serial data stream is configured to include: identification of a transmission control signal and multiplexing of service data streams;
the method comprises the steps that a transmission control signal is identified and configured to reject non-transmission data service, and transmission bandwidth is allocated to the rest service in a system;
the service data stream multiplexing is configured to combine the service data streams to be transmitted into a high-speed synchronous serial data stream by adopting a byte interleaving mode.
6. The multiple service shared channel transmission system based on synchronous time division multiplexing system as claimed in claim 1, wherein the framing process and service coding information stream insertion method comprises: the system framing processing is the same as the original synchronous framing mode, and the service coding information stream is synchronously inserted into overhead bits of a frame signal for transmission;
wherein the primary synchronization framing mode is PCM or SDH.
7. The multiple service shared channel transmission system based on synchronous time division multiplexing system as claimed in claim 3, wherein the method for configuring the transmission channel time slot bandwidth slicing mechanism is as follows: and slicing the transmission channel by taking the service transmission bandwidth with the minimum bandwidth requirement in the multichannel service shared channel transmission system as a reference, and adjusting the transmission bandwidths of the rest services to be integer multiples of the reference transmission bandwidth.
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