CN113488091A - Imprint suppression method - Google Patents
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- CN113488091A CN113488091A CN202110819181.0A CN202110819181A CN113488091A CN 113488091 A CN113488091 A CN 113488091A CN 202110819181 A CN202110819181 A CN 202110819181A CN 113488091 A CN113488091 A CN 113488091A
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- 230000001629 suppression Effects 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000012360 testing method Methods 0.000 claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 230000000087 stabilizing effect Effects 0.000 claims description 16
- 230000002401 inhibitory effect Effects 0.000 claims description 9
- 238000001514 detection method Methods 0.000 abstract description 2
- 230000010287 polarization Effects 0.000 description 11
- 230000006386 memory function Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000005764 inhibitory process Effects 0.000 description 1
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
Abstract
The invention provides a marking suppression method, which is applied to the manufacture of a ferroelectric memory and comprises the steps that after the test of the ferroelectric memory is finished, a control circuit of the ferroelectric memory applies suppression voltage to a ferroelectric memory unit to suppress the generation of marks in the ferroelectric memory unit and improve the performance of the ferroelectric memory, and the control circuit is realized through an internal circuit of the ferroelectric memory without an external circuit, so that the detection cost is reduced, wherein the suppression voltage and the write operation voltage of the ferroelectric memory unit are mutually reverse voltages, and the suppression voltage is greater than or equal to the coercive voltage of the ferroelectric memory unit and is less than the write operation voltage.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for suppressing imprinting.
Background
In the case where the ferroelectric memory is left for a long time in a state where data is written (ferroelectric film polarization state) or the ferroelectric film is exposed to a high temperature in a state where data is written on the ferroelectric memory, imprint may be generated in the ferroelectric memory.
Chinese patent publication No. CN1383210A discloses a ferroelectric memory, in which a mark suppressing part is added to the ferroelectric memory to suppress the generation of marks, and an additional circuit mark suppressing part is added to increase the chip area and the cost.
Therefore, there is a need to provide a new imprint suppression method to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a mark suppression method, which suppresses the generation of marks in a ferroelectric memory cell and improves the performance of a ferroelectric memory.
In order to achieve the above object, the imprint suppressing method of the present invention is applied to manufacture of a ferroelectric memory, and includes:
after the test of the ferroelectric memory is finished, applying an inhibiting voltage to the ferroelectric memory unit by a control circuit of the ferroelectric memory to inhibit the generation of marks in the ferroelectric memory unit, wherein the inhibiting voltage and the write operation voltage of the ferroelectric memory unit are opposite voltages, and the inhibiting voltage is greater than or equal to the coercive voltage of the ferroelectric memory unit and is less than the write operation voltage.
The imprinting inhibition method has the advantages that: after the ferroelectric memory is tested, the control circuit of the ferroelectric memory applies suppression voltage to the ferroelectric memory unit to suppress the generation of marks in the ferroelectric memory unit and improve the performance of the ferroelectric memory, and the detection cost is reduced by realizing the control circuit through the internal circuit of the ferroelectric memory without an external circuit.
Preferably, the inhibit voltage is one-half of the write operation voltage.
Preferably, the control circuit includes a ferroelectric memory cell parameter register and a digital voltage stabilizing circuit, the ferroelectric memory cell parameter register outputs a state parameter signal of the ferroelectric memory according to a received operation instruction of the ferroelectric memory, and the digital voltage stabilizing circuit converts an external voltage signal into the write operation voltage or the inhibit voltage applied to the ferroelectric memory cell according to the state parameter signal of the ferroelectric memory output by the ferroelectric memory cell parameter register.
Further preferably, the state parameter signal of the ferroelectric memory is a digital signal, different digital signals represent different control commands, and the digital voltage stabilizing circuit converts an external voltage signal into different write operation voltages or different inhibit voltages according to different digital signals.
Preferably, the write operation voltage is a voltage applied to the ferroelectric memory cell by a control circuit of the ferroelectric memory at the time of testing of the ferroelectric memory.
Preferably, the method further comprises writing data into the ferroelectric memory cell after the test of the ferroelectric memory is completed, and the write operation voltage is a voltage applied to the ferroelectric memory cell by a control circuit of the ferroelectric memory when data is written into the ferroelectric memory cell. The beneficial effects are as follows: it is convenient to apply the inhibit voltage to the ferroelectric memory cell in the event of loss of the test write operation voltage.
Further preferably, the testing and the writing of data into the ferroelectric memory cell each comprise:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the write operation voltage to the bit line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the plate line connection terminal of the ferroelectric memory cell to write data 1 into the ferroelectric memory cell.
Further preferably, the applying, by the control circuit of the ferroelectric memory, the inhibit voltage to the ferroelectric memory cell comprises:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the suppression voltage to the plate line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the bit line connection terminal of the ferroelectric memory cell. The beneficial effects are that: it is convenient to apply the inhibit voltage to the ferroelectric memory storing the data 1.
Further preferably, the testing and the writing of data into the ferroelectric memory cell each comprise:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the write operation voltage to the plate line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the bit line connection terminal of the ferroelectric memory cell to write data 0 into the ferroelectric memory cell.
Further preferably, the applying, by the control circuit of the ferroelectric memory, the inhibit voltage to the ferroelectric memory cell comprises:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
the suppression voltage is applied to the bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory, and the plate line connection terminal of the ferroelectric memory cell is grounded. The beneficial effects are that: it is convenient to apply the inhibit voltage to the ferroelectric memory storing data 0.
Preferably, the pulse width of the inhibit voltage is less than or equal to the pulse width of the write operation voltage.
Preferably, the test of the ferroelectric memory is any one of a test performed before packaging and a test performed after packaging.
Drawings
FIG. 1 illustrates a method for fabricating a ferroelectric memory in accordance with some embodiments of the present invention;
FIG. 2 illustrates a method of fabricating a ferroelectric memory according to further embodiments of the present invention;
FIG. 3 illustrates a method of fabricating a ferroelectric memory in accordance with further embodiments of the present invention;
FIG. 4 illustrates a method of fabricating a ferroelectric memory in accordance with yet other embodiments of the present invention;
FIG. 5 is a schematic diagram of a control circuit in some embodiments of the invention;
FIG. 6 is a graph showing the hysteresis characteristics of the polarization state of a ferroelectric memory cell fabricated by the prior art;
FIG. 7 is a graph of hysteresis characteristics of polarization states of ferroelectric memory cells having a suppression voltage applied thereto in some embodiments of the present invention;
FIG. 8 is a graph of hysteresis characteristics of polarization states of another prior art ferroelectric memory cell;
fig. 9 is a graph of hysteresis characteristics of polarization states of ferroelectric memory cells having a suppression voltage applied thereto in further embodiments of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In view of the problems in the prior art, an embodiment of the present invention provides an imprint suppression method applied to manufacture of a ferroelectric memory, including:
after the test of the ferroelectric memory is finished, applying an inhibiting voltage to the ferroelectric memory unit by a control circuit of the ferroelectric memory to inhibit the generation of marks in the ferroelectric memory unit, wherein the inhibiting voltage and the write operation voltage of the ferroelectric memory unit are opposite voltages, and the inhibiting voltage is greater than or equal to the coercive voltage of the ferroelectric memory unit and is less than the write operation voltage. Preferably, the inhibit voltage is one half of the write operation voltage, and the pulse width of the inhibit voltage is smaller than or equal to the pulse width of the write operation voltage.
In some embodiments, the testing of the ferroelectric memory is any one of a testing performed before packaging and a testing performed after packaging.
In some embodiments, the write operation voltage is a voltage applied to the ferroelectric memory cell by a control circuit of the ferroelectric memory at the time of testing of the ferroelectric memory. In still other embodiments, the writing of data into the ferroelectric memory cell is further performed after the test of the ferroelectric memory is completed, and the write operation voltage is a voltage applied to the ferroelectric memory cell by a control circuit of the ferroelectric memory when data is written into the ferroelectric memory cell.
In some embodiments, said testing and said writing data into said ferroelectric memory cell each comprise:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the write operation voltage to the bit line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the plate line connection terminal of the ferroelectric memory cell to write data 1 into the ferroelectric memory cell.
When data 1 has been written in the ferroelectric memory cell, the applying, by the control circuit of the ferroelectric memory, an inhibit voltage to the ferroelectric memory cell includes:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the suppression voltage to the plate line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the bit line connection terminal of the ferroelectric memory cell.
In still other embodiments, the testing and the writing data into the ferroelectric memory cell each comprise:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the write operation voltage to the plate line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the bit line connection terminal of the ferroelectric memory cell to write data 0 into the ferroelectric memory cell.
When data 0 has been written in the ferroelectric memory cell, the applying, by the control circuit of the ferroelectric memory, an inhibit voltage to the ferroelectric memory cell includes:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
the suppression voltage is applied to the bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory, and the plate line connection terminal of the ferroelectric memory cell is grounded.
Example 1
Fig. 1 illustrates a method of fabricating a ferroelectric memory in accordance with some embodiments of the present invention. Referring to fig. 1, a method of manufacturing a ferroelectric memory includes the steps of:
s100: manufacturing a wafer, and then performing a ferroelectric memory processing process on the wafer to form a die (die) having a ferroelectric memory function on the wafer, wherein the die already has a circuit of the ferroelectric memory, and the circuit of the ferroelectric memory includes a control circuit and a ferroelectric memory cell;
s101: applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell; then, a control circuit of the ferroelectric memory applies a write operation voltage of 2.5V to a bit line connecting terminal of the ferroelectric memory unit, and a plate line connecting terminal of the ferroelectric memory unit is grounded to write data 1 into the ferroelectric memory unit, so as to realize the test of the ferroelectric memory; or a control circuit of the ferroelectric memory applies a write operation voltage of 2.5V to a plate line connecting terminal of the ferroelectric memory unit, and makes a bit line connecting terminal of the ferroelectric memory unit grounded so as to write data 0 into the ferroelectric memory unit, thereby realizing the test of the ferroelectric memory; then, dividing the wafer to screen out qualified crystal grains;
s102: applying an inhibit voltage to the ferroelectric memory cell in the qualified crystal grain, wherein if data 1 is written into the ferroelectric memory cell during the test in step S101, a control circuit of the ferroelectric memory applies a turn-on voltage to a word line connection terminal of the ferroelectric memory cell to gate the ferroelectric memory cell, and then the control circuit of the ferroelectric memory applies an inhibit voltage of 1.25V to a plate line connection terminal of the ferroelectric memory cell and grounds a bit line connection terminal of the ferroelectric memory cell; if data 0 is written into the ferroelectric memory cell during the test in step S101, applying a turn-on voltage to the word line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory to gate the ferroelectric memory cell, and then applying a suppression voltage of 1.25V to the bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory and grounding the plate line connection terminal of the ferroelectric memory cell;
s103: packaging is performed to form the final ferroelectric memory.
In embodiment 1, after the final ferroelectric memory is formed after packaging, the test of the packaged chip is performed, and the suppression voltage is applied again after the test of the packaged chip is completed to remove the imprint.
Example 2
Fig. 2 illustrates a method of fabricating a ferroelectric memory according to further embodiments of the present invention. Referring to fig. 2, a method of manufacturing a ferroelectric memory includes the steps of:
s200: manufacturing a wafer, and then performing a ferroelectric memory processing process on the wafer to form a die (die) having a ferroelectric memory function on the wafer, wherein the die has a circuit of the ferroelectric memory therein, and the circuit of the ferroelectric memory includes a control circuit and a ferroelectric memory cell;
s201: cutting and packaging the wafer to form a packaged ferroelectric memory, and applying a conducting voltage to a word line connecting end of a ferroelectric memory unit by a control circuit of the ferroelectric memory to gate the ferroelectric memory unit; then, a control circuit of the ferroelectric memory applies 3V write operation voltage to a bit line connecting terminal of the ferroelectric memory unit, and a plate line connecting terminal of the ferroelectric memory unit is grounded so as to write data 1 into the ferroelectric memory unit, thereby realizing the test of the ferroelectric memory; or a control circuit of the ferroelectric memory applies 3V write operation voltage to a plate line connecting terminal of the ferroelectric memory unit, and leads a bit line connecting terminal of the ferroelectric memory unit to be grounded so as to write data 0 into the ferroelectric memory unit, thereby realizing the test of the ferroelectric memory;
s202: applying an inhibit voltage to the ferroelectric memory cells in the qualified ferroelectric memory, wherein if data 1 is written into the ferroelectric memory cells during the test in step S201, a control circuit of the ferroelectric memory applies a turn-on voltage to word line connection terminals of the ferroelectric memory cells to gate the ferroelectric memory cells, and then the control circuit of the ferroelectric memory applies an inhibit voltage of 2V to plate line connection terminals of the ferroelectric memory cells and grounds bit line connection terminals of the ferroelectric memory cells; if data 0 is written in the ferroelectric memory cell at the time of the test in step S201, a control circuit of the ferroelectric memory applies a turn-on voltage to a word line connection terminal of the ferroelectric memory cell to gate the ferroelectric memory cell, and then a control circuit of the ferroelectric memory applies a suppression voltage of 2V to a bit line connection terminal of the ferroelectric memory cell and grounds a plate line connection terminal of the ferroelectric memory cell.
Fig. 3 illustrates a method of fabricating a ferroelectric memory in accordance with further embodiments of the present invention. Referring to fig. 3, a method of manufacturing a ferroelectric memory includes the steps of:
s300: manufacturing a wafer, and then performing a ferroelectric memory processing process on the wafer to form a die (die) having a ferroelectric memory function on the wafer, wherein the die already has a circuit of the ferroelectric memory, and the circuit of the ferroelectric memory includes a control circuit and a ferroelectric memory cell;
s301: writing data 1 or data 1 into the ferroelectric memory unit, then reading to realize the test of the ferroelectric memory, and segmenting the wafer to screen out qualified crystal grains; applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell, then applying a write operation voltage of 2.5V to a bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory, and grounding a plate line connection terminal of the ferroelectric memory cell to write data 1 into the ferroelectric memory cell; or a control circuit of the ferroelectric memory applies a write operation voltage of 2.5V to a plate line connection terminal of the ferroelectric memory cell and grounds a bit line connection terminal of the ferroelectric memory cell to write data 0 into the ferroelectric memory cell;
s302: if the data written into the ferroelectric memory cell at the time of the test in step S301 is lost, data 1 or data 0 is newly written into the ferroelectric memory cell, wherein a turn-on voltage is applied to the word line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory to gate the ferroelectric memory cell, then a write operation voltage of 2.5V is applied to the bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory, and the plate line connection terminal of the ferroelectric memory cell is grounded to write data 1 into the ferroelectric memory cell; applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell, and then applying the write operation voltage to a plate line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory and grounding a bit line connection terminal of the ferroelectric memory cell to write data 0 into the ferroelectric memory cell;
s303: if data 1 is written into the ferroelectric memory cell in step S302, the control circuit of the ferroelectric memory applies a turn-on voltage to the word line connection terminal of the ferroelectric memory cell to gate the ferroelectric memory cell, and then the control circuit of the ferroelectric memory applies a suppression voltage of 1.2V to the plate line connection terminal of the ferroelectric memory cell and grounds the bit line connection terminal of the ferroelectric memory cell; if data 0 is written into the ferroelectric memory cell in step S302, a control circuit of the ferroelectric memory applies a turn-on voltage to a word line connection terminal of the ferroelectric memory cell to gate the ferroelectric memory cell, and then the control circuit of the ferroelectric memory applies a suppression voltage of 1.2V to a bit line connection terminal of the ferroelectric memory cell and grounds a plate line connection terminal of the ferroelectric memory cell;
s304: packaging is performed to form the final ferroelectric memory.
In embodiment 3, after the final ferroelectric memory is formed after packaging, the test of the packaged chip is performed, and the suppression voltage is applied again after the test of the packaged chip is completed to remove the imprint.
Fig. 4 illustrates a method of fabricating a ferroelectric memory in accordance with further embodiments of the present invention. Referring to fig. 4, a method of manufacturing a ferroelectric memory includes the steps of:
s400: manufacturing a wafer, and then performing a ferroelectric memory processing process on the wafer to form a die (die) having a ferroelectric memory function on the wafer, wherein the die already has a circuit of the ferroelectric memory, and the circuit of the ferroelectric memory includes a control circuit and a ferroelectric memory cell;
s401: cutting and packaging the wafer to form a packaged ferroelectric memory, writing data 1 or data 1 into the ferroelectric memory unit, and then reading to test the ferroelectric memory; applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell, then applying a write operation voltage of 2.5V to a bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory, and grounding a plate line connection terminal of the ferroelectric memory cell to write data 1 into the ferroelectric memory cell; or a control circuit of the ferroelectric memory applies a write operation voltage of 2.5V to a plate line connection terminal of the ferroelectric memory cell and grounds a bit line connection terminal of the ferroelectric memory cell to write data 0 into the ferroelectric memory cell;
s402: if the data written into the ferroelectric memory cell at the time of the test in step S401 is lost, data 1 or data 0 is newly written into the ferroelectric memory cell, wherein a turn-on voltage is applied to the word line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory to gate the ferroelectric memory cell, then a write operation voltage of 2.5V is applied to the bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory, and the plate line connection terminal of the ferroelectric memory cell is grounded to write data 1 into the ferroelectric memory cell; applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell, and then applying a write operation voltage of 2.5V to a plate line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory and grounding a bit line connection terminal of the ferroelectric memory cell to write data 0 into the ferroelectric memory cell;
s403: if data 1 is written into the ferroelectric memory cell in step S402, a control circuit of the ferroelectric memory applies a turn-on voltage to a word line connection terminal of the ferroelectric memory cell to gate the ferroelectric memory cell, and then the control circuit of the ferroelectric memory applies a suppression voltage of 1.5V to a plate line connection terminal of the ferroelectric memory cell and grounds a bit line connection terminal of the ferroelectric memory cell; if data 0 is written in the ferroelectric memory cell in step S402, a control circuit of the ferroelectric memory applies a turn-on voltage to a word line connection terminal of the ferroelectric memory cell to gate the ferroelectric memory cell, and then a control circuit of the ferroelectric memory applies a suppression voltage of 1.5V to a bit line connection terminal of the ferroelectric memory cell and grounds a plate line connection terminal of the ferroelectric memory cell.
In the foregoing embodiment 1, embodiment 2, embodiment 3 and embodiment 4, the principle of the present invention is described only by taking some examples, wherein the suppression voltage and the write operation voltage of the ferroelectric memory cell are opposite voltages, and the write operation voltage of the ferroelectric memory cell depends on the ferroelectric material of the ferroelectric memory cell and the specific circuit design requirements, etc., and is not limited to 2.5V, etc. recited in the foregoing specific examples, and likewise, the coercive voltage of the ferroelectric memory cell depends on the specific ferroelectric material used, and the coercive voltage thereof should also be determined according to the specific actual product. And the suppression voltage is greater than or equal to the coercive voltage of the ferroelectric memory cell and less than the write operation voltage. Preferably, the specific value of the inhibit voltage is one half of the write operation voltage of the ferroelectric memory cell. Preferably, the pulse width of the inhibit voltage is less than or equal to the pulse width of the write operation voltage.
FIG. 5 is a schematic diagram of a control circuit according to some embodiments of the present invention. Referring to fig. 5, the control circuit 100 includes a ferroelectric memory cell parameter register 101 and a digital voltage regulator circuit 102, the ferroelectric memory cell parameter register 101 outputs a ferroelectric memory state parameter signal according to a received operation command of the ferroelectric memory, and the digital voltage regulator circuit 102 converts an external voltage signal into the write operation voltage or the inhibit voltage applied to the ferroelectric memory cell according to the ferroelectric memory state parameter signal output by the ferroelectric memory cell parameter register. Preferably, the state parameter signal of the ferroelectric memory is a digital signal, different digital signals represent different control commands, and the digital voltage stabilizing circuit 102 converts an external voltage signal into different write operation voltages or different inhibit voltages according to different digital signals.
Referring to fig. 5, the ferroelectric memory cell parameter register 101 outputs a ferroelectric memory state parameter signal specifically to 0001, 0010, 0100, etc. according to a received operation instruction of the ferroelectric memory, the external voltage signal received by the digital voltage stabilizing circuit 102 is 3.3V, and when the ferroelectric memory state parameter signal received by the digital voltage stabilizing circuit 102 is 0001, the digital voltage stabilizing circuit 102 converts the external voltage signal of 3.3V into a write operation voltage of 3V for output; the external voltage signal received by the digital voltage stabilizing circuit 102 is 3.3V, and when the state parameter signal of the ferroelectric memory received by the digital voltage stabilizing circuit 102 is 0010, the digital voltage stabilizing circuit 102 converts the external voltage signal of 3.3V into a write operation voltage of 2.5V for output; the external voltage signal received by the digital voltage stabilizing circuit 102 is 3.3V, and when the state parameter signal of the ferroelectric memory received by the digital voltage stabilizing circuit 102 is 0100, the digital voltage stabilizing circuit 102 converts the external voltage signal of 3.3V into a suppression voltage of 1.25V for output. The ferroelectric memory cell parameter register 101 and the digital voltage stabilizing circuit 102 are common circuits of a ferroelectric memory in the prior art, and are not described in detail herein.
Fig. 6 is a graph showing hysteresis characteristics of a polarization state of a ferroelectric memory cell fabricated by using the prior art. Referring to fig. 6, wherein a first curve 1 represents the hysteresis characteristic curve of the ferroelectric memory cell manufactured by the prior art, and a second curve 2 represents the hysteresis characteristic curve of the ferroelectric memory cell manufactured by the prior art after being baked at 175 ℃ for 52 minutes, which is used for simulating the packaging of a chip, it can be clearly seen that, in the prior art, after being baked at 175 ℃ for 52 minutes to complete the packaging, the second curve 2 is obviously changed from the first curve 1, which indicates that the ferroelectric memory cell manufactured by the method according to the prior art generates obvious marks after being baked at 175 ℃ for 52 minutes.
Fig. 7 is a graph of hysteresis characteristics of polarization states of ferroelectric memory cells having a suppression voltage applied thereto in some embodiments of the present invention. Referring to fig. 7, under the same condition of the write operation voltage before and after packaging, a third curve 3 shows the hysteresis characteristic curve of the polarization state of the ferroelectric memory cell of the ferroelectric memory manufactured according to the method of the present invention, and a fourth curve 4 shows the hysteresis characteristic curve of the ferroelectric memory cell after the ferroelectric memory is baked at 175 ℃ for 52 minutes after the reverse inhibit voltage is applied to the tested ferroelectric memory, it can be clearly seen that after the ferroelectric memory is baked at 175 ℃ for 52 minutes after the reverse inhibit voltage is applied to the tested ferroelectric memory, the fourth curve 4 has no significant change relative to the third curve 3, which illustrates that after the reverse inhibit voltage is applied to the tested ferroelectric memory by the method of the present invention, no obvious mark is generated in the ferroelectric memory cell after the ferroelectric memory cell is baked for 52 minutes under the condition of 175 ℃.
Fig. 8 is a graph showing the hysteresis characteristics of the polarization state of another ferroelectric memory cell fabricated by the prior art. Referring to fig. 8, wherein a fifth curve 5 shows the hysteresis characteristic curve of the ferroelectric memory cell manufactured by the prior art, and a sixth curve 6 shows the hysteresis characteristic curve of the ferroelectric memory cell manufactured by the prior art after being baked at 200 ℃ for 15 hours, which is used for simulating chip bonding after packaging, it can be clearly seen that, in the prior art, after being baked at 200 ℃ for 15 hours, the sixth curve 6 is obviously changed from the fifth curve 5, which illustrates that the ferroelectric memory cell manufactured by the method according to the prior art generates obvious marks after being baked at 200 ℃ for 15 hours.
Fig. 9 is a graph of hysteresis characteristics of polarization states of ferroelectric memory cells having a suppression voltage applied thereto in further embodiments of the present invention. Referring to fig. 9, under the same conditions of the write operation voltage before and after packaging, wherein a seventh curve 7 shows the polarization state hysteresis characteristic curve of the ferroelectric memory cell of the ferroelectric memory manufactured according to the method of the present invention, and an eighth curve 8 shows the hysteresis characteristic curve of the ferroelectric memory cell after applying the reverse inhibit voltage to the tested ferroelectric memory and then baking the ferroelectric memory cell at 200 ℃ for 15 hours by using the method of the present invention, it can be clearly seen that the eighth curve 8 does not significantly change from the seventh curve 7 after baking the ferroelectric memory at 200 ℃ for 15 hours after applying the reverse inhibit voltage to the tested ferroelectric memory by using the method of the present invention, which illustrates that no significant imprint is generated in the packaged ferroelectric memory cell after baking the ferroelectric memory at 200 ℃ for 15 hours after applying the reverse inhibit voltage to the tested ferroelectric memory by using the method of the present invention .
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (12)
1. A imprint suppression method applied to manufacture of a ferroelectric memory, comprising:
after the test of the ferroelectric memory is finished, applying an inhibiting voltage to the ferroelectric memory unit by a control circuit of the ferroelectric memory to inhibit the generation of marks in the ferroelectric memory unit, wherein the inhibiting voltage and the write operation voltage of the ferroelectric memory unit are opposite voltages, and the inhibiting voltage is greater than or equal to the coercive voltage of the ferroelectric memory unit and is less than the write operation voltage.
2. The imprint suppression method of claim 1, wherein the suppression voltage is one-half of the write operation voltage.
3. The imprint suppressing method as recited in claim 1, wherein the control circuit includes a ferroelectric memory cell parameter register that outputs a ferroelectric memory state parameter signal in accordance with the received operation instruction of the ferroelectric memory, and a digital voltage stabilizing circuit that converts an external voltage signal into the write operation voltage or the suppression voltage to be applied to the ferroelectric memory cell in accordance with the ferroelectric memory state parameter signal output from the ferroelectric memory cell parameter register.
4. The imprint suppressing method of claim 3, wherein the state parameter signal of the ferroelectric memory is a digital signal, different ones of the digital signals represent different control commands, and the digital voltage stabilizing circuit converts an external voltage signal into different ones of the write operation voltage or the suppression voltage in accordance with the different ones of the digital signals.
5. The imprint suppressing method according to claim 1, wherein the write operation voltage is a voltage applied to the ferroelectric memory cell by a control circuit of the ferroelectric memory at the time of testing of the ferroelectric memory.
6. The imprint suppressing method according to claim 1, further comprising writing data into the ferroelectric memory cell after the test of the ferroelectric memory is completed, wherein the write operation voltage is a voltage applied to the ferroelectric memory cell by a control circuit of the ferroelectric memory when data is written into the ferroelectric memory cell.
7. The imprint suppression method according to claim 5 or 6, wherein the testing and the writing of data into the ferroelectric memory cell each include:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the write operation voltage to the bit line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the plate line connection terminal of the ferroelectric memory cell to write data 1 into the ferroelectric memory cell.
8. The imprint suppression method of claim 7, wherein the applying, by the control circuit of the ferroelectric memory, the suppression voltage to the ferroelectric memory cell comprises:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the suppression voltage to the plate line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the bit line connection terminal of the ferroelectric memory cell.
9. The imprint suppression method according to claim 5 or 6, wherein the testing and the writing of data into the ferroelectric memory cell each include:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
applying the write operation voltage to the plate line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory, and grounding the bit line connection terminal of the ferroelectric memory cell to write data 0 into the ferroelectric memory cell.
10. The imprint suppression method of claim 9, wherein the applying, by the control circuit of the ferroelectric memory, the suppression voltage to the ferroelectric memory cell comprises:
applying a turn-on voltage to a word line connection terminal of the ferroelectric memory cell by a control circuit of the ferroelectric memory to gate the ferroelectric memory cell;
the suppression voltage is applied to the bit line connection terminal of the ferroelectric memory cell by the control circuit of the ferroelectric memory, and the plate line connection terminal of the ferroelectric memory cell is grounded.
11. The imprint suppression method of claim 1, wherein a pulse width of the suppression voltage is less than or equal to a pulse width of the write operation voltage.
12. The imprint suppressing method according to claim 1, wherein the test of the ferroelectric memory is any one of a test performed before packaging and a test performed after packaging.
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