CN113485791A

CN113485791A - Configuration method, access method, device, virtualization system and storage medium

Info

Publication number: CN113485791A
Application number: CN202110767684.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Bi Ren Technology Co ltd
Priority date: 2021-07-07
Filing date: 2021-07-07
Publication date: 2021-10-08
Anticipated expiration: 2041-07-07
Also published as: CN113485791B

Abstract

A configuration method and an access method, an apparatus, a virtualization system, and a storage medium. The configuration method is used for configuring on-chip cache space of a computing device, the computing device comprises a physical device and a storage device, and at least one virtual device is created, and the configuration method comprises the following steps: dividing at least one partitioned memory space in the memory space of a storage device of the computing equipment; the split memory space comprises a first memory subspace and a second memory subspace, the first memory subspace is configured to be accessed by the virtual device at least in a memory mode, and the second memory subspace is configured to be accessed by the physical device but cannot be accessed by the virtual device in the memory mode; and dividing a third memory subspace in the second memory subspace, configuring the third memory subspace as an on-chip cache space of the virtual device, and accessing the on-chip cache space by the virtual device in a cache mode. The configuration method can provide the on-chip cache space for the user of the virtual machine to use under the condition of not increasing extra hardware and physical address space.

Description

Configuration method, access method, device, virtualization system and storage medium

Technical Field

The embodiment of the disclosure relates to a configuration method and an access method applied to an on-chip cache space of a computing device, a configuration device, an access device, a virtualization system of the computing device and a storage medium.

Background

In the field of computers, on-chip buffers (on-chip buffers) can improve the performance of computing, transmission, storage and the like, and therefore, the performance of the whole system can be greatly improved. Under the virtualization technology, the virtual machine is sensitive to performance, and if support for on-chip buffering can be added, obvious performance improvement can be brought to virtualization.

Disclosure of Invention

At least one embodiment of the present disclosure provides a configuration method applied to an on-chip cache space of a computing device, where the computing device includes at least one physical apparatus and a storage apparatus, and at least one virtual apparatus is created in the computing device, and the method includes: partitioning at least one partitioned memory space for the at least one virtual device in a memory space of a storage device of the computing apparatus, the partitioned memory space comprising a first memory subspace configured to be memory-accessed at least by the virtual device and a second memory subspace configured to be memory-accessed by the physical device but not by the virtual device; and dividing a third memory subspace in the second memory subspace, configuring the third memory subspace as an on-chip cache space of the virtual device, and accessing the on-chip cache space by the virtual device in a cache manner.

For example, in a configuration method provided in at least one embodiment of the present disclosure, the third memory subspace is less than or equal to the second memory subspace.

For example, in a configuration method provided in at least one embodiment of the present disclosure, the third memory subspace is addressed continuously with the first memory subspace.

For example, in a configuration method provided in at least one embodiment of the present disclosure, the third memory subspace is not addressed consecutively to the first memory subspace.

For example, in a configuration method provided in at least one embodiment of the present disclosure, the accessing by the virtual device in the cache manner includes: in the virtual appliance, access is made in a cache manner from a device side of the virtual appliance, or in the virtual appliance, access is made in a cache manner from a host side of the virtual appliance.

For example, in a configuration method provided by at least one embodiment of the present disclosure, a plurality of virtual devices are created in a computing apparatus, and at least one split memory space for the at least one virtual device is partitioned from a memory space of a storage device of the computing apparatus, including: and respectively dividing a plurality of partitioned memory spaces correspondingly used for the plurality of virtual devices in the memory space of the storage device of the computing equipment, wherein one virtual device corresponds to one partitioned memory space.

At least one embodiment of the present disclosure further provides an access method for an on-chip cache space, where the on-chip cache space is configured based on a configuration method for the on-chip cache space provided in any embodiment of the present disclosure, and the access method includes: responding to the access request for the partitioned memory space to be an access request from the virtual device, judging whether the address of the access request exceeds the first memory subspace, and responding to the address of the access request located in the first memory subspace, and accessing the first memory subspace in a memory mode by the virtual device; and responding to the address of the access request exceeding the first memory subspace, judging whether the address of the access request exceeds the third memory subspace, and responding to the address of the access request located in the third memory subspace, and accessing the third memory subspace by the virtual device in a cache mode.

For example, the access method provided in at least one embodiment of the present disclosure further includes: responding to the access request for the partitioned memory space from the physical device, judging whether the address of the access request exceeds the partitioned memory space, responding to the address of the access request in the partitioned memory space, and accessing the partitioned memory space by the physical device; and reporting an error in response to the address of the access request exceeding the partitioned memory space.

For example, the access method provided in at least one embodiment of the present disclosure further includes: determining whether the access request to the partitioned memory space is from the physical device or the virtual device.

For example, in an access method provided in at least one embodiment of the present disclosure, an access request from the physical device and an access request from the virtual device respectively include a device-side access request and a host-side access request; the device side access request of the physical device is configured to access the partitioned memory space from the device side of the physical device; the host side access request of the physical device is configured to access the second memory subspace from the host side of the physical device; the device side access request of the virtual device is configured to access the first memory subspace and the third memory subspace from the device side of the virtual device in a memory manner; the host side access request of the virtual device is configured to access the first memory subspace in a memory manner and the third memory subspace in a cache manner from the host side of the virtual device.

For example, in an access method provided in at least one embodiment of the present disclosure, in response to that the access request for the partitioned memory space is an access request from the virtual device, determining whether an address of the access request exceeds the first memory subspace includes: determining whether an access request from the virtual device is a device side access request or a host side access request of the virtual device; responding to the access request which is a device side access request of the virtual device, judging whether the address of the access request exceeds the first memory subspace, responding to the address of the access request which is positioned in the first memory subspace, and accessing the first memory subspace by the virtual device in a memory mode; and responding to the address of the access request exceeding the first memory subspace, judging whether the address of the access request exceeds the third memory subspace, and responding to the address of the access request located in the third memory subspace, and accessing the third memory subspace by the virtual device in a cache mode.

For example, in an access method provided in at least one embodiment of the present disclosure, in response to that the access request for the partitioned memory space is an access request from the virtual device, determining whether an address of the access request exceeds the first memory subspace, further includes: responding to the access request as a host side access request of the virtual device, judging whether the address of the access request exceeds the first memory subspace, responding to the address of the access request in the first memory subspace, and accessing the virtual device to the first memory subspace in the memory mode; an error is reported in response to the address of the access request exceeding the first memory subspace.

For example, in an access method provided in at least one embodiment of the present disclosure, in response to that the access request for the partitioned memory space is an access request from the virtual device, determining whether an address of the access request exceeds the first memory subspace includes: determining whether an access request from the virtual device is a device side access request or a host side access request of the virtual device; responding to the access request as a host side access request of the virtual device, judging whether the address of the access request exceeds the first memory subspace, responding to the address of the access request in the first memory subspace, and accessing the first memory subspace by the virtual device in a memory mode; and responding to the address of the access request exceeding the first memory subspace, judging whether the address of the access request exceeds the third memory subspace, and responding to the address of the access request located in the third memory subspace, and accessing the third memory subspace by the virtual device in a cache mode.

For example, in an access method provided in at least one embodiment of the present disclosure, in response to that the access request for the partitioned memory space is an access request from the virtual device, determining whether an address of the access request exceeds the first memory subspace, further includes: responding to the access request which is a device side access request of the virtual device, judging whether the address of the access request exceeds the first memory subspace, responding to the address of the access request which is positioned in the first memory subspace, and accessing the first memory subspace by the virtual device in a memory mode; an error is reported in response to the address of the access request exceeding the first memory subspace.

For example, in an access method provided in at least one embodiment of the present disclosure, the device side and the host side of the virtual device access the third memory subspace in the cache manner at the same time.

For example, in an access method provided in at least one embodiment of the present disclosure, in response to that the access request for the partitioned memory space is an access request from the physical device, determining whether an address of the access request exceeds the partitioned memory space includes: judging whether the access request is a device side access request of the physical device or a host side access request of the physical device; responding to the access request which is a device side access request of the physical device, judging whether the address of the access request exceeds the partitioned memory space, responding to the address of the access request which is located in the partitioned memory space, and accessing the partitioned memory space by the physical device; and reporting an error in response to the address of the access request exceeding the partitioned memory space.

For example, in an access method provided in at least one embodiment of the present disclosure, in response to that the access request for the partitioned memory space is an access request from the physical device, determining whether an address of the access request exceeds the partitioned memory space, further includes: responding to the access request as a host side access request of the physical device, judging whether the address of the access request exceeds the second memory subspace, and responding to the address of the access request in the second memory subspace, and accessing the second memory subspace by the physical device; reporting an error in response to the address of the access request exceeding the second memory subspace.

For example, in the access method provided in at least one embodiment of the present disclosure, before determining whether an address of the access request exceeds the first memory subspace in response to the access request for the partitioned memory space being an access request from the virtual device, the method further includes: and judging whether the access request for the partitioned memory space is a device side access request or a host side access request.

For example, the access method provided in at least one embodiment of the present disclosure further includes: in response to the access request being the host side access request, determining whether the host side access request is an access request from the physical device or an access request from the virtual device; and in response to the host side access request for the partitioned memory space being an access request from the virtual device, determining whether an address of the access request exceeds the first memory subspace.

For example, in the access method provided in at least one embodiment of the present disclosure, in response to the access request being the device-side access request, it is determined whether the device-side access request is an access request from the physical apparatus or an access request from the virtual apparatus; responding to the access request which is a device side access request of the virtual device, judging whether the address of the access request exceeds the first memory subspace, responding to the address of the access request which is positioned in the first memory subspace, and accessing the first memory subspace by the virtual device in a memory mode; reporting an error in response to the address of the access request exceeding the first memory subspace; responding to the access request which is a device side access request of the physical device, judging whether the address of the access request exceeds the partitioned memory space, responding to the address of the access request which is located in the partitioned memory space, and accessing the partitioned memory space by the physical device; and reporting an error in response to the address of the access request exceeding the partitioned memory space.

For example, the access method provided in at least one embodiment of the present disclosure further includes: in response to the access request being the device-side access request, determining whether the device-side access request is an access request from the physical device or an access request from the virtual device; and in response to the device side access request for the partitioned memory space being an access request from the virtual device, determining whether the address of the access request exceeds the first memory subspace.

For example, in an access method provided in at least one embodiment of the present disclosure, in response to that the access request is the host side access request, it is determined whether the host side access request is an access request from the physical device or an access request from the virtual device; responding to the access request as a host side access request of the virtual device, judging whether the address of the access request exceeds the first memory subspace, responding to the address of the access request in the first memory subspace, and accessing the first memory subspace by the virtual device in a memory mode; reporting an error in response to the address of the access request exceeding the first memory subspace; responding to the access request as a host side access request of the physical device, judging whether the address of the access request exceeds the second memory subspace, and responding to the address of the access request in the second memory subspace, and accessing the second memory subspace by the physical device; reporting an error in response to the address of the access request exceeding the second memory subspace.

At least one embodiment of the present disclosure further provides a configuration apparatus applied to an on-chip cache space of a computing device, where the computing device includes at least one physical apparatus and a storage apparatus, at least one virtual apparatus is created in the computing device, and the configuration apparatus includes: a first configuration unit configured to partition at least one partitioned memory space for the at least one virtual device in a memory space of a storage device of the computing apparatus, the partitioned memory space comprising a first memory subspace configured to be memory-accessed at least by the virtual device and a second memory subspace configured to be memory-accessed by the physical device but not by the virtual device; a second configuration unit, configured to partition a third memory subspace in the second memory subspace, configure the third memory subspace as an on-chip cache space of the virtual device, and enable the virtual device to access the on-chip cache space in a cache manner.

At least one embodiment of the present disclosure further provides a configuration apparatus applied to an on-chip cache space of a computing device, where the computing device includes at least one physical apparatus and a storage apparatus, at least one virtual apparatus is created in the computing device, and the configuration apparatus includes: a processor; a memory; one or more computer program modules stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing a method of configuration provided by any embodiment of the disclosure.

At least one embodiment of the present disclosure further provides an access device for an on-chip cache space, where the on-chip cache space is configured by a configuration device provided in any one of the embodiments of the present disclosure, and the access device includes: a first access unit configured to determine whether an address of the access request exceeds the first memory subspace in response to the access request for the partitioned memory space being an access request from the virtual device, and a second access unit configured to access the first memory subspace by the virtual device in a memory manner in response to the address of the access request being located in the first memory subspace; and the fourth access unit is configured to respond to the fact that the address of the access request is located in the third memory subspace, and the virtual device accesses the third memory subspace in the cache mode.

At least one embodiment of the present disclosure further provides an access device for an on-chip cache space, where the on-chip cache space is configured by a configuration device provided in any one of the embodiments of the present disclosure, and the access device includes: a processor; a memory; one or more computer program modules stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing an access method provided by any embodiment of the present disclosure.

At least one embodiment of the present disclosure further provides a virtualization system of a computing device, including: a configuration device provided in any embodiment of the present disclosure or an access device, at least one physical device, and at least one virtual device provided in any embodiment of the present disclosure; wherein the physical device is configured to access the partitioned memory space or the second memory subspace; the virtual device is configured to access the first memory subspace in the memory mode and the third memory subspace in the cache mode.

At least one embodiment of the present disclosure also provides a storage medium that non-transitory stores computer readable instructions that, when executed by a computer, can perform a configuration method provided according to any embodiment of the present disclosure or an access method provided by any embodiment of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 shows a schematic diagram of accessing on-chip cache space in a non-virtualized situation;

fig. 2 is a flowchart illustrating a method for configuring an on-chip cache space according to at least one embodiment of the present disclosure;

FIG. 3 illustrates a schematic diagram of a partitioned storage provided by at least one embodiment of the present disclosure;

FIG. 4 illustrates a schematic diagram of physical devices and virtual devices accessing storage provided by at least one embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram of a third memory subspace provided by at least one embodiment of the present disclosure;

FIG. 6 illustrates a schematic diagram of discontinuous addressing of a third memory subspace and a first memory subspace provided by at least one embodiment of the present disclosure;

FIG. 7 illustrates a flow chart of an access method provided by at least one embodiment of the present disclosure;

FIG. 8 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure;

FIG. 9 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure;

FIG. 10 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure;

FIG. 11 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure;

FIG. 12 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure;

fig. 13 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure;

FIG. 14 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure;

fig. 15 illustrates a schematic block diagram of a configuration apparatus provided by at least one embodiment of the present disclosure;

fig. 16 is a schematic block diagram of an access device provided in at least one embodiment of the present disclosure;

fig. 17 illustrates a schematic block diagram of another configuration apparatus provided by at least one embodiment of the present disclosure;

fig. 18 shows a schematic block diagram of another access device provided by at least one embodiment of the present disclosure;

fig. 19 shows a schematic block diagram of another configuration device or access device provided by at least one embodiment of the present disclosure; and

fig. 20 illustrates a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In virtualization technology, a resource (e.g., a CPU (Central Processing Unit) or other peripheral device) on one physical device may be virtualized into multiple virtual physical components. The virtualization technology can virtualize a plurality of logical computers on one physical computer, that is, a plurality of logical computers can be simultaneously run on one physical computer, each logical computer has its own virtual hardware, for example, a virtual CPU (central Processing Unit), a virtual GPU (graphics Processing Unit), and the like, each logical computer can run different operating systems, and application programs on each logical computer can run in mutually independent spaces without mutual influence, so that the work efficiency of the computer can be significantly improved.

In an embodiment of the present disclosure, the physical device may be the above-mentioned physical computer, also referred to as a physical machine, which is a hardware system having hardware entities. The Virtual device may be the above-mentioned logical computer, also called Virtual Machine (Virtual Machine), which is a computer system having complete hardware system functions and operating in a completely isolated environment simulated by software.

In embodiments of the present disclosure, an on-chip cache may also be referred to as an on-chip buffer.

The inventor finds that, under the virtualization technology, if a virtual machine needs to access an on-chip buffer, an access mode needs specific hardware equipment and occupies extra hardware address space, and a specific interface is also needed for displaying operation, so that the complexity of hardware design and software use is brought compared with the access mode of the virtual machine to a memory. In another access mode, the virtual machine can perform the access operation of the on-chip buffer through the host, and in this access mode, the virtual machine cannot perform the access operation of the on-chip buffer alone.

At least one embodiment of the present disclosure provides a configuration method and an access method applied to an on-chip cache space of a computing device, a configuration apparatus, an access apparatus, a virtualization system of a computing device, and a storage medium. The computing equipment comprises at least one physical device and a storage device, at least one virtual device is established in the computing equipment, and the configuration method comprises the following steps: partitioning at least one partitioned memory space for at least one virtual device from memory spaces of storage devices of a computing device, the partitioned memory space comprising a first memory subspace configured to be accessed by at least the virtual device in a memory manner and a second memory subspace configured to be accessed by a physical device but not the virtual device in the memory manner; and dividing a third memory subspace in the second memory subspace, configuring the third memory subspace as an on-chip cache space of the virtual device, and accessing the on-chip cache space by the virtual device in a cache mode.

According to the configuration method provided by at least one embodiment of the present disclosure, under the condition that no additional hardware and physical address space are added, by using the characteristic that the physical memory address space can be multiplexed, a part of the physical memory address space is multiplexed as the on-chip cache space and provided for the user of the virtual machine, so that the user of the virtual machine can access the on-chip cache space in the same way as the physical memory, the operation mode is simple, and the complexity of hardware design and software use is reduced.

For example, the computing device includes, but is not limited to, a laptop, a desktop, a local area network server, a wide area network server, a cloud server, or an edge-end computer, etc. The computing device may include, for example, a host and a target device, the target device may be connected to the host, for example, may be a graphics card device externally connected to the host, the graphics card device may include a GPU and a GPU memory, etc., and the host may include a CPU and a CPU memory, etc.

For example, the storage device may be a storage device in the target device, for example, a GPU memory, or may be located outside the target device, for example, on the computing device, as long as the storage device is operated corresponding to the target device, and the storage device may be a semiconductor storage device (for example, a DRAM, an SRAM, a PMEM, or the like), a magnetic medium storage device (hard disk), or the like, which is not limited in this embodiment of the present disclosure. For example, the storage device may be a physical memory address space, for example, a physical address may be stored, and by accessing the physical address in the storage device, the target data pointed to by the physical address may be further accessed according to the physical address. In other embodiments, other data than physical addresses may be stored in the storage device.

For example, access to the address space of a storage device includes two categories, one is device (device) side access and the other is host (host) side access. For example, the device-side Access may be an Access of the target device to its own storage apparatus, such as an address Access request initiated by a DMA (Direct Memory Access) inside the target device to the storage apparatus, or an address Access request initiated by a computing unit of the target device to the storage apparatus, for example; the host-side access may be an access to the storage device by another device except the target device, for example, an address access request initiated by a Central Processing Unit (CPU) in the host to the storage device, and the like, which is not limited in this embodiment of the disclosure.

For example, a computing device includes at least one physical appliance, and at least one virtual appliance may be created in the computing device using virtualization techniques.

For example, the access of the physical device to the storage device may be divided into host (host) side access of the physical device and device (device) side access of the physical device, and the host side access of the physical device may be the access of the host of the physical device to the storage device of the target device, for example, the access of the CPU of the physical device to the GPU memory of the physical device. The device-side access of the physical device may be that the target device of the physical device accesses a memory device of the target device itself, for example, that the GPU of the physical device accesses a GPU memory.

For example, in the case of virtualization, access to a storage device by a virtual device is divided into host-side access of the virtual device and device-side access of the virtual device. The host-side access of the virtual device may be an access by the host of the virtual device to the storage of the target appliance, e.g., an access by the CPU of the virtual device to the GPU memory of the virtual device. The device-side access of the virtual device may be that the target device of the virtual device accesses the storage device of the target device itself, for example, that the GPU of the virtual device accesses the GPU memory.

In the following example, the storage device is taken as a GPU memory as an example for explanation. However, this is merely an example, and embodiments of the present disclosure are not limited thereto. In other embodiments, the target device may also be a device other than a graphics card device, for example, a processing device including a CPU and a CPU memory, and the storage device may be the CPU memory, which is not limited in this embodiment of the present disclosure.

Fig. 1 illustrates a schematic diagram of accessing an on-chip cache space in a non-virtualized situation provided by at least one embodiment of the present disclosure. As shown in fig. 1, in a non-virtualized case, the storage apparatus 10 may include a memory space 11, and in order to realize the access of the physical apparatus to the on-chip cache, the size of the memory space 11 of the target device must be increased, for example, an on-chip cache space 12 is added, and the on-chip cache space 12 is different from the memory space 11 of the device, so that the host and the target device have the capability of accessing the on-chip cache. For example, a physical device may access the storage device 10, and the host side access of the physical device is consistent with the space that the device side can access, e.g., both the memory space 11 and the on-chip cache space 12 may be accessed. Therefore, under the non-virtualization technology, additional hardware and memory space of the storage device need to be added to realize the access of the on-chip cache. Similarly, the same problem is faced in the virtualization technology.

In view of the foregoing problems, a detailed description is provided below with reference to the accompanying drawings for a configuration method of an on-chip cache space under virtualization according to an embodiment of the present disclosure.

Fig. 2 illustrates a flowchart of a configuration method applied to an on-chip cache space of a computing device according to at least one embodiment of the present disclosure.

As shown in fig. 2, the method may include steps S110 to S120.

Step S110: partitioning at least one partitioned memory space for at least one virtual device in a memory space of a storage device of a computing device; the partitioned memory space includes a first memory subspace configured to be accessed by at least the virtual device in a memory manner and a second memory subspace configured to be accessed by the physical device but not the virtual device in the memory manner.

Step S120: and dividing a third memory subspace in the second memory subspace, configuring the third memory subspace as an on-chip cache space of the virtual device, and accessing the on-chip cache space by the virtual device in a cache mode.

For step S110, for example, fig. 3 shows a schematic diagram of a partitioned storage device provided by at least one embodiment of the present disclosure.

For example, as shown in fig. 3, a computing device may have multiple virtual appliances created therein, for example, 4 virtual appliances created: virtual device a, virtual device b, virtual device c, and virtual device d. Of course more or fewer virtual devices may be provided. For clarity and conciseness, the following description takes the example of creating the above 4 virtual devices as a virtual device, and the embodiment of the present disclosure is not limited thereto. In the memory space of the storage device 20 of the computing apparatus, a plurality of partitioned memory spaces 21 corresponding to the plurality of virtual devices are respectively partitioned for the plurality of virtual devices, and one virtual device corresponds to one partitioned memory space 21. For example, the memory space may be divided according to the number of virtual devices, and 4 divided memory spaces 21 may be divided corresponding to 4 virtual devices. For example, the size of each of the partitioned memory spaces 21 may be the same or different, and the specific partitioning manner may be determined according to actual situations, which is not limited in this embodiment of the disclosure.

For example, each of the partitioned memory spaces 21 includes a first memory subspace 211 and a second memory subspace 212, and the first memory subspace 211 can be accessed by the virtual device in a memory manner, i.e., can respond to a request initiated by the virtual device for accessing the memory. The second memory subspace 212 is occupied by a physical device and can respond to a memory access request initiated by the physical device, but cannot be accessed by the virtual device in a memory manner, i.e., cannot respond to a memory access request initiated by the virtual device. For example, the first memory subspace 211 may also be accessed by a physical device in some cases, which will be described in detail below and will not be described herein.

For example, the storage device 20 may be partitioned by a plurality of virtual devices and one physical device, for example, the plurality of virtual devices are a plurality of logical computers that can be simultaneously run on the physical device.

For example, the memory space corresponding to each virtual device may form a split memory subspace 21, and each virtual device may access its corresponding first memory subspace 211. The memory occupied by the physical devices may be uniformly distributed into a corresponding number of second memory subspaces 212 according to the number of virtual devices, where each second memory subspace 212 corresponds to one first memory subspace 211. Each virtual device may access its own corresponding first memory subspace 211 and a physical device may access any one of the second memory subspaces 212. But each second memory subspace 212 is not accessible by the virtual devices in a memory manner, i.e., is not responsive to any virtual device initiated access request to memory.

Fig. 4 illustrates a schematic diagram of a physical device and a virtual device accessing a storage device according to at least one embodiment of the present disclosure.

For example, as shown in fig. 4, taking a split memory space as an example for description, the access of a virtual device to a storage device is divided into a host side access and a device side access, and for the host side access and the device side access of the virtual device, only the first memory subspace 211 allocated to the virtual device can be accessed in a memory manner, that is, the memory space addresses that can be accessed by the host side and the device side of the virtual device are only the address range between [ MEM _ BASE, MEM _ M ], otherwise, an error is reported.

For example, the access of the physical device to the storage device is also divided into host side access and device side access, and the device side of the physical device can access the entire memory space of the storage device, including the memory space (the second memory subspace 212) allocated to the physical device and the memory space (the first memory subspace 211) accessible by the virtual device, i.e., the address range between the memory space addresses [ MEM _ BASE, MEM _ SIZE ] accessible by the device side of the physical device. The host side of the physical device can only access the second memory subspace 212, i.e. the memory space addresses that the host side of the physical device can access are in the address range between [ MEM _ M, MEM _ SIZE ], otherwise an error is reported.

For step S120, for example, the third memory subspace is multiplexed as the on-chip cache space of the virtual device, that is, the third memory space may be accessed by the physical device, or may be accessed by the virtual device in a cache manner.

Fig. 5 illustrates a schematic diagram of a third memory subspace provided by at least one embodiment of the present disclosure. As shown in fig. 5, for each second memory subspace 212, at least one third memory subspace 213 may be partitioned therefrom, the third memory subspace 213 being a memory space accessible by a physical device, and at the same time, the third memory subspace 213 is multiplexed as an on-chip cache space of a virtual device. The third memory subspace 213 may be accessed by the virtual device in a cached manner, i.e. may be responsive to an access request by the virtual device to the on-chip cache.

For example, the third memory subspace 213 may be smaller than the second memory subspace 212, i.e., a part of the second memory subspace 212 may be used as the third memory subspace 213, i.e., a part of the second memory subspace 212 may be multiplexed as the on-chip cache space. In another example, the third memory subspace 213 may be equal to the second memory subspace 212, i.e., the second memory subspace 212 is entirely used as the third memory subspace 213, i.e., the entire space of the second memory subspace 212 is multiplexed as the on-chip cache space. The ratio of the third memory subspace 213 to the second memory subspace 212 may be determined according to practical situations, and the embodiment of the present disclosure is not limited thereto.

For example, the third memory subspace 213 may be addressed consecutively with the first memory subspace 211. As shown in fig. 4 and fig. 5, the start address of the first memory subspace 211 is, for example, MEM _ BASE, and the end address is, for example, MEM _ M, if the third memory subspace 213 and the first memory subspace 211 are addressed consecutively, the start address BUF _ OFFSET of the third memory subspace 213 is the end address of the first memory subspace 211, that is, BUF _ OFFSET and MEM _ M are the same address. If the SIZE of the third memory subspace 213 is BUF _ SIZE, the termination address of the third memory subspace 213 is BUF _ OFFSET + BUF _ SIZE.

In another example, the third memory subspace 213 and the first memory subspace 211 may also be addressed non-consecutively. Fig. 6 illustrates a schematic diagram of discontinuous addressing of the third memory subspace and the first memory subspace, which is provided by at least one embodiment of the present disclosure. As shown in fig. 6, for example, the starting address of the first memory subspace 211 is, for example, MEM _ BASE, and the ending address is, for example, MEM _ M. The starting address of the third memory subspace 213 is, for example, BUF _ OFFSET, and the ending address is, for example, BUF _ OFFSET + BUF _ SIZE. If the third memory subspace 213 and the first memory subspace 211 are not addressed consecutively, the end address MEM _ M of the first memory subspace 211 is different from the start address BUF _ OFFSET of the third memory subspace 213, and there is another address spaced between them, which can only be accessed by physical devices but not by virtual devices.

For example, in one example, cached access by the virtual appliance may include: the method includes accessing in a virtual appliance in a cached manner from a device side of the virtual appliance, and accessing in a virtual appliance in a cached manner from a host side of the virtual appliance. For example, both the host side and the device side of the virtual appliance may access the third memory subspace 213 in a cached manner.

For example, in another example, cached access by the virtual appliance may include: the access is in a cache manner from the device side of the virtual device in the virtual device or from the host side of the virtual device in the virtual device.

For example, the third memory subspace 213 may be accessed in a cached manner by one of the host side and the device side of the virtual apparatus, but not by the other.

For example, as shown in fig. 5, the device side of the virtual device may access the third memory subspace 213 in a cached manner, while the host side of the virtual device may not access the third memory subspace 213 in a cached manner. In this case, the host side of the virtual device may access the first memory subspace 211 in a memory manner, and the address of the access request to the memory initiated by the host side of the virtual device may be an address between [ MEM _ BASE, BUF _ OFFSET ]. The device side of the virtual device may access the first memory subspace 211 in a memory manner, and may access the third memory subspace 213 in a cache manner, where an address of a memory access request initiated by the device side of the virtual device may be an address between [ MEM _ BASE, BUF _ OFFSET ], and if the third memory subspace 213 includes an address range of [ BUF _ OFFSET, BUF _ OFFSET + BUF _ SIZE ], an address of an access request initiated by the device side of the virtual device to the on-chip cache may be an address between [ BUF _ OFFSET, BUF _ OFFSET + BUF _ SIZE ].

In another example, the host side of the virtual device may access the third memory subspace 213 in a cached manner, while the device side of the virtual device may not access the third memory subspace 213 in a cached manner. The user may set the device side or the host side of the virtual device according to actual requirements to access the third memory subspace 213 in a cache manner, which is not limited in the embodiment of the present disclosure.

For example, the device side of the physical device may access all physical memory spaces in the partitioned memory space, and the address of the memory access request initiated by the device side of the physical device may be an address between [ MEM _ BASE, MEM _ SIZE ]. The host side of the physical device may access the first memory subspace 211, and the address of the memory access request initiated by the host side of the physical device may be an address between [ BUF _ OFFSET, MEM _ SIZE ].

For example, the address space that cannot be accessed by the virtual device (the second memory subspace 212) is divided into a slice region to be multiplexed as an address region of the on-chip buffer, so that the on-chip buffer can be accessed by the virtual device in a cache manner, that is, the address space is multiplexed to perform the addressing operation of the on-chip buffer by using the characteristic that the space cannot be used for accessing the memory under the virtual device. If the mechanism is not adopted, a new address needs to be newly created in a PCIE (peripheral component interconnect express) space, and according to the stipulation that the PCIE address space is 2n, the space needs to be doubled, which causes too much overhead.

It should be noted that, in the embodiment of the present disclosure, the split memory space, the first sub memory space, the second memory sub space, and the third memory sub space may be used for storing addresses, and the virtual device and the physical device further access target data pointed by the addresses according to the addresses by accessing the addresses in the above spaces; of course, the target data may also be directly stored, and the embodiment of the disclosure is not limited thereto.

In at least one embodiment of the present disclosure, under the condition that no additional hardware and physical address space are added, the characteristic that the physical memory address space can be multiplexed is utilized, and a part of the physical memory address space is multiplexed as the on-chip cache space to be provided for a user of the virtual machine, so that the user of the virtual machine can access the on-chip cache space as the physical memory is accessed, and other operations are performed, the operation mode is simple, the complexity of hardware design and software use is reduced, and the performance of the computing device under virtualization is improved. In addition, the on-chip cache space is placed in the physical address space, so that the usability of the on-chip cache is improved, and the physical memory space of each virtual machine is independent, so that the on-chip cache space can also ensure good isolation.

At least one embodiment of the present disclosure further provides an access method for an on-chip cache space, where the on-chip cache space may be configured based on the configuration method for the on-chip cache space of any of the embodiments.

Fig. 7 illustrates a flowchart of an access method provided by at least one embodiment of the present disclosure. As shown in fig. 7, the access method includes steps S310 to S340.

Step S310: responding to the access request for the partitioned memory space, wherein the access request is from the virtual device, and judging whether the address of the access request exceeds a first memory subspace; if not, go to step S320; if so, step S330 is performed.

Step S320: the first memory subspace is accessed by the virtual device in a memory manner in response to the address of the access request being located in the first memory subspace.

Step S330: judging whether the address of the access request exceeds a third memory subspace; if yes, go to step S340; if not, step S350 is performed.

Step S340: accessing, by the virtual device, the third memory subspace in a cached manner.

Step S350: and reporting an error.

It should be noted that "more than … space" described in the embodiments of the present disclosure may be understood as "not located in … space", "not located in … space", and the like, and correspondingly, "not more than … space", "not more than … space" may be understood as "located in … space", "in … space", and the like. For example, an address of an access request exceeding the first memory subspace may be understood as an address of an access request not being within the first memory subspace, including a case where the address of the access request is greater than a maximum address of the first memory subspace and a case where the address of the access request is less than a minimum address of the first memory subspace. For another example, referring to FIG. 6, the address of the access request exceeding the third memory subspace 213 may be that the address of the access request does not belong to an address between [ BUF _ OFFSET, BUF _ OFFSET + BUF _ SIZE ], including a case where the address of the access request is greater than BUF _ OFFSET + BUF _ SIZE and a case where the address of the access request is less than BUF _ OFFSET.

For example, the access method may further include, before step S310, step S301: it is determined whether the access request to the partitioned memory space is from a physical device or a virtual device. If the access request is from the virtual device, step S310 is executed to determine whether the address of the access request is located in the first memory subspace.

For example, referring to fig. 5, in step S310, it is determined whether the address of the access request is located between [ MEM _ BASE, BUF _ OFFSET ]. If the address of the access request is located in the first memory subspace, then in response to the address of the access request being located in the first memory subspace, step S320 is executed, in which the virtual device accesses the first memory subspace 211 in a memory manner. If the address of the access request exceeds the first memory subspace, i.e. the address of the access request is not in the first memory subspace, then in response to the address of the access request exceeding the first memory subspace, step S330 is executed to determine whether the address of the access request exceeds the third memory subspace, i.e. whether the address of the access request is in the first memory subspace, for example, referring to fig. 5, determine whether the address of the access request is in [ BUF _ OFFSET, BUF _ OFFSET + BUF _ SIZE ]. If the address of the access request does not exceed the third memory subspace 213, i.e. the address of the access request is located in the third memory subspace, it is characterized that the virtual device requests to access the on-chip cache space, and in response to the address of the access request being located in the third memory subspace, step S340 is executed, i.e. the virtual device accesses the third memory subspace 213 in a cache manner. If the address of the access request exceeds the third memory subspace 213, i.e. the address of the access request is not in the third memory subspace, the address of the access request does not belong to the address space accessible by the virtual device, and the address is illegal, step S350 is executed, i.e. an error is reported in response to the address of the access request exceeding the third memory subspace (the address of the access request is not in the third memory subspace). The error reporting may be, for example, returning error information for the access request, and the like, which is not limited in this regard by the embodiments of the present disclosure.

For example, as shown in FIG. 7, the access method may further include S360-S380.

Step S360: responding to the access request for the partitioned memory space, namely the access request from the physical device, and judging whether the address of the access request exceeds the partitioned memory space; if so, go to step S370; if not, step S380 is executed.

Step S370: the partitioned memory space is accessed by a physical device.

Step S380: and reporting an error.

For example, if the access request is from a physical device, step S360 is executed to determine whether the address of the access request is located in the split memory space, for example, referring to fig. 5, whether the address of the access request is located between [ MEM _ BASE, MEM _ SIZE ]. If the address of the access request is located in the partitioned memory space, S370 is executed, that is, the partitioned memory space is accessed by the physical device in response to the address of the access request being located in the partitioned memory space; if the address of the access request exceeds the partitioned memory space (the address of the access request is not in the partitioned memory space), the address of the access request does not belong to the space accessible by the physical device, and step S380 is executed, that is, an error is reported in response to the address of the access request exceeding the partitioned memory space (the address of the access request is not in the partitioned memory space).

For example, the access request from the physical device and the access request from the virtual device include a device side access request and a host side access request, respectively. The device side access request of the physical device is configured to access the partitioned memory space from the device side of the physical device, and the host side access request of the physical device is configured to access the second memory subspace from the host side of the physical device. The device side access request of the virtual device is configured to access the first memory subspace and the third memory subspace from the device side of the virtual device in a memory manner, and the host side access request of the virtual device is configured to access the first memory subspace and the third memory subspace from the host side of the virtual device in a memory manner.

For example, as described above, in one example, both the host side and the device side of the virtual appliance may access the third memory subspace 213 in a cached manner at the same time. For example, the host side and the device side of the virtual appliance may access the third memory subspace 213 at the same time, rather than only one of the host side and the device side.

In this case, when an access request of the virtual device is received, it is determined whether an address of the access request exceeds the first memory subspace, and the first memory subspace is accessed by the virtual device in a memory manner in response to the address of the access request being located in the first memory subspace. For example, if the access request is initiated by the device side of the virtual device, the device side accesses the first memory subspace in a memory mode; and if the access request is initiated by the host side of the virtual device, the host side accesses the first memory subspace in a memory mode. And if the address of the access request exceeds the first memory subspace, judging whether the address of the access request exceeds a third memory subspace, and responding to the situation that the address of the access request is located in the third memory subspace, and accessing the third memory subspace by the virtual device in a cache mode. For example, if the access request is initiated by the device side of the virtual device, the device side accesses the third memory subspace in a cache manner; if the device side accesses the third memory subspace and the host side of the virtual device initiates an access request, the host side may also access the third memory subspace in a cache manner. If the address of the access request also exceeds the third memory subspace, an error may be reported.

For example, as described above, in another example, the third memory subspace may be accessed in a cached manner by one of the host side and the device side of the virtual apparatus, but not by the other. For example, in some examples, step S310 is described below by taking as an example that the third memory subspace is accessible by the device side of the virtual device in a cache manner, but is not accessible by the host side of the virtual device in a cache manner.

Fig. 8 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure. For example, fig. 8 is a flowchart of an example of step S310 shown in fig. 7, and for example, as shown in fig. 8, step S310 may include step S311 to step S313.

Step S311: determining whether the access request from the virtual device is a device side access request of the virtual device or a host side access request of the virtual device; if the access request is a device side access request of the virtual device, step S312 is executed; if the access request is a host side access request of the virtual device, step S313 is performed.

Step S312: judging whether the address of the access request exceeds the first memory subspace, if so, executing the step S321; if not, step S331 is performed.

Step S313: judging whether the address of the access request exceeds a first memory subspace, if so, executing a step S352; if not, step S322 is performed.

For example, after determining that the access request is from the virtual device in step S301, step S311 is performed to determine whether the access request from the virtual device is a device side access request of the virtual device or a host side access request of the virtual device.

For example, if the access request is a device-side access request of the virtual device, step S312 is executed to determine whether the address of the access request exceeds the first memory subspace (whether the address of the access request is located in the split memory space) in response to the access request being a device-side access request of the virtual device. If the address of the access request is located in the first memory subspace, step S321 is executed, and in response to that the address of the access request is located in the first memory subspace, the virtual device accesses the first memory subspace in a memory manner, for example, the device side of the virtual device accesses the first memory subspace in a memory manner. If the address of the access request exceeds the first memory subspace (the address of the access request is not in the first memory subspace), step S331 is executed to determine whether the address of the access request exceeds the third memory subspace (whether the address of the access request is in the third memory subspace) in response to the address of the access request exceeding the first memory subspace. If the address of the access request is located in the third memory subspace, step S341 is executed, and in response to that the address of the access request is located in the third memory subspace, the virtual device accesses the third memory subspace in a cache manner, for example, the device side of the virtual device accesses the third memory subspace in a cache manner. If the address of the access request exceeds the third memory subspace (the address of the access request is not in the third memory subspace), step S351 is executed to report an error. For example, step 321, step 331, step 341, and step 351 are the same as step S310 to step S350 in fig. 7, and are not repeated herein.

For example, if the access request is a host-side request of the virtual device, step S313 is executed to determine whether the address of the access request exceeds the first memory subspace in response to the access request being a host-side access request of the virtual device. If not, that is, the address of the access request is located in the first memory subspace, then step S322 is executed, in response to the address of the access request being located in the first memory subspace, the virtual device accesses the first memory subspace in a memory manner, for example, the host side of the virtual device accesses the first memory subspace in a memory manner; if so, that is, the address of the access request exceeds the first memory subspace (the address of the access request is not in the first memory subspace), step S352 is executed to report an error in response to the address of the access request exceeding the first memory subspace.

For example, in other examples, step S310 is described below with an example that the third memory subspace can be accessed by the host side of the virtual device in a cache manner, but cannot be accessed by the device side of the virtual device in a cache manner.

Fig. 9 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure. For example, fig. 9 is a flowchart of another example of step S310 shown in fig. 7. For example, as shown in fig. 9, step S310 may include steps S314 to S316.

Step S314: determining whether the access request from the virtual device is a device-side access request of the virtual device or a host-side access request of the virtual device, and if the access request is a host-side request of the virtual device, performing step S315; if the access request is a device side request of the virtual device, step S316 is executed.

Step S315: judging whether the address of the access request exceeds the first memory subspace, if so, executing the step S323; if not, step S332 is performed.

Step S316: judging whether the address of the access request exceeds the first memory subspace, if so, executing the step S354; if not, step S324 is performed.

For example, after determining that the access request is from the virtual device in step S301, step S314 is performed to determine whether the access request from the virtual device is a device side access request of the virtual device or a host side access request of the virtual device.

For example, if the access request is a host-side request of the virtual device, step S315 is executed to determine whether the address of the access request exceeds the first memory subspace (whether the address of the access request is located in the first memory subspace) in response to the access request being a host-side access request of the virtual device. If not, i.e. the address of the access request is located in the first memory subspace, step S323 is executed, in response to the address of the access request being located in the first memory subspace, accessing the first memory subspace memory-wise by the virtual device, e.g. by the host side of the virtual device. If so, that is, the address of the access request exceeds the first memory subspace (the address of the access request is not in the first memory subspace), step S332 is executed to determine whether the address of the access request exceeds the third memory subspace in response to the address of the access request exceeding the first memory subspace. If the address of the access request is located in the third memory subspace, step S342 is executed, and in response to that the address of the access request is located in the third memory subspace, the virtual device accesses the third memory subspace in a cache manner, for example, the host side of the virtual device accesses the third memory subspace in a cache manner. If the address of the access request exceeds the third memory subspace (the address of the access request is not in the third memory subspace), step S353 is executed to report an error in response to the address of the access request exceeding the third memory subspace. For example, step 323, step 332, step 342, and step S353 are the same as step S310 to step S350 in fig. 7, and are not repeated herein.

For example, if the access request is a device-side request of the virtual device, step S316 is executed to determine whether the address of the access request exceeds the first memory subspace in response to the access request being a device-side access request of the virtual device. If not, that is, the address of the access request is located in the first memory subspace, step S324 is executed, and in response to the address of the access request being located in the first memory subspace, the virtual device accesses the first memory subspace in a memory manner, for example, the device side of the virtual device accesses the first memory subspace in a memory manner. If so, i.e. the address of the access request exceeds the first memory subspace (the address of the access request is not in the first memory subspace), step S354 is executed to report an error in response to the address of the access request exceeding the first memory subspace.

Fig. 10 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure. For example, fig. 10 is a flowchart of an example of step S360 shown in fig. 7. For example, as shown in fig. 10, step S360 may include steps S361 to S363.

Step S361: determining whether the access request from the physical device is a device-side access request of the physical device or a host-side access request of the physical device, and if the access request is a device-side access request of the physical device, performing step S362; if the access request is a host side access request of the physical device, step S363 is executed;

step S362: judging whether the address of the access request exceeds the partitioned memory space;

step S363: it is determined whether the address of the access request exceeds the second memory subspace.

For example, after determining that the access request is from the physical device in step S301, step S361 is executed to determine whether the access request from the physical device is a device side access request of the physical device or a host side access request of the physical device.

If the access request is a device-side access request of the physical device, step S362 is executed to respond to the access request being a device-side access request of the physical device, and determine whether an address of the access request exceeds the split memory space. If so, that is, the address of the access request does not exceed the split memory space (the address of the access request is located in the split memory space), step S371 is executed, and in response to that the address of the access request is located in the split memory space, the split memory space is accessed by the physical device, for example, the device side of the physical device accesses the first memory space or the second memory space. If the address of the access request exceeds the split memory space (the address of the access request is not in the split memory space), step S381 is executed, and an error is reported in response to the address of the access request exceeding the split memory space.

If the access request is a host side access request of the physical device, step S363 is executed to respond that the access request is a host side access request of the physical device, and determine whether an address of the access request exceeds the second memory subspace. If the address of the access request does not exceed the second memory subspace (the address of the access request is located in the second memory subspace), step S372 is executed to access the second memory subspace by the physical device, for example, the host side of the physical device, in response to the address of the access request being located in the second memory subspace. If the address of the access request exceeds the second memory subspace (the address of the access request is not in the second memory subspace), step S382 is executed to report an error in response to the address of the access request exceeding the second memory subspace.

The above describes an example of determining an access manner by first determining whether an access request is from a virtual device or a physical device, then determining whether the access request is a device-side access request or a host-side access request, and determining an access manner in accordance with an address range to which an address of the access request belongs, the access request being from the virtual device or the physical device, the device side or the host side, and the access request.

In another example of the present disclosure, it may be determined whether the access request is a device side access request or a host side access request, and then it is determined whether the access request is from a virtual device or a physical device, and the access manner is determined in combination with the address range to which the address of the access request belongs, and the access request is from the device side or the host side, the virtual device or the physical device.

Fig. 11 illustrates a flow chart of another access method provided by at least one embodiment of the present disclosure. As shown in fig. 11, before determining whether an address of an access request exceeds a first memory subspace in response to an access request for the partitioned memory space being an access request from a virtual device, step S401 may be included: and judging whether the access request for the partitioned memory space is a device side access request or a host side access request.

For example, the access method may further include step S402 and step S403.

Step S402: in response to the access request being a host side access request, determining whether the host side access request is an access request from a physical device or an access request from a virtual device; if the host side access request is an access request from a virtual device, step S403 is performed;

step S403: judging whether the address of the access request exceeds a first memory subspace, if not, executing a step S407; if so, step S405 is performed.

In the case where the access request is a host-side access request, step S402 is executed: in response to the access request being a host side access request, it is determined whether the host side access request is an access request from a physical device or an access request from a virtual device. If the access request is from a virtual device, step S403 is performed: in response to a host-side access request for the partitioned memory space being an access request from a virtual device, determining whether an address of the access request exceeds a first memory subspace.

For example, in some examples, the host side of the virtual device may access the third memory subspace in a cached manner, while the device side of the virtual device may not access the third memory subspace in a cached manner.

In this case, as shown in fig. 11, the access method may further include steps S404 to S407. In case the address of the access request does not exceed the first memory subspace (the address of the access request is located within the first memory subspace), step S404 is performed, in response to the address of the access request being located within the first memory subspace, accessing the first memory subspace memory-wise by the virtual device, e.g. by the host side of the virtual device. If the address of the access request exceeds the first memory subspace (the address of the access request is not in the first memory subspace), step S405 is executed to determine whether the address of the access request exceeds the third memory subspace in response to the address of the access request exceeding the first memory subspace. If the address of the access request does not exceed the third memory subspace (the address of the access request is located in the third memory subspace), step S406 is executed, and in response to that the address of the access request is located in the third memory subspace, the virtual device accesses the third memory subspace in a cache manner, for example, the host side of the virtual device accesses the third memory subspace in a cache manner. If the address of the access request exceeds the third memory subspace, step S407 is executed to report an error in response to the address of the access request exceeding the third memory subspace (the address of the access request is not in the first memory subspace). For example, steps 404 to 407 are the same as steps S310 to S350 in fig. 7, and are not described herein again.

For example, if it is determined in step S402 that the access request is from a physical device, the access method may further include steps S408 to S410, as shown in fig. 11. Step S408: and in response to the host side access request being an access request from a physical device, determining whether an address of the access request exceeds a second memory subspace. If the address of the access request does not exceed the second memory subspace (the address of the access request is located in the second memory subspace), step S409 is executed, and in response to that the address of the access request is located in the second memory subspace, the physical device accesses the second memory subspace in a memory manner, for example, the host side of the physical device accesses the second memory subspace. If the address of the access request exceeds the second memory subspace (the address of the access request is not in the second memory subspace), step S410 is executed to report an error in response to the address of the access request exceeding the second memory subspace.

For example, in this example, if it is determined in step S401 that the access request is a device side access request, as shown in fig. 12, the access method may further include steps S411 to S417.

Step S411: in response to the access request being a device-side access request, determining whether the device-side access request is an access request from a physical apparatus or an access request from a virtual apparatus, and if the device-side access request is a device-side access request of the virtual apparatus, performing step S412; if the device-side access request is a device-side access request of a physical apparatus, step S415 is executed.

Step S412: judging whether the address of the access request exceeds a first memory subspace; if not, go to step S413; if so, step S414 is performed.

Step S413: the first memory subspace is accessed by the virtual device in a memory manner. The first memory subspace is accessed in memory, for example by the device side of the virtual appliance.

Step S414: and reporting an error.

Step S415: judging whether the address of the access request exceeds the split memory space, if so, executing step S416; if not, step S417 is performed.

Step S416: the partitioned memory space is accessed by a physical device.

The first memory subspace or the second memory subspace is accessed, for example, by a device side of the physical apparatus.

Step S417: and reporting an error.

Fig. 13 is a flow chart illustrating another access method provided by at least one embodiment of the present disclosure. As shown in fig. 13, before determining whether an address of an access request exceeds a first memory subspace in response to an access request for a partitioned memory space being an access request from a virtual device, step 401 may be included: and judging whether the access request for the partitioned memory space is a device side access request or a host side access request.

For example, the access method may further include step S502 and step S503.

Step S502: it is determined whether the device side access request is an access request from a physical apparatus or an access request from a virtual apparatus, and if the device side access request is an access request from a virtual apparatus, step S503 is executed.

Step S503: it is determined whether the address of the access request exceeds the first memory subspace.

If the access request is a device-side access request, step S502 is executed: in response to the access request being a device side access request, it is determined whether the device side access request is an access request from a physical device or an access request from a virtual device. If the access request is from the virtual device, step S503 is executed: and in response to the device side access request for the partitioned memory space being an access request from the virtual device, determining whether the address of the access request exceeds the first memory subspace.

For example, in some examples, the device side of the virtual device may access the third memory subspace in a cache manner, while the host side of the virtual device may not access the third memory subspace in a cache manner, in which case, as shown in fig. 13, the access method may further include steps S504 to S507. In case the address of the access request does not exceed the first memory subspace (the address of the access request is located within the first memory subspace), step S504 is performed, in response to the address of the access request being located within the first memory subspace, accessing the first memory subspace memory-wise by the virtual device, e.g. by the device side of the virtual device. If the address of the access request exceeds the first memory subspace (the address of the access request is not in the first memory subspace), step S505 is executed to determine whether the address of the access request exceeds the third memory subspace in response to the address of the access request exceeding the first memory subspace. If the address of the access request does not exceed the third memory subspace (the address of the access request is located in the third memory subspace), step S506 is executed, and in response to that the address of the access request is located in the third memory subspace, the virtual device accesses the third memory subspace in a cache manner, for example, the device side of the virtual device accesses the third memory subspace in a cache manner. If the address of the access request exceeds the third memory subspace (the address of the access request is not in the third memory subspace), step S507 is executed to report an error in response to the address of the access request exceeding the third memory subspace.

For example, if it is determined in step S502 that the access request is from a physical device, the access method may further include steps S508 to S510, as shown in fig. 13. Step S508: and responding to the access request from the physical device of the equipment side, and judging whether the address of the access request exceeds the partitioned memory space. If the address of the access request does not exceed the split memory space (the address of the access request is located in the split memory space), step S509 is executed, and in response to that the address of the access request is located in the split memory space, the physical device accesses the split memory space in a memory manner, for example, the device side of the physical device accesses the first memory subspace or the second memory subspace. If the address of the access request exceeds the partitioned memory space (the address of the access request is not in the partitioned memory space), step S510 is executed, and an error is reported in response to the address of the access request exceeding the partitioned memory space.

For example, if it is determined in step S401 that the access request is a host-side access request, as shown in fig. 14, the access method may further include steps S511 to S517.

Step S511: in response to the access request being a host-side access request, determining whether the host-side access request is an access request from a physical device or an access request from a virtual device, and if the access request is a host-side access request from a virtual device, performing step S512; if the access request is a host-side access request of the physical device, step S515 is executed.

Step S512: it is determined whether the address of the access request exceeds the first memory subspace. If not, go to step S513; if so, step S514 is performed.

Step S513: the first memory subspace is accessed by the virtual device in a memory manner.

The first memory subspace is accessed in memory, for example, by a host side of the virtual device.

Step S514: and reporting an error.

Step S515: and responding to the host side access request of the physical device, judging whether the address of the access request exceeds the second memory subspace, and if not, judging whether the address of the access request exceeds the second memory subspace. Step S516 is executed; if so, step S517 is performed.

Step S516: the second memory subspace is accessed by the physical device.

The second memory subspace is accessed, for example, by the host side of the physical device.

Step S517: and reporting an error.

It should be noted that, in the embodiments of the present disclosure, the execution order of the steps of the on-chip cache space configuration method and the access method is not limited, and although the execution process of the steps is described above in a specific order, this does not constitute a limitation to the embodiments of the present disclosure. The various steps in the configuration method and the access method may be performed in series or in parallel, which may depend on the actual requirements. The configuration method and the access method may also include more or fewer steps, and embodiments of the present disclosure are not limited in this respect.

For technical effects of the access method in the embodiment of the present disclosure, reference may be made to technical effects of the configuration method provided in the embodiment of the present disclosure, and details are not described here.

At least one embodiment of the present disclosure further provides a configuration apparatus applied to an on-chip cache space of a computing device, for example, the computing device includes at least one physical apparatus and a storage apparatus, and at least one virtual apparatus is created in the computing device. For specific descriptions of the computing device, the physical device and the storage device, reference may be made to the above description of the method for allocating the on-chip cache space in the embodiment, and details thereof are not repeated herein.

Fig. 15 illustrates a schematic block diagram of a configuration apparatus 600 provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 15, the configuration apparatus 600 includes a first configuration unit 610 and a second configuration unit 620.

The first configuration unit 610 is configured to partition at least one partitioned memory space for at least one virtual device in a memory space of a storage device of the computing device. For example, the partitioned memory space includes a first memory subspace configured to be accessed by at least the virtual device in a memory manner and a second memory subspace configured to be accessed by the physical device but not by the virtual device in the memory manner. For example, the first configuration unit 610 may execute step S110 described in fig. 2, and for a specific description, reference may be made to the related description of step S110, which is not described herein again.

The second configuration unit 620 is configured to partition a third memory subspace in the second memory subspace, and configure the third memory subspace as an on-chip cache space of the virtual device, which is accessed by the virtual device in a cache manner. For example, the second configuration unit 620 may, for example, execute step S120 described in fig. 2, and refer to the related description of step S120 for specific description.

For example, the first configuration unit 610 and the second configuration unit 620 may be hardware, software, firmware, and any feasible combination thereof. For example, the first configuration unit 610 and the second configuration unit 620 may be dedicated or general circuits, chips, devices, or the like, or may be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the on-chip cache space configuration apparatus 600 corresponds to each step of the foregoing on-chip cache space configuration method, and specific functions of the on-chip cache space configuration apparatus 600 may refer to related descriptions about the on-chip cache space configuration method, which are not described herein again. The components and structure of the on-chip cache space configuration apparatus 600 shown in fig. 15 are only exemplary and not limiting, and the on-chip cache space configuration apparatus 600 may further include other components and structures as needed.

At least one embodiment of the present disclosure further provides an access device for an on-chip cache space, where the on-chip cache space is configured by the configuration device of the foregoing embodiment.

Fig. 16 illustrates a schematic block diagram of an access device 700 provided by at least one embodiment of the present disclosure.

For example, as shown in fig. 16, the access device 700 includes a first access unit 710, a second access unit 720, a third access unit 730, and a fourth access unit 740.

The first accessing unit 710 is configured to determine whether an address of an access request exceeds a first memory subspace in response to the access request for the partitioned memory space being an access request from a virtual device. For example, the first accessing unit 710 may, for example, execute step S310 described in fig. 7, and refer to the related description of step S310 for specific introduction.

The second accessing unit 720 is configured to access the first memory subspace in a memory manner by the virtual device in response to the address of the access request being located in the first memory subspace. For example, the second accessing unit 720 may execute step S320 described in fig. 7, for example, and refer to the related description of step S320.

The third access unit 730 is configured to determine whether the address of the access request exceeds the third memory subspace in response to the address of the access request exceeding the first memory subspace. For example, the third accessing unit 730 may execute step S330 described in fig. 7, for example, and refer to the related description of step S330 for specific introduction.

The fourth accessing unit 740 is configured to access the third memory subspace by the virtual device in a cached manner in response to the address of the access request being located in the third memory subspace. For example, the fourth accessing unit 740 may execute step S340 described in fig. 7, and refer to the related description of step S340 for specific description.

For example, first access unit 710, second access unit 720, third access unit 730, and fourth access unit 740 may be hardware, software, firmware, and any feasible combination thereof. For example, the first access unit 710, the second access unit 720, the third access unit 730, and the fourth access unit 740 may be dedicated or general circuits, chips, devices, or the like, or may be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

For example, the access device 700 of the on-chip cache space may further include a fifth access unit and a sixth access unit. For example, the fifth accessing unit is configured to determine whether an address of the access request exceeds the partitioned memory space in response to the access request for the partitioned memory space being an access request from a physical device. The sixth access unit is configured to access the partitioned memory space by the physical device in response to the address of the access request being located in the partitioned memory space, and report an error in response to the address of the access request exceeding the partitioned memory space.

For example, the accessing apparatus 700 of the on-chip cache space may further include a seventh accessing unit. For example, the seventh accessing unit is configured to determine whether the access request for the partitioned memory space is an access request from a physical device or an access request from a virtual device.

It should be noted that, in the embodiment of the present disclosure, each unit of the on-chip cache space access apparatus 700 corresponds to each step of the foregoing on-chip cache space access method, and for a specific function of the on-chip cache space access apparatus 700, reference may be made to the description related to the on-chip cache space access method, which is not described herein again. The components and structure of the on-chip cache space accessing apparatus 700 shown in fig. 16 are exemplary only, and not limiting, and the on-chip cache space accessing apparatus 700 may further include other components and structures as needed.

At least one embodiment of the present disclosure also provides another configuration apparatus applied to an on-chip cache space of a computing device, where the computing device includes at least one physical apparatus and a storage apparatus, at least one virtual apparatus is created in the computing device, the configuration apparatus includes a processor and a memory, and the memory includes one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for implementing the configuration method described above. The configuration device can provide the on-chip cache space for the user of the virtual machine to use without adding extra hardware and physical address space.

Fig. 17 is a schematic block diagram of another configuration apparatus provided in at least one embodiment of the present disclosure. As shown in fig. 17, the configuration means 810 includes a processor 811 and a memory 812. Memory 812 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 811 is configured to execute non-transitory computer readable instructions, which when executed by the processor 811 may perform one or more steps of the configuration method described above. The memory 812 and the processor 811 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

At least one embodiment of the present disclosure also provides another apparatus for accessing an on-chip cache space, the on-chip cache space being configured by the configuration apparatus of any of the above embodiments, the apparatus comprising a processor and a memory, the memory comprising one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for implementing the access method provided by any of the embodiments described above.

Fig. 18 is a schematic block diagram of another access device provided in at least one embodiment of the present disclosure. As shown in fig. 18, the access device 820 includes a processor 821 and a memory 822. The memory 822 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 821 is configured to execute non-transitory computer readable instructions that, when executed by the processor 821, may perform one or more of the steps of the access methods described above. The memory 822 and the processor 821 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, processor 811 and/or processor 821 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. Processor 811 and/or processor 821 may be a general-purpose processor or a special-purpose processor that may control other components in electronic device 800 to perform desired functions.

For example, memory 821 and/or memory 822 may comprise any combination of one or more computer program products that can include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 811 and/or processor 821 to implement various functions of configuration apparatus 810 and/or access apparatus 820. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the configuration method and/or the access method for specific functions and technical effects of the configuration device 810 and/or the access device 820, which are not described herein again.

Fig. 19 is a schematic block diagram of another configuration device or access device provided in at least one embodiment of the present disclosure. The apparatus 900 is, for example, suitable for implementing the configuration method or the access method provided by the embodiments of the present disclosure. Apparatus 900 may be a terminal device or the like. It should be noted that the apparatus 900 shown in fig. 19 is only an example, and does not bring any limitation to the functions and the scope of the application of the embodiments of the present disclosure.

As shown in fig. 19, the apparatus 900 may include a processing unit (e.g., central processing unit, graphics processor, etc.) 910 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)920 or a program loaded from a storage unit 980 into a Random Access Memory (RAM) 930. In the RAM930, various programs and data necessary for the operation of the apparatus 900 are also stored. The processing unit 910, the ROM 920, and the RAM930 are connected to each other through a bus 940. An input/output (I/O) interface 950 is also connected to bus 940.

Generally, the following devices may be connected to the I/O interface 950: an input unit 960 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output unit 970 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; a storage unit 980 including, for example, a magnetic tape, a hard disk, and the like; and a communication unit 990. The communication unit 990 may allow the apparatus 900 to communicate with other electronic devices wirelessly or by wire to exchange data. While fig. 19 shows the device 900 having various elements, it is to be understood that it is not required that all of the illustrated elements be implemented or provided, and that the device 900 can alternatively be implemented or provided with more or less elements.

For example, according to an embodiment of the present disclosure, the above-described configuration method or access method may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the above-described configuration method or access method. In such an embodiment, the computer program may be downloaded and installed from a network through the communication unit 990, or installed from the storage unit 980, or installed from the ROM 920. When executed by the processing unit 910, the computer program may implement the functions defined in the configuration method or the access method provided by the embodiments of the present disclosure.

At least one embodiment of the present disclosure further provides a virtualization system of a computing device, including the configuration apparatus of any of the above embodiments or the access apparatus of any of the above embodiments, at least one physical apparatus, and at least one virtual apparatus.

For example, the physical device is configured to access the partitioned memory space or the second memory subspace. The virtual device is configured to access the first memory subspace in a memory manner and to access the third memory subspace in a cache manner.

At least one embodiment of the present disclosure also provides a computer-readable storage medium that non-transitory stores computer-readable instructions that, when executed by a computer, can implement the configuration method or the access method described above. With the computer-readable storage medium, on-chip cache space can be made available to users of virtual machines without adding additional hardware and physical address space.

Fig. 20 is a schematic diagram of a storage medium according to at least one embodiment of the present disclosure. As shown in fig. 20, the storage medium 1000 is for non-transitory storage of computer readable instructions 1010. For example, the non-transitory computer readable instructions 1010, when executed by a computer, may perform one or more steps according to a configuration method or an access method described above.

For example, the storage medium 1000 may be applied to the configuration device 810 or the access device 820. For example, the storage medium 1000 may be the memory 812 in the configuration device 810 shown in fig. 17 or the memory 822 in the access device 820 shown in fig. 18.

For example, the storage medium can be any combination of one or more computer-readable storage media, e.g., in some examples, one computer-readable storage medium comprising program code that partitions a memory space of a storage device of a computing device into at least one partitioned memory space for at least one virtual device, the partitioned memory space including a first memory subspace configured to be memory-accessed by at least the virtual device and a second memory subspace configured to be memory-accessed by a physical device but not the virtual device. Another computer readable storage medium includes program code for partitioning the second memory subspace into a third memory subspace, and configuring the third memory subspace as an on-chip cache space for the virtual device, the on-chip cache space being accessed by the virtual device in a cached manner. For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to perform a configuration method such as that provided by any of the embodiments of the present disclosure.

For example, in other examples, a computer-readable storage medium includes program code to determine whether an address of the access request exceeds the first memory subspace in response to the access request for the partitioned memory space being an access request from the virtual device. Another computer readable storage medium contains program code for accessing, by the virtual device, the first memory subspace in the memory mode in response to the address of the access request being located in the first memory subspace. Another computer readable storage medium contains program code for determining whether an address of the access request exceeds the third memory subspace in response to the address of the access request exceeding the first memory subspace. Another computer readable storage medium contains program code for accessing, by the virtual device, the third memory subspace in the cached manner in response to the address of the access request being located in the third memory subspace. For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to perform an access method such as that provided by any of the embodiments of the present disclosure.

For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above, as well as other suitable storage media.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A configuration method applied to an on-chip cache space of a computing device, wherein the computing device comprises at least one physical apparatus and a storage apparatus, at least one virtual apparatus is created in the computing device, and the method comprises:

partitioning at least one partitioned memory space for the at least one virtual device in a memory space of a storage device of the computing device, wherein the partitioned memory space comprises a first memory subspace configured to be memory-accessed at least by the virtual device and a second memory subspace configured to be memory-accessed by the physical device but not by the virtual device;

and dividing a third memory subspace in the second memory subspace, configuring the third memory subspace as an on-chip cache space of the virtual device, and accessing the on-chip cache space by the virtual device in a cache manner.

2. The configuration method of claim 1, wherein the accessing by the virtual appliance in the cached manner comprises:

in the virtual appliance, access is made in a cached manner from the device side of the virtual appliance, or

Accessing in the virtual device in a cached manner from a host side of the virtual device.

3. The configuration method of claim 1, wherein a plurality of virtual appliances are created in the computing device,

partitioning at least one partitioned memory space for the at least one virtual device from memory spaces of storage devices of the computing device, comprising:

and respectively dividing a plurality of partitioned memory spaces correspondingly used for the plurality of virtual devices in the memory space of the storage device of the computing equipment, wherein one virtual device corresponds to one partitioned memory space.

4. A configuration method according to any of claims 1-3, wherein said third memory subspace is equal to or smaller than said second memory subspace.

5. The configuration method according to any one of claims 1 to 3,

the third memory subspace is addressed consecutively with the first memory subspace; or

The third memory subspace is not addressed consecutively to the first memory subspace.

6. An access method of an on-chip cache space configured based on the configuration method of the on-chip cache space of claim 1,

the access method comprises the following steps:

in response to the access request to the partitioned memory space being an access request from the virtual device, determining whether an address of the access request exceeds the first memory subspace,

accessing, by the virtual device, the first memory subspace in the memory-wise manner in response to the address of the access request being located in the first memory subspace;

in response to the address of the access request exceeding the first memory subspace, determining whether the address of the access request exceeds the third memory subspace,

accessing, by the virtual device, the third memory subspace in the cached manner in response to the address of the access request being located in the third memory subspace.

7. The access method of claim 6, further comprising:

in response to the access request for the partitioned memory space being an access request from the physical device, determining whether an address of the access request exceeds the partitioned memory space,

responding to the address of the access request in the partitioned memory space, and accessing the partitioned memory space by the physical device;

and reporting an error in response to the address of the access request exceeding the partitioned memory space.

8. The access method of claim 7, further comprising:

determining whether the access request to the partitioned memory space is from the physical device or the virtual device.

9. The access method of claim 7, wherein the access request from the physical device and the access request from the virtual device comprise a device-side access request and a host-side access request, respectively;

the device side access request of the physical device is configured to access the partitioned memory space from the device side of the physical device;

the host side access request of the physical device is configured to access the second memory subspace from the host side of the physical device;

the device side access request of the virtual device is configured to access the first memory subspace and the third memory subspace from the device side of the virtual device in a memory manner;

the host side access request of the virtual device is configured to access the first memory subspace in a memory manner and the third memory subspace in a cache manner from the host side of the virtual device.

10. The method of accessing of claim 9, wherein determining whether the address of the access request exceeds the first memory subspace in response to the access request for the partitioned memory space being an access request from the virtual device comprises:

determining whether an access request from the virtual device is a device side access request or a host side access request of the virtual device;

responding to the access request as a device side access request of the virtual device, judging whether the address of the access request exceeds the first memory subspace or not,

accessing, by the virtual device, the third memory subspace in the cached manner in response to the address of the access request being located in the third memory subspace;

in response to the access request being a host-side access request of the virtual device, determining whether an address of the access request exceeds the first memory subspace,

accessing, by the virtual device, to the first memory subspace in the memory manner in response to the address of the access request being located in the first memory subspace;

an error is reported in response to the address of the access request exceeding the first memory subspace.

11. The method of accessing of claim 9, wherein determining whether the address of the access request exceeds the first memory subspace in response to the access request for the partitioned memory space being an access request from the virtual device comprises:

12. The access method according to claim 9, wherein the device side and the host side of the virtual device access the third memory subspace in the cached manner at the same time.

13. The method of accessing of claim 9, wherein determining whether an address of the access request exceeds the partitioned memory space in response to the access request for the partitioned memory space being an access request from the physical device comprises:

judging whether the access request is a device side access request of the physical device or a host side access request of the physical device;

responding to the access request as a device side access request of the physical device, judging whether the address of the access request exceeds the split memory space,

responding to the address of the access request exceeding the segmented memory space, and reporting an error;

responding to the access request as a host side access request of the physical device, judging whether the address of the access request exceeds the second memory subspace or not,

accessing, by the physical device, the second memory subspace in response to the address of the access request being located in the second memory subspace;

reporting an error in response to the address of the access request exceeding the second memory subspace.

14. The method of accessing according to claim 9, wherein before determining whether an address of the access request exceeds the first memory subspace in response to the access request for the partitioned memory space being an access request from the virtual device, further comprising:

and judging whether the access request for the partitioned memory space is a device side access request or a host side access request.

15. The access method of claim 14, further comprising:

in response to the access request being the host side access request, determining whether the host side access request is an access request from the physical device or an access request from the virtual device;

responding to the host side access request for the partitioned memory space to be an access request from the virtual device, and judging whether the address of the access request exceeds the first memory subspace; accessing, by the virtual device, the first memory subspace in the memory-wise manner in response to the address of the access request being located in the first memory subspace; responding to the address of the access request exceeding the first memory subspace, judging whether the address of the access request exceeds the third memory subspace, responding to the address of the access request located in the third memory subspace, and accessing the third memory subspace by the virtual device in a cache mode;

in response to the access request being the device-side access request, determining whether the device-side access request is an access request from the physical device or an access request from the virtual device;

reporting an error in response to the address of the access request exceeding the first memory subspace;

16. The access method of claim 14, further comprising:

responding to the device side access request for the partitioned memory space to be an access request from the virtual device, and judging whether the address of the access request exceeds the first memory subspace; accessing, by the virtual device, the first memory subspace in the memory-wise manner in response to the address of the access request being located in the first memory subspace; responding to the address of the access request exceeding the first memory subspace, judging whether the address of the access request exceeds the third memory subspace, responding to the address of the access request located in the third memory subspace, and accessing the third memory subspace by the virtual device in a cache mode;

17. An access device for an on-chip cache space, wherein the on-chip cache space is configured by the configuration method of claim 1,

the access device includes:

a first access unit configured to determine whether an address of the access request exceeds the first memory subspace in response to the access request for the partitioned memory space being an access request from the virtual device,

a second accessing unit configured to access the first memory subspace in the memory manner by the virtual device in response to an address of the access request being located in the first memory subspace;

a third access unit configured to determine whether the address of the access request exceeds the third memory subspace in response to the address of the access request exceeding the first memory subspace,

a fourth accessing unit configured to access, by the virtual device, the third memory subspace in the cached manner in response to the address of the access request being located in the third memory subspace.

18. An access device of an on-chip cache space, wherein the on-chip cache space is configured by the configuration method of claim 1, the access device comprising:

a processor;

a memory;

one or more computer program modules stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing an access method that implements claim 6.

19. A virtualization system of a computing device, comprising: the access device, at least one physical device, and at least one virtual device of claims 17 or 18; wherein the content of the first and second substances,

the physical device is configured to access the partitioned memory space or the second memory subspace;

the virtual device is configured to access the first memory subspace in the memory mode and the third memory subspace in the cache mode.

20. A storage medium storing, non-transitory, computer-readable instructions that when executed by a computer perform the configuration method of any of claims 1-5 or the access method of any of claims 6-16.