CN113485661A - Four-way server and method for outputting log information by four-way server - Google Patents
Four-way server and method for outputting log information by four-way server Download PDFInfo
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- CN113485661A CN113485661A CN202110748469.3A CN202110748469A CN113485661A CN 113485661 A CN113485661 A CN 113485661A CN 202110748469 A CN202110748469 A CN 202110748469A CN 113485661 A CN113485661 A CN 113485661A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1407—General aspects irrespective of display type, e.g. determination of decimal point position, display with fixed or driving decimal point, suppression of non-significant zeros
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3476—Data logging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a four-way server and a method for outputting log information by the four-way server. Wherein, the four-way server includes: the data conversion device inserts preset designated characters into the first log information, the second log information, the third log information and the fourth log information respectively and is configured into fifth log information, the data conversion chip converts the fifth log information into first log information, second log information, third log information and fourth log information which are matched with data display of the serial communication port, and the serial communication port synchronously displays the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip. By the method, the four-way server can synchronously display the log information of the four-way processor on the four-way server.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a four-way server and a method for outputting log information by the four-way server.
Background
The existing four-path server comprises a first processor, a second processor, a third processor and a fourth processor which are four-path processors; the first processor is used as a main processor to control and integrate the four-path processor, the whole system and peripheral equipment, and the second processor, the third processor and the fourth processor are used as auxiliary processors to process tasks issued by the first processor. The first processor, the second processor, the third processor and the fourth processor are respectively provided with independent debugging serial ports, the first processor can output log information through the debugging serial ports on the first processor, and the second processor, the third processor and the fourth processor can respectively output the log information through the debugging serial ports on the second processor, the third processor and the fourth processor in the power-on self-test stage of the four-path server.
However, the conventional four-way server generally provides only one COM (serial communication port) interface, and can only display the log information output by the first processor, but the log information of the second processor, the third processor and the fourth processor cannot be known, and the four-way server cannot synchronously display the log information of the four-way processor thereon.
Disclosure of Invention
In view of the above, the present invention is directed to a four-way server and a method for outputting log information thereof, which enable the four-way server to synchronously display log information of four-way processors thereon.
According to an aspect of the present invention, there is provided a four-way server, comprising: the system comprises a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip and a serial communication port; the first processor is provided with a first debugging serial port and is used for outputting first log information to the programmable logic device data conversion chip through the first debugging serial port; the second processor is provided with a second debugging serial port and used for outputting second log information to the programmable logic device through the second debugging serial port; the third processor is provided with a third debugging serial port and is used for outputting third log information to the programmable logic device through the third debugging serial port; the fourth processor is provided with a fourth debugging serial port and is used for outputting fourth log information to the programmable logic device through the fourth debugging serial port; the programmable logic device is configured to insert preset designated characters into the first log information, the second log information, the third log information, and the fourth log information, configure the first log information, the second log information, the third log information, and the fourth log information into fifth log information after the preset designated characters are inserted, and send the fifth log information to the data conversion chip; the data conversion chip is used for converting first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port from the fifth log information; and the serial communication port is used for synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to preset designated characters respectively inserted into the fifth buffer.
Wherein the programmable logic device comprises: the device comprises a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter and a serial port output controller; the first buffer is used for buffering the first log information; the second buffer is used for buffering the second log information; the third buffer is used for buffering the third log information; the fourth buffer is used for buffering the fourth log information; the counter is used for respectively carrying out synchronous counting related to the working frequency according to the working frequency of the first processor, the second processor, the third processor and the fourth processor; the fifth buffer is configured to insert preset specified characters into the first log information, the second log information, the third log information, and the fourth log information respectively according to synchronous counting associated with the operating frequency respectively performed by the counter, and configure the first log information, the second log information, the third log information, and the fourth log information into fifth log information after the preset specified characters are inserted; and the serial port output controller is used for sending the fifth log information to the data conversion chip.
Wherein, the counter is specifically configured to: and according to the working frequencies of the first processor, the second processor, the third processor and the fourth processor, respectively carrying out synchronous counting related to the working frequencies in a mode of starting counting by respectively using the same specific cycles of the first debugging serial port, the second debugging serial port, the third debugging serial port and the fourth debugging serial port.
The data conversion chip is specifically configured to: and decomposing first log information, second log information, third log information and fourth log information which are matched with the preset designated characters respectively inserted from the fifth log information through the preset designated characters respectively inserted into the fifth buffer, and converting the decomposed first log information, second log information, third log information and fourth log information into first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port.
Wherein, the serial communication port is specifically used for: and according to the preset designated characters respectively inserted into the fifth buffer, acquiring the starting time and the ending time matched with the preset designated characters respectively inserted, and according to the acquired starting time and ending time, synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip.
According to another aspect of the present invention, there is provided a method for outputting log information by a four-way server, including: the four-path server comprises a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip and a serial communication port; the first processor outputs first log information to the programmable logic device data conversion chip through a first debugging serial port arranged on the first processor, the second processor outputs second log information to the programmable logic device data conversion chip through a second debugging serial port arranged on the second processor, the third processor outputs third log information to the programmable logic device data conversion chip through a third debugging serial port arranged on the third processor, and the fourth processor outputs fourth log information to the programmable logic device data conversion chip through a fourth debugging serial port arranged on the fourth processor; the programmable logic device inserts preset specified characters into the first log information, the second log information, the third log information and the fourth log information respectively, configures the first log information, the second log information, the third log information and the fourth log information into fifth log information after the preset specified characters are inserted, and sends the fifth log information to the data conversion chip; the data conversion chip converts first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port from the fifth log information; and the serial communication port synchronously displays the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to preset designated characters respectively inserted into the fifth buffer.
The method for configuring the data conversion chip by the programmable logic device includes the steps that the programmable logic device inserts preset designated characters into the first log information, the second log information, the third log information and the fourth log information respectively, configures the first log information, the second log information, the third log information and the fourth log information into fifth log information after the preset designated characters are inserted, and sends the fifth log information to the data conversion chip, and includes the steps of: the programmable logic device comprises a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter and a serial port output controller; the first buffer caches the first log information, the second buffer caches the second log information, the third buffer caches the third log information, the fourth buffer caches the fourth log information, the counter respectively performs synchronous counting associated with the working frequency according to the working frequency of the first processor, the second processor, the third processor and the fourth processor, the fifth buffer respectively inserts preset designated characters into the first log information, the second log information, the third log information and the fourth log information according to the synchronous counting associated with the working frequency respectively performed by the counter, and configures the first log information, the second log information, the third log information and the fourth log information after the preset designated characters are inserted into fifth log information, and the serial port output controller sends the fifth log information to the data conversion chip.
Wherein the counter performs synchronous counting associated with the operating frequencies according to the operating frequencies of the first processor, the second processor, the third processor, and the fourth processor, respectively, and includes: and according to the working frequencies of the first processor, the second processor, the third processor and the fourth processor, respectively carrying out synchronous counting related to the working frequencies in a mode of starting counting by respectively using the same specific cycles of the first debugging serial port, the second debugging serial port, the third debugging serial port and the fourth debugging serial port.
The data conversion chip converts the fifth log information into first log information, second log information, third log information and fourth log information which are matched with the serial communication port data display, and the data conversion chip comprises: and decomposing first log information, second log information, third log information and fourth log information which are matched with the preset designated characters respectively inserted from the fifth log information through the preset designated characters respectively inserted into the fifth buffer, and converting the decomposed first log information, second log information, third log information and fourth log information into first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port.
The method for synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip by the serial communication port according to the preset designated characters respectively inserted into the fifth buffer comprises the following steps: and according to the preset designated characters respectively inserted into the fifth buffer, acquiring the starting time and the ending time matched with the preset designated characters respectively inserted, and according to the acquired starting time and ending time, synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip.
It can be found that, in the above solution, the four-way server may include a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip, and a serial communication port, the first processor may be provided with a first debug serial port through which first log information may be output to the programmable logic device data conversion chip, the second processor may be provided with a second debug serial port through which second log information may be output to the programmable logic device, the third processor may be provided with a third debug serial port through which third log information may be output to the programmable logic device, the fourth processor may be provided with a fourth debug serial port through which fourth log information may be output to the programmable logic device, the programmable logic device can insert preset designated characters into the first log information, the second log information, the third log information and the fourth log information respectively, configure the first log information, the second log information, the third log information and the fourth log information after the preset designated characters are inserted into fifth log information and send the fifth log information to the data conversion chip, the data conversion chip can convert the first log information, the second log information, the third log information and the fourth log information which are matched with the data display of the serial communication port from the fifth log information, the serial communication port can synchronously display the first log information, the second log information, the third log information and the fourth log information which are converted by the data conversion chip according to the preset designated characters respectively inserted into the fifth buffer, the four-way server can synchronously display the log information of the four-way processor on the four-way server.
Further, in the above solution, the programmable logic device may include a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter, and a serial output controller, where the first buffer may buffer the first log information, the second buffer may buffer the second log information, the third buffer may buffer the third log information, the fourth buffer may buffer the fourth log information, the counter may perform synchronous counting associated with the operating frequency according to the operating frequency of the first processor, the second processor, the third processor, and the fourth processor, respectively, the fifth buffer may insert preset designated characters for the first log information, the second log information, the third log information, and the fourth log information according to the synchronous counting associated with the operating frequency by the counter, respectively, and configuring the first log information, the second log information, the third log information and the fourth log information after the preset specified character is inserted into fifth log information, wherein the serial port output controller can send the fifth log information to the data conversion chip, so that the advantage of acquiring the log information of a four-way processor which is the same as the first processor, the second processor, the third processor and the fourth processor can be realized.
Further, according to the above scheme, the counter may perform synchronous counting associated with the operating frequencies respectively according to the operating frequencies of the first processor, the second processor, the third processor, and the fourth processor in a manner that the first debugging serial port, the second debugging serial port, the third debugging serial port, and the fourth debugging serial port start counting in the same bit rate cycle respectively, so as to achieve synchronous counting of the operating frequencies of four processors including the first processor, the second processor, the third processor, and the fourth processor, which is associated with each other, and conveniently obtain log information of the four processors completely according to the synchronous counting associated with the operating frequencies respectively.
Further, according to the above aspect, the data conversion chip can separate the first log information, the second log information, the third log information and the fourth log information which match with the respectively inserted preset designated characters from the fifth log information through the respectively inserted preset designated characters, and convert the separated first log information, second log information, third log information and fourth log information into the first log information, the second log information, the third log information and the fourth log information which match with the data display of the serial communication port, which can realize the advantage of facilitating the subsequent synchronous display of the log information of the four-way processor including the first processor, the second processor, the third processor and the fourth processor.
Further, according to the above solution, the serial communication port can obtain the start time and the end time matched with the preset designated characters respectively inserted into the fifth buffer, and synchronously display the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to the obtained start time and end time, which is advantageous in that the log information of a four-way processor including the first processor, the second processor, the third processor and the fourth processor can be synchronously displayed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an embodiment of a four-way server according to the present invention;
fig. 2 is a flowchart illustrating an embodiment of a method for outputting log information by a four-way server according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
The invention provides a four-way server, which can synchronously display log information of a four-way processor on the four-way server.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a four-way server according to an embodiment of the present invention. In this embodiment, the four-way server 10 includes a first processor 11, a second processor 12, a third processor 13, a fourth processor 14, a programmable logic device 15, a data conversion chip 16, and a serial communication port 17.
The first processor 11 is provided with a first debugging serial port (not shown), and is configured to output first log information to the data conversion chip 16 of the programmable logic device 15 through the first debugging serial port.
The second processor 12 is provided with a second debugging serial port (not shown), and is configured to output second log information to the programmable logic device 15 through the second debugging serial port.
The third processor 13 is provided with a third debugging serial port (not labeled in the figure), and is configured to output third log information to the programmable logic device 15 through the third debugging serial port.
The fourth processor 14 is provided with a fourth debugging serial port (not shown in the figure), and is configured to output fourth log information to the programmable logic device 15 through the fourth debugging serial port.
The programmable logic device 15 is configured to insert preset designated characters into the first log information, the second log information, the third log information, and the fourth log information, configure the first log information, the second log information, the third log information, and the fourth log information into fifth log information after the preset designated characters are inserted, and send the fifth log information to the data conversion chip 16.
The data conversion chip 16 is configured to convert the fifth log information into first log information, second log information, third log information and fourth log information that match the data display of the serial communication port 17.
The serial communication port 17 is used for synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip 16 according to the preset designated characters respectively inserted into the fifth buffer 155.
Alternatively, the programmable logic device 15 may include:
a first buffer 151, a second buffer 152, a third buffer 153, a fourth buffer 154, a fifth buffer 155, a counter 156, and a serial output controller 157;
the first buffer 151, for buffering the first log information;
the second buffer 152 is used for buffering the second log information;
the third buffer 153 is configured to buffer the third log information;
the fourth buffer 154, configured to buffer the fourth log information;
the counter 156 is configured to perform synchronous counting related to the operating frequencies of the first processor 11, the second processor 12, the third processor 13, and the fourth processor 14 respectively;
the fifth buffer 155, configured to insert preset specified characters into the first log information, the second log information, the third log information and the fourth log information, respectively, according to the synchronous counting associated with the operating frequency, respectively, performed by the counter 156, and configure the first log information, the second log information, the third log information and the fourth log information after the preset specified characters are inserted into fifth log information;
the serial port output controller 157 is configured to send the fifth log information to the data conversion chip 16;
this has the advantage of enabling the log information of the four-way processor including the first processor 11, the second processor 12, the third processor 13 and the fourth processor 14 to be obtained.
Optionally, the counter 156 may be specifically configured to:
according to the working frequencies of the first processor 11, the second processor 12, the third processor 13 and the fourth processor 14, respectively performing synchronous counting associated with the working frequencies in a mode that the first debugging serial port, the second debugging serial port, the third debugging serial port and the fourth debugging serial port respectively start counting in the same special rate cycle;
this has the advantage of enabling to perform synchronous counting of the operating frequencies of the four-way processors associated with the first processor 11, the second processor 12, the third processor 13, and the fourth processor 14, respectively, and facilitating to completely acquire the log information of the four-way processors according to the performed synchronous counting associated with the operating frequencies, respectively.
Optionally, the data conversion chip 16 may be specifically configured to:
the first log information, the second log information, the third log information and the fourth log information which are matched with the preset designated characters respectively inserted are separated from the fifth log information through the preset designated characters respectively inserted into the fifth buffer 155, and the separated first log information, second log information, third log information and fourth log information are converted into the first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port 17;
this has the advantage of facilitating subsequent simultaneous display of log information for the four-way processor including the first processor 11, the second processor 12, the third processor 13 and the fourth processor 14.
Optionally, the serial communication port 17 may be specifically configured to:
acquiring a start time and an end time matched with the preset designated characters respectively inserted into the fifth buffer 155 according to the preset designated characters respectively inserted into the fifth buffer, and synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip 16 according to the acquired start time and end time;
this has the advantage of enabling the log information of the four-way processor including the first processor 11, the second processor 12, the third processor 13 and the fourth processor 14 to be displayed synchronously.
It can be seen that, in this embodiment, the four-way server may include a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip, and a serial communication port, the first processor may be provided with a first debug serial port through which first log information may be output to the programmable logic device data conversion chip, the second processor may be provided with a second debug serial port through which second log information may be output to the programmable logic device, the third processor may be provided with a third debug serial port through which third log information may be output to the programmable logic device, the fourth processor may be provided with a fourth debug serial port through which fourth log information may be output to the programmable logic device, the programmable logic device can insert preset designated characters into the first log information, the second log information, the third log information and the fourth log information respectively, configure the first log information, the second log information, the third log information and the fourth log information after the preset designated characters are inserted into fifth log information and send the fifth log information to the data conversion chip, the data conversion chip can convert the first log information, the second log information, the third log information and the fourth log information which are matched with the data display of the serial communication port from the fifth log information, the serial communication port can synchronously display the first log information, the second log information, the third log information and the fourth log information which are converted by the data conversion chip according to the preset designated characters respectively inserted into the fifth buffer, the four-way server can synchronously display the log information of the four-way processor on the four-way server.
Further, in this embodiment, the programmable logic device may include a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter, and a serial output controller, where the first buffer may buffer the first log information, the second buffer may buffer the second log information, the third buffer may buffer the third log information, the fourth buffer may buffer the fourth log information, the counter may perform synchronous counting associated with the operating frequency according to the operating frequency of the first processor, the second processor, the third processor, and the fourth processor, respectively, the fifth buffer may insert preset designated characters into the first log information, the second log information, the third log information, and the fourth log information, respectively, according to the synchronous counting associated with the operating frequency by the counter, and configuring the first log information, the second log information, the third log information and the fourth log information after the preset specified character is inserted into fifth log information, wherein the serial port output controller can send the fifth log information to the data conversion chip, so that the advantage of acquiring the log information of a four-way processor which is the same as the first processor, the second processor, the third processor and the fourth processor can be realized.
Further, in this embodiment, the counter may respectively perform synchronous counting associated with the operating frequencies according to the operating frequencies of the first processor, the second processor, the third processor, and the fourth processor in a manner that the first debugging serial port, the second debugging serial port, the third debugging serial port, and the fourth debugging serial port respectively start counting in the same bit rate cycle, which is beneficial to realize synchronous counting of the operating frequencies of the four-way processors associated with the first processor, the second processor, the third processor, and the fourth processor, respectively, and conveniently and completely obtain log information of the four-way processors according to the respectively performed synchronous counting associated with the operating frequencies.
Further, in this embodiment, the data conversion chip may separate the first log information, the second log information, the third log information and the fourth log information matching the respectively inserted preset designated characters from the fifth log information by the respectively inserted preset designated characters of the fifth buffer, and convert the separated first log information, second log information, third log information and fourth log information into the first log information, the second log information, the third log information and the fourth log information matching the data display of the serial communication port, which is advantageous in that it can facilitate the subsequent synchronous display of the log information of the four-way processor including the first processor, the second processor, the third processor and the fourth processor.
Further, in this embodiment, the serial communication port may obtain a start time and an end time matching with the preset designated characters inserted into the fifth buffer, respectively, and synchronously display the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to the obtained start time and end time, which is advantageous in that the log information of the four-way processor including the first processor, the second processor, the third processor and the fourth processor can be synchronously displayed.
The invention also provides a method for outputting the log information by the four-way server, which can realize that the four-way server can synchronously display the log information of the four-way processor on the four-way server.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for outputting log information by a four-way server according to an embodiment of the present invention. The four-path server comprises a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip and a serial communication port. It should be noted that the method of the present invention is not limited to the flow sequence shown in fig. 2 if the results are substantially the same. As shown in fig. 1, the method comprises the steps of:
s201: the first processor outputs first log information to the programmable logic device data conversion chip through a first debugging serial port arranged on the first processor, the second processor outputs second log information to the programmable logic device data conversion chip through a second debugging serial port arranged on the second processor, the third processor outputs third log information to the programmable logic device data conversion chip through a third debugging serial port arranged on the third processor, and the fourth processor outputs fourth log information to the programmable logic device data conversion chip through a fourth debugging serial port arranged on the fourth processor.
S202: the programmable logic device inserts preset specified characters into the first log information, the second log information, the third log information and the fourth log information respectively, configures the first log information, the second log information, the third log information and the fourth log information after the preset specified characters are inserted into fifth log information, and sends the fifth log information to the data conversion chip.
S203: the data conversion chip converts the first log information, the second log information, the third log information and the fourth log information which are matched with the data display of the serial communication port from the fifth log information.
S204: the serial communication port synchronously displays the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to preset designated characters respectively inserted into the fifth buffer.
Wherein, the programmable logic device inserts preset designated characters into the first log information, the second log information, the third log information and the fourth log information, respectively, configures the first log information, the second log information, the third log information and the fourth log information into fifth log information after the preset designated characters are inserted, and sends the fifth log information to the data conversion chip, and may include:
the programmable logic device can comprise a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter and a serial port output controller;
the first buffer buffers the first log information, the second buffer buffers the second log information, the third buffer buffers the third log information, the fourth buffer buffers the fourth log information, the counter respectively performs synchronous counting related to the working frequency according to the working frequency of the first processor, the second processor, the third processor and the fourth processor, the fifth buffer inserts preset designated characters into the first log information, the second log information, the third log information and the fourth log information according to the synchronous counting associated with the operating frequency respectively performed by the counter, and configuring the first log information, the second log information, the third log information and the fourth log information after the preset specified character is inserted into fifth log information, and sending the fifth log information to the data conversion chip by the serial port output controller.
Wherein, the counter performs synchronous counting associated with the working frequency according to the working frequency of the first processor, the second processor, the third processor, and the fourth processor, respectively, and may include:
and according to the working frequencies of the first processor, the second processor, the third processor and the fourth processor, respectively carrying out synchronous counting related to the working frequencies in a mode of starting counting by respectively using the same specific cycles of the first debugging serial port, the second debugging serial port, the third debugging serial port and the fourth debugging serial port.
The data conversion chip converts the first log information, the second log information, the third log information and the fourth log information which are matched with the data display of the serial communication port from the fifth log information, and may include:
and decomposing first log information, second log information, third log information and fourth log information which are matched with the preset designated characters respectively inserted into the fifth buffer from the fifth log information, and converting the decomposed first log information, second log information, third log information and fourth log information into first log information, second log information, third log information and fourth log information which are matched with the serial communication port data display.
The step of synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip by the serial communication port according to the preset designated characters respectively inserted into the fifth buffer may include:
and according to the preset designated characters respectively inserted into the fifth buffer, acquiring the starting time and the ending time matched with the preset designated characters respectively inserted into the fifth buffer, and synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to the acquired starting time and ending time.
In this embodiment, each unit module in the method for outputting log information by the four-way server can respectively perform the functions and functions of the corresponding unit module in the four-way server embodiment, so that the description of each unit module is omitted here, and please refer to the description of the functions and functions of the corresponding unit module above in detail.
It can be found that, in the above solution, the four-way server may include a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip, and a serial communication port, the first processor may be provided with a first debug serial port through which first log information may be output to the programmable logic device data conversion chip, the second processor may be provided with a second debug serial port through which second log information may be output to the programmable logic device, the third processor may be provided with a third debug serial port through which third log information may be output to the programmable logic device, the fourth processor may be provided with a fourth debug serial port through which fourth log information may be output to the programmable logic device, the programmable logic device can insert preset designated characters into the first log information, the second log information, the third log information and the fourth log information respectively, configure the first log information, the second log information, the third log information and the fourth log information after the preset designated characters are inserted into fifth log information and send the fifth log information to the data conversion chip, the data conversion chip can convert the first log information, the second log information, the third log information and the fourth log information which are matched with the data display of the serial communication port from the fifth log information, the serial communication port can synchronously display the first log information, the second log information, the third log information and the fourth log information which are converted by the data conversion chip according to the preset designated characters respectively inserted into the fifth buffer, the four-way server can synchronously display the log information of the four-way processor on the four-way server.
Further, in the above solution, the programmable logic device may include a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter, and a serial output controller, where the first buffer may buffer the first log information, the second buffer may buffer the second log information, the third buffer may buffer the third log information, the fourth buffer may buffer the fourth log information, the counter may perform synchronous counting associated with the operating frequency according to the operating frequency of the first processor, the second processor, the third processor, and the fourth processor, respectively, the fifth buffer may insert preset designated characters for the first log information, the second log information, the third log information, and the fourth log information according to the synchronous counting associated with the operating frequency by the counter, respectively, and configuring the first log information, the second log information, the third log information and the fourth log information after the preset specified character is inserted into fifth log information, wherein the serial port output controller can send the fifth log information to the data conversion chip, so that the advantage of acquiring the log information of a four-way processor which is the same as the first processor, the second processor, the third processor and the fourth processor can be realized.
Further, according to the above scheme, the counter may perform synchronous counting associated with the operating frequencies respectively according to the operating frequencies of the first processor, the second processor, the third processor, and the fourth processor in a manner that the first debugging serial port, the second debugging serial port, the third debugging serial port, and the fourth debugging serial port start counting in the same bit rate cycle respectively, so as to achieve synchronous counting of the operating frequencies of four processors including the first processor, the second processor, the third processor, and the fourth processor, which is associated with each other, and conveniently obtain log information of the four processors completely according to the synchronous counting associated with the operating frequencies respectively.
Further, according to the above aspect, the data conversion chip can separate the first log information, the second log information, the third log information and the fourth log information which match with the respectively inserted preset designated characters from the fifth log information through the respectively inserted preset designated characters, and convert the separated first log information, second log information, third log information and fourth log information into the first log information, the second log information, the third log information and the fourth log information which match with the data display of the serial communication port, which can realize the advantage of facilitating the subsequent synchronous display of the log information of the four-way processor including the first processor, the second processor, the third processor and the fourth processor.
Further, according to the above solution, the serial communication port can obtain the start time and the end time matched with the preset designated characters respectively inserted into the fifth buffer, and synchronously display the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to the obtained start time and end time, which is advantageous in that the log information of a four-way processor including the first processor, the second processor, the third processor and the fourth processor can be synchronously displayed.
In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only a part of the embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes performed by the present invention through the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A four-way server, comprising:
the system comprises a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip and a serial communication port;
the first processor is provided with a first debugging serial port and is used for outputting first log information to the programmable logic device data conversion chip through the first debugging serial port;
the second processor is provided with a second debugging serial port and used for outputting second log information to the programmable logic device through the second debugging serial port;
the third processor is provided with a third debugging serial port and is used for outputting third log information to the programmable logic device through the third debugging serial port;
the fourth processor is provided with a fourth debugging serial port and is used for outputting fourth log information to the programmable logic device through the fourth debugging serial port;
the programmable logic device is configured to insert preset designated characters into the first log information, the second log information, the third log information, and the fourth log information, configure the first log information, the second log information, the third log information, and the fourth log information into fifth log information after the preset designated characters are inserted, and send the fifth log information to the data conversion chip;
the data conversion chip is used for converting first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port from the fifth log information;
and the serial communication port is used for synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to preset designated characters respectively inserted into the fifth buffer.
2. The four-way server according to claim 1, wherein the programmable logic device comprises:
the device comprises a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter and a serial port output controller;
the first buffer is used for buffering the first log information;
the second buffer is used for buffering the second log information;
the third buffer is used for buffering the third log information;
the fourth buffer is used for buffering the fourth log information;
the counter is used for respectively carrying out synchronous counting related to the working frequency according to the working frequency of the first processor, the second processor, the third processor and the fourth processor;
the fifth buffer is configured to insert preset specified characters into the first log information, the second log information, the third log information, and the fourth log information respectively according to synchronous counting associated with the operating frequency respectively performed by the counter, and configure the first log information, the second log information, the third log information, and the fourth log information into fifth log information after the preset specified characters are inserted;
and the serial port output controller is used for sending the fifth log information to the data conversion chip.
3. The four-way server according to claim 2, wherein the counter is specifically configured to:
and according to the working frequencies of the first processor, the second processor, the third processor and the fourth processor, respectively carrying out synchronous counting related to the working frequencies in a mode of starting counting by respectively using the same specific cycles of the first debugging serial port, the second debugging serial port, the third debugging serial port and the fourth debugging serial port.
4. The four-way server according to claim 1, wherein the data conversion chip is specifically configured to:
and decomposing first log information, second log information, third log information and fourth log information which are matched with the preset designated characters respectively inserted from the fifth log information through the preset designated characters respectively inserted into the fifth buffer, and converting the decomposed first log information, second log information, third log information and fourth log information into first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port.
5. The four-way server according to claim 1, wherein the serial communication port is specifically configured to:
and according to the preset designated characters respectively inserted into the fifth buffer, acquiring the starting time and the ending time matched with the preset designated characters respectively inserted, and according to the acquired starting time and ending time, synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip.
6. A method for outputting log information by a four-way server is characterized by comprising the following steps:
the four-path server comprises a first processor, a second processor, a third processor, a fourth processor, a programmable logic device, a data conversion chip and a serial communication port;
the first processor outputs first log information to the programmable logic device data conversion chip through a first debugging serial port arranged on the first processor, the second processor outputs second log information to the programmable logic device data conversion chip through a second debugging serial port arranged on the second processor, the third processor outputs third log information to the programmable logic device data conversion chip through a third debugging serial port arranged on the third processor, and the fourth processor outputs fourth log information to the programmable logic device data conversion chip through a fourth debugging serial port arranged on the fourth processor;
the programmable logic device inserts preset specified characters into the first log information, the second log information, the third log information and the fourth log information respectively, configures the first log information, the second log information, the third log information and the fourth log information into fifth log information after the preset specified characters are inserted, and sends the fifth log information to the data conversion chip;
the data conversion chip converts first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port from the fifth log information;
and the serial communication port synchronously displays the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to preset designated characters respectively inserted into the fifth buffer.
7. The four-way server according to claim 6, wherein the programmable logic device inserts a preset designated character for each of the first log information, the second log information, the third log information, and the fourth log information, configures the first log information, the second log information, the third log information, and the fourth log information after the insertion of the preset designated character as fifth log information, and transmits the fifth log information to the data conversion chip, and comprises:
the programmable logic device comprises a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a counter and a serial port output controller;
the first buffer caches the first log information, the second buffer caches the second log information, the third buffer caches the third log information, the fourth buffer caches the fourth log information, the counter respectively performs synchronous counting associated with the working frequency according to the working frequency of the first processor, the second processor, the third processor and the fourth processor, the fifth buffer respectively inserts preset designated characters into the first log information, the second log information, the third log information and the fourth log information according to the synchronous counting associated with the working frequency respectively performed by the counter, and configures the first log information, the second log information, the third log information and the fourth log information after the preset designated characters are inserted into fifth log information, and the serial port output controller sends the fifth log information to the data conversion chip.
8. The four-way server according to claim 7, wherein the counter performs synchronous counting associated with the operating frequencies according to the operating frequencies of the first processor, the second processor, the third processor, and the fourth processor, respectively, and comprises:
and according to the working frequencies of the first processor, the second processor, the third processor and the fourth processor, respectively carrying out synchronous counting related to the working frequencies in a mode of starting counting by respectively using the same specific cycles of the first debugging serial port, the second debugging serial port, the third debugging serial port and the fourth debugging serial port.
9. The four-way server according to claim 6, wherein the data conversion chip converts the first log information, the second log information, the third log information and the fourth log information matched with the data display of the serial communication port from the fifth log information, and comprises:
and decomposing first log information, second log information, third log information and fourth log information which are matched with the preset designated characters respectively inserted from the fifth log information through the preset designated characters respectively inserted into the fifth buffer, and converting the decomposed first log information, second log information, third log information and fourth log information into first log information, second log information, third log information and fourth log information which are matched with the data display of the serial communication port.
10. The four-way server according to claim 6, wherein the serial communication port synchronously displays the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip according to the predetermined designated characters respectively inserted into the fifth buffer, and comprises:
and according to the preset designated characters respectively inserted into the fifth buffer, acquiring the starting time and the ending time matched with the preset designated characters respectively inserted, and according to the acquired starting time and ending time, synchronously displaying the first log information, the second log information, the third log information and the fourth log information converted by the data conversion chip.
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