CN113475023A - Apparatus and method for parallelized recursive block decoding - Google Patents

Abstract

A decoder (300) for determining an estimate of a vector of information symbols carried by a signal received over a transmission channel represented by a channel matrix. The decoder includes: -a block dividing unit (303) configured to divide a vector of information symbols into two or more sub-vectors, each sub-vector being associated with a block level; -two or more processors configured to determine candidate sub-vectors in parallel and to store the candidate sub-vectors in a first stack (310). Each processor is configured to determine at least one candidate sub-vector by applying a symbol estimation algorithm and to store each candidate sub-vector with a decoding metric and a block level associated with the candidate sub-vector. The decoding metric is lower than or equal to the decoding metric threshold. A processor among the two or more processors is configured to determine at least one candidate vector from the candidate sub-vectors stored in the first stack (310), the candidate vector being associated with an accumulated decoding metric, and to update the decoding metric threshold according to the accumulated decoding metric.

Description

Apparatus and method for parallelized recursive block decoding

Technical Field

The present invention relates generally to digital communications, and in particular to a method and apparatus for decoding data signals.

Background

Multiple Input Multiple Output (MIMO) technology is used in various communication systems to provide high transmission rates. MIMO systems utilize the spatial and time dimensions to encode and multiplex more data symbols using multiple transmit and/or receive antennas over multiple time slots. As a result, the capacity, range and reliability of the MIMO-based communication system may be enhanced. Exemplary MIMO communication systems include wired, wireless and optical communication systems.

Space-time diversity is achieved in a MIMO system using space-time coding. At a transmitter device, a space-time encoder is implemented to encode a data stream into codewords that are subsequently transmitted over a transmission channel. At the receiver device, a space-time decoder is implemented to recover the desired data stream transmitted by the transmitter device.

There are several space-time decoding algorithms. The choice of decoding algorithm used depends on the target performance as well as the implementation complexity and associated costs.

In the presence of uniformly distributed information symbols, the best space-time decoder will implement the Maximum Likelihood (ML) decoding standard. Exemplary ML decoding algorithms include exhaustive search and sequential decoding algorithms, such as a Sphere decoder, Schnorr-Euchner decoder, Stack decoder, and SB-Stack decoder. The ML decoder provides the best performance but requires a high computational complexity which increases with the number of antennas and the size of the letter to which the information symbol belongs.

Alternatively, a sub-optimal decoding algorithm may be used that requires lower computational complexity compared to the ML decoder. Exemplary sub-optimal decoding algorithms include linear decoders (e.g., zero-forcing (ZF) and Minimum Mean Square Error (MMSE) decoders) and non-linear decoders (e.g., ZF-DFE decoders).

Both linear and non-linear decoders are based on intersymbol interference cancellation and estimation of each information symbol separately.

According to another block decoding method, information symbols may be decoded by means of sub-vectors, i.e. by means of symbol blocks. The decoding algorithm that implements block decoding is based on dividing a vector of information symbols into two or more sub-vectors. Given the sub-vectors of previously estimated information symbols, each sub-vector is separately and recursively estimated. The estimation of each sub-vector of a symbol is performed using a symbol estimation algorithm (hereinafter also referred to as "estimation algorithm"). Any sequential, linear or non-linear decoding algorithm may be implemented in a given block as a symbol estimation algorithm to generate estimates of the corresponding sub-vectors of information symbols.

According to the QR-based block decoding algorithm, the division of the vector of information symbols is performed according to the division of an upper triangular matrix representing the transmission channel. The upper triangular matrix may be obtained by applying QR decomposition to a channel matrix representing the transmission channel.

QR-based block decoding algorithms are disclosed in "W-J Choi, R.Negi and J.M.Cioffi, Combined ML and DFE decoding for the V-BLAST system, IEEE International Conference on Communications, Volume 3,1243 and 1248 pages, 2000". A wireless MIMO system using spatial multiplexing of data streams is proposed in a combination of ML and DFE decoding. First, a vector of information symbols of length n is divided into two sub-vectors of length p and n-p, respectively. ML decoding is then used to determine an estimate of the sub-vector comprising p information symbols. The remaining n-p symbols are then estimated after inter-symbol interference cancellation using decision feedback equalization. The choice of the partition parameters (i.e. the number of sub-vectors and the length of each sub-vector) is determined.

For example, other QR-based block decoding algorithms for coded wireless MIMO systems are disclosed in:

-K.Pavan Srinath and B.Sundar Rajan,Low ML-Decoding Complexity,Large Coding Gain,Full-Rate,Full-Diversity STBCs for 2x2 and 4x2 MIMO Systems,IEEE Journal of Selected Topics in Signal Processing,Volume 3,Issue6,pages 916-927,2009”；

"L.P.Natarajan, K.P.Srinath, and B.Sundar Rajan, On The Sphere Decoding compatibility of Gigh-Rate Multigroup Decoding STBCs in asymmetry MIMO Systems, IEEE Transactions On Information Theory, Volume 59, Issue 9,2013"; and

-“T.P.Ren,Y.L.Guan,C.Yuen,and R.J.Shen.Fast-group-decodable space-time block code.In Proceedings of IEEE Information Theory Workshop,pages 1–5,January 2010”。

according to another QR-based block decoding method, the estimation of the vector of information is based on an exhaustive search of candidate sub-vectors associated with each sub-vector of information symbols. According to the method, a received signal is divided into two or more sub-vectors. For each sub-vector of an information symbol, an exhaustive search is applied to enumerate all possible candidate sub-vectors representing estimates of the sub-vector of the information symbol. Using recursive interference cancellation, an exhaustive list of candidates is constructed by subtracting the interference due to previously decoded subvectors associated with blocks at lower levels in the upper triangular matrix and by applying the ML or ZF-DFE estimation algorithm. After deriving a candidate list for all sub-vectors of an information symbol, a solution corresponding to a candidate vector comprising the candidate sub-vector associated with the smallest decoding metric is conveyed as an estimate of the vector of information symbols.

The exhaustive search applied for generating candidate sub-vectors associated with each sub-vector of an information symbol requires a high computational complexity.

Recently, a QR-based block decoding algorithm, called a "semi-exhaustive recursive block decoder", has been proposed in patent application No. 15306808.5. A semi-exhaustive recursive block decoder provides a decoding solution that is inspired from the original exhaustive search based recursive decoder. Thus, instead of performing an exhaustive search to enumerate all possible candidate estimates for each sub-vector of information symbols, the semi-exhaustive recursive block decoder uses a radius for each sub-vector as a threshold for a decoding metric for the candidate sub-vector to be generated. Setting such a threshold enables a reduction of the number of candidate sub-vectors in the different lists. The selection of radius thresholds for different sub-vectors is performed according to a target diversity order. The semi-exhaustive recursive block decoder provides better decoding performance while providing reduced decoding complexity compared to the original exhaustive search based recursive block decoder.

Existing recursive block decoding algorithms provide better performance than linear and non-linear decoders. However, they still require increased computational complexity compared to linear and non-linear decoders. Therefore, there is a need to develop a recursive block decoder with low complexity and low delay.

Disclosure of Invention

To address these and other problems, a decoder is provided for determining an estimate of a vector of information symbols carried by a signal received over a transmission channel represented by a channel matrix. The decoder includes:

-a block division unit configured to divide the vector of information symbols into two or more sub-vectors of information symbols, each sub-vector being associated with a block level representing a level of the sub-vector in the channel matrix, in accordance with the division of the channel matrix into sub-matrices;

-two or more processors configured to operate in parallel for determining candidate sub-vectors and storing the candidate sub-vectors in a first stack, each of the two or more processors being configured to determine at least one candidate sub-vector representing an estimate of a sub-vector of information symbols by applying a symbol estimation algorithm and to store the at least one candidate sub-vector of information symbols in the first stack with a decoding metric and a block level representing a level of the candidate sub-vector within a channel matrix. The decoding metric is lower than or equal to the decoding metric threshold. A processor among the two or more processors is configured to determine at least one candidate vector from the candidate sub-vectors stored in the first stack, the candidate vector representing an estimate of a vector of information symbols and being associated with an accumulated decoding metric determined from decoding metrics stored with the candidate sub-vectors, and to update the decoding metric threshold based on the accumulated decoding metric.

According to some embodiments, the two or more processors may include:

-a first processor configured to determine one or more candidate sub-vectors associated with each sub-vector of information symbols by applying an estimation algorithm recursively starting from the sub-vector of information symbols associated with the highest block level until reaching the sub-vector of information symbols associated with the lowest block level, the first processor being configured to store each candidate sub-vector in a first stack; and

-a second processor configured to determine one or more candidate sub-vectors by recursively selecting the sub-vectors associated with the lowest block level in the first stack and determining candidate sub-vectors associated with each sub-vector of information symbols associated with block levels lower than the lowest block level by applying a symbol estimation algorithm until the lowest block level of the channel matrix is reached. The second processor may be further configured to determine a candidate vector from the selected candidate sub-vector and a candidate sub-vector determined in association with a sub-vector of information symbols associated with a block level below the lowest block level, the candidate vector representing an estimate of the vector of information symbols, the second processor being further configured to determine an accumulated metric associated with the candidate vector by adding a decoding metric associated with the selected candidate sub-vector and a decoding metric associated with a candidate sub-vector determined in association with a sub-vector of information symbols associated with a block level below the lowest block level, the second processor being configured to store the candidate vector in a second stack together with the accumulated decoding metric, the decoding metric threshold being updated to the accumulated decoding metric.

According to some embodiments, a processor among the two or more processors may be configured to:

-ordering the first stacks according to a given order of decoding metrics associated with the candidate sub-vectors,

-updating the decoding metric threshold to an accumulated decoding metric associated with the candidate vector,

-removing from the first stack candidate sub-vectors associated with decoding metrics above the updated decoding metric threshold, and

-determining an estimate of the vector of information symbols from the candidate vector stored in the second stack associated with the lowest accumulated decoding metric.

According to some embodiments, the symbol estimation algorithm is selected from the group consisting of a trellis decoding algorithm, a zero forcing algorithm, a minimum mean square error algorithm, and a zero forcing decision feedback equalizer.

According to some embodiments, the symbol estimation algorithm comprises a pre-processing step using a lattice reduction algorithm and/or MMSE-GDFE filtering.

According to some embodiments, the symbol estimation algorithm may be predetermined depending on the signal-to-noise ratio and/or the outage capacity.

According to some embodiments, the symbol estimation algorithm may be predetermined depending on a target quality of service metric selected in a group comprising a target achievable transmission rate.

According to some embodiments, the block division unit may be configured to divide the vector of information symbols according to a set of division parameters comprising a number of blocks at least equal to two representing a number of sub-vectors of said information symbols and a block length representing a number of information symbols comprised in a sub-vector of information symbols.

A method is also provided for determining an estimate of a vector of information symbols carried by a signal received over a transmission channel represented by a channel matrix. The method comprises the following steps:

-dividing the vector of information symbols into two or more sub-vectors of information symbols, each sub-vector being associated with a block level representing the level of said sub-vector in the channel matrix, in dependence on dividing the channel matrix into sub-matrices;

-determining, by two or more processors operating in parallel, candidate sub-vectors and storing the candidate sub-vectors in a first stack, the step of determining the candidate sub-vectors comprising:

determining, by each of the two or more processors, at least one candidate sub-vector representing an estimate of a sub-vector of the information symbols by applying a symbol estimation algorithm, and

storing at least one candidate sub-vector of information symbols in a first stack with a decoding metric and a block level representing a level of said candidate sub-vector within said channel matrix, said decoding metric being lower than or equal to a decoding metric threshold,

the method further comprises determining at least one candidate vector from the candidate sub-vectors stored in the first stack, the candidate vector representing an estimate of the vector of information symbols and being associated with an accumulated decoding metric determined from the decoding metrics stored with the candidate sub-vectors, and updating the decoding metric threshold in dependence on the accumulated decoding metric.

Advantageously, embodiments of the present invention provide a parallelized recursive block decoding technique that provides optimal decoding complexity, as well as reduced decoding delay and reduced computational complexity.

Other advantages of the invention will become apparent to those skilled in the art upon examination of the drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and:

figure 1 is a block diagram of an exemplary application of the present invention in a communication system, according to some embodiments;

figure 2 is a block diagram of an exemplary application of the invention on a wireless single-user MIMO system, according to some embodiments;

figure 3 is a block diagram representing the structure of a space-time decoder according to some embodiments, in which parallelized recursive block decoding is used;

FIG. 4 is a flow chart describing a method of parallelized recursive block decoding according to some embodiments;

figure 5 shows the hardware architecture of a space-time decoder according to some embodiments.

Detailed Description

Embodiments of the present disclosure provide a low complexity and low delay parallelized recursive block decoding apparatus and method for decoding a signal received over a transmission channel and carrying information symbols with an optimal diversity order and reduced decoding complexity and decoding delay. The transmission channel is represented by an upper triangular matrix obtained by applying QR decomposition to a channel state matrix representing the transmission channel.

Embodiments of the present disclosure provide a recursive decoding algorithm based on parallelized QR, the parallelization of the processing of different blocks or sub-vectors of information symbols resulting in a significant reduction of decoding delay.

The apparatus and methods according to various embodiments may be implemented in different types of systems. In particular, they may be implemented in a communication system to determine estimates of vectors of information symbols communicated from one or more transmitter devices to a receiver device.

For purposes of illustration only, the following description of some embodiments will be made with reference to a communication system. However, the skilled person will readily understand that the various embodiments may be applied to other types of systems, such as signal processing systems, cryptographic systems and positioning systems.

Fig. 1 is a block diagram of an exemplary application of a communication system 100 according to some embodiments. The communication system 100 may be wired, wireless, or optical (e.g., fiber-based). The communication system 100 may include at least one transmitter device 11 (hereinafter "transmitter") configured to transmit a plurality of information symbols to at least one receiver device 15 (hereinafter "receiver") via a transmission channel 13. A receiver 15 may be included at the space-time decoder 10 to decode information symbols transmitted by one or more transmitter devices 11. The transmission channel 13 may be any wired connection, wireless medium, or optical link.

In the application of the present invention to radio communication, the communication system 100 may be a wireless single-user MIMO system, comprising: a wireless transmitter device 11 configured to communicate a stream of information symbols representing input data; and a wireless receiver device 15 configured to decode the symbols transmitted by the transmitter 11.

Transmitter device 11 may be equipped with one or more transmit antennas and receiver device 15 may be equipped with one or more receive antennas, the number n of transmit antennas_tAnd the number n of receiving antennas_rGreater than or equal to one.

In another application of the present invention to radio communications, the communication system 100 may be a wireless multi-user MIMO system, in which a plurality of wireless transmitter devices 11 and receiver devices 15 communicate with each other. In such embodiments, communication system 100 may also use any multiple access technique, such as Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Code Division Multiple Access (CDMA), and Space Division Multiple Access (SDMA), alone or in combination.

In applications of the present invention to optical communications, the communication system 100 may be an optical fiber-based communication system. The transmitter 11 and receiver 15 may thus be any optical transceiver capable of operating in an optical fiber based transmission system. The transmission channel 13 may be any fiber optic link designed to carry data over short or long distances. Exemplary applications that use optical fiber links over short distances include high capacity networks, such as data center interconnects. Exemplary applications that use fiber optic links over long distances include terrestrial and transoceanic transmission. In such embodiments, the information symbols transmitted by the transmitter 11 may be carried by optical signals polarized according to different polarization states of the optical fiber. The optical signal propagates along the fiber-based transmission channel 11 according to one or more propagation modes until reaching the receiver 15.

In another application of the invention to optical communications, a single wavelength laser may be used to generate an optical signal carrying information symbols.

In other embodiments, Wavelength Division Multiplexing (WDM) techniques may be used at the transmitter 11 to enable the use of multiple independent wavelengths to generate the optical signal.

In yet another application of the present invention to optical communication systems using multimode and/or multicore optical fibers, spatial multiplexing techniques may be used to multiplex information symbols according to various propagation modes.

Furthermore, multiple access techniques such as WDMA (wavelength division multiple access) may be used in some applications of the present invention to optical communication systems.

The transmission channel 13 may be any linear Additive White Gaussian Noise (AWGN) channel or multipath channel using single or multi-carrier modulation formats, such as OFDM (orthogonal frequency division multiplexing) and FBMC (filter bank multi-carrier), for mitigating frequency selectivity, interference, and delay.

In the application of the present invention to a wireless single-user MIMO system, the trade-off between complexity, performance and decoding delay of QR-based sub-block decoding of received signals can be optimized by optimizing the sub-block division of the vector of information symbols considering inter-sub-vector interference. Exemplary applications of the decoding method and apparatus include, but are not limited to, MIMO decoding in a configuration implemented in:

-powerline wired communication standardized in ITU g.hn and HomePlug AV2 specifications;

wireless standards such as Wi-Fi (IEEE 802.11n and IEEE 802.11ac), cellular WiMax (IEEE 802.16e), cooperative WiMax (IEEE 802.16j), Long Term Evolution (LTE), LTE-advanced, and ongoing standardization of 5G.

For purposes of illustration only, the following description will be made with reference to a wireless single-user MIMO system including a MIMO system equipped with n_tTransmitter device 11 with more than or equal to 1 transmitting antenna and equipped with n_rReceiver equipment 15 for more than 1 receive antenna for decoding the information symbols transmitted by the transmitter 11. However, the skilled person will readily understand that embodiments of the present invention are applicable to other communication systems, such as wireless multi-user MIMO systems and optical MIMO systems. More generally, the invention may be applied to any communication system featuring a linear representation (equivalently a trellis representation) of the channel output at the receiver device. In addition, although not limited to such an embodiment, there are more than or equal to two transmit antennas (n)_tMore than or equal to 2) and/or a number of receiving antennas (n) greater than or equal to two_rThe invention has special advantages under the condition of more than or equal to 2).

Referring to fig. 2, an exemplary wireless single-user MIMO communication system 200 is shown in which various embodiments of the present invention may be implemented. The wireless single-user MIMO communication system 200 may include a transmitter 20 implementing space-time block code (STBC) for multiplexing information symbols in the time and space dimensions, i.e., on transmit antennas. Each transmitter 20 of a station may exchange data with a receiver 21 of another station in accordance with the wireless communication system 200.

The wireless single-user MIMO communication system 200 may exhibit a symmetric configuration. As used herein, a symmetric configuration refers to a configuration in which the transmitter 20 and the receiver 21 are equipped with the same number of antennas n_t＝n_rThe configuration of (2). Alternatively, the MIMO configuration may be asymmetric, the number of receive antennas n_rDifferent from the number n of transmitting antennas_t. In particular, in one embodiment, to avoid the rank starvation problem, the number of receive antennas n_rMay be greater than the number n of antennas at the transmitter_t. Exemplary asymmetric MIMO configurations include, for example, 2x4 (n) supported in the LTE standard_t＝2，n_r4) and 4x8 (n)_t＝4，n_r＝8)。

The transmitter 20 may transmit the data by using a channel matrix H_cThe illustrated noisy wireless MIMO channel delivers signals to the receiver 21. The transmitter 20 may be implemented in different devices or systems capable of operating in a wireless environment. Exemplary devices suitable for such applications include mobile phones, drones, laptops, tablets, robots, IoT (internet of things) devices, base stations, and the like. The transmitter 20 may be fixed or mobile. For example, it may include:

a channel encoder 201 implementing one or more Forward Error Correction (FEC) codes, such as linear block codes, convolutional codes, polar codes, etc.;

a modulator 203 implementing a modulation scheme such as Quadrature Amplitude Modulation (QAM) to transmit a modulated symbol vector s_c；

A space-time encoder 205 for transmitting a codeword matrix X;

-n_ta plurality of transmit antennas 207, each associated with a single or multi-carrier modulator (e.g., an OFDM or FBMC modulator).

The transmitter 20 may be configured to encode the received information bit stream into a data input using an FEC encoder 201, the FEC encoder 201 implementing, for example, a linear block code, a convolutional code, or a polar code. The encoded binary signal may then be modulated into a symbol vector s using a modulator 203_c. Different modulation schemes may be implemented, e.g. with 2^q2 of a symbol or state^q-QAM or 2^q-PSK. Modulation vector s_cMay be a symbol comprising k complex values s₁,s₂,…,s_кQ bits per symbol.

Information symbol s_jHaving an average power E_sThe following can be written:

s_j＝Re(s_j)+iIm(s_j) (1)

in equation (1), i represents a complex number such that i²The operators Re (. -) and Im (. -) output the real and imaginary parts of the input value, respectively.

When using a device such as 2^q-modulation formats such as QAM, 2^qThe symbol or state representing an integer field

A subset of (a). The corresponding constellation diagram is composed of 2^qDots, which represent different states or symbols. In addition, in the case of square modulation, the real and imaginary parts of the information symbols belong to the same finite alphabet a [ - (q-1), (q-1)]. Minimum distance d of modulation scheme_minRepresents the euclidean distance between two adjacent points in the constellation diagram and is equal to 2 in this example.

Space-time encoder 205 may be configured to generate codeword matrix X from the encoded symbols. Space-time encoder 205 may use a linear STBC of length T and may transmit a dimension n_tA codeword matrix X of X T, which belongs to codebook C and is transmitted over T slots. The code rate of such codes is equal to the usage per channel

A complex symbol, wherein in this case kIs a vector s having a component dimension of κ_c＝[s₁,s₂,…,s_к]^tThe number of encoded complex-valued symbols. When using a full rate code, the space-time encoder 205 pairs k ═ n_tT complex-valued symbols are encoded. An example of STBC is "perfect code". Perfect code passing pair number of

Is encoded to provide a complete coding rate and to satisfy the non-vanishing determinant property.

In some embodiments, space-time encoder 205 may use a spatial multiplexing scheme known as the V-BLAST scheme by multiplexing received complex-valued information symbols over different transmit antennas without performing encoding in the time dimension.

The codewords thus constructed may be converted from the time domain to the frequency domain using multi-carrier modulation techniques (e.g., using OFDM or FBMC modulators) and spread over the transmit antennas 207. The signal may be transmitted from the transmit antenna 207 after optional filtering, frequency conversion, and amplification.

The receiver 21 may be configured to receive and decode signals transmitted by the transmitter 20 in the wireless network over a transmission channel (also referred to as "communication channel") subject to fading and interference and represented by a complex-valued channel matrix Hc. In addition, the communication channel may be noisy, e.g., affected by gaussian noise.

The receiver 21 may be integrated in a base station, such as a node B in a cellular network, an access point in a local area network or an ad hoc network, or any other interface device operating in a wireless environment. The receiver 21 may be fixed or mobile. In one exemplary embodiment, the receiver 21 may include:

a space-time decoder 211 configured to decode from the channel matrix H_cSum channel output signal Y_cTransmitting the modulated symbol vector s_cIs estimated by

A demodulator 213 configured to estimate the symbol vector by

Demodulating to generate a binary sequence;

a channel decoder 215 configured to deliver as output the binary signal as an estimate of the transmitted bits using, for example, the Viterbi algorithm.

The receiver 21 implements the inverse of the processing performed by the transmitter 20. Thus, if single carrier modulation is used at the transmitter instead of multi-carrier modulation, then n for the FBMC demodulator_rThe OFDM symbols may be replaced by corresponding single-carrier demodulators.

Fig. 3 shows a block diagram of a space-time decoder 300 (also referred to as "decoder") according to some embodiments applied to a wireless Rayleigh fading multi-antenna system, the decoder 300 being configured to receive and decode signals from a mobile station equipped with n_tSignals transmitted by a transmitter having a transmitting antenna, a decoder 300 provided with n_rIn a receiver device with a single receive antenna.

In accordance with some embodiments in which space-time encoding is performed at the transmitter using a space-time code of length T encoding k symbols, the received complex-valued signal may be written in the form:

Y_c＝H_cX_c+W_c (2)

in equation (2), Y_cIs n representing the received signal_rxT matrix, X_cWith a representation dimension of n_tA complex valued codeword matrix of xT.

According to some embodiments in which V-BLAST spatial multiplexing is used, the received complex-valued signal may be written in the following form:

y_c＝H_cs_c+w_c (3)

in equation (3), y_cIs n_rDimension vector, s_cWith a representation dimension of n_tA complex-valued vector of transmitted information symbols.

Complex value n in equations (2) and (3)_r×n_tMatrix H_cRepresenting a channel matrix including fading gains. In a Rayleigh fading channel, the channel matrix H_cThe entries of (a) are independent complex gaussian shapes of the same distribution (i.i.d). The channel matrix may be estimated in coherent transmission at the receiver using an estimation technique such as a least squares estimator. In addition to the effects of multipath fading, the transmission channel may be noisy. The noise may be due to thermal noise of system components, inter-user interference, and interference radiation intercepted by the antenna. Can be generated by_rxT complex matrix W_cAnd n_rVector w of complex dimensional values_cThe variance σ for each real-valued dimension modeled in equations (2) and (3), respectively²The total noise is modeled as zero-mean additive white gaussian noise.

The decoder may comprise a complex-to-real converter 301 configured to convert a complex-valued channel matrix H into a complex-valued channel matrix H_cThe channel matrix H is converted to a real-valued equivalent channel matrix H, and the complex-valued received signal is converted to a real signal.

In one embodiment using V-BLAST spatial multiplexing, the complex to real converter 301 may be configured to transform the system in equation (3) into:

the Re (.) and Im (.) operators in equation (4) specify the real and imaginary parts of each element that makes up the base vector or matrix. The complex to real conversion may be performed in any order considering the elements of the vector, and is not limited to the exemplary conversion expressed in equation (4).

In another embodiment using linear space-time block coding at the transmitter, the complex-to-real converter 301 may be configured to transform the system in equation (2) into a real-valued system that may be written in a linear representation of equation (4), where the equivalent channel matrix is a real-valued 2n in equation (4)_rT x 2 k matrix H_eq，Given by:

2n_tthe T x 2 k matrix G represents a real-valued matrix known as a generator matrix or encoding matrix of a linear space-time block code used at the transmitter. I is_TRepresenting an identity matrix of dimension T, and an operator

Is the Kronecker matrix product.

To facilitate an understanding of the following embodiments, the following description will refer to a spatial multiplexing scheme and relate to a symmetric MIMO configuration, where the transmitter and receiver are equipped with the same number of antennas n_t＝n_rFor illustrative purposes only. Thus, the real-valued system in equation (3) can be represented in linear form as:

y＝Hs+w (6)

in equation (6), the vectors y, s and w are n-2 n_t＝2n_rAnd the equivalent real-valued channel matrix H is an n × n square matrix. The vector s includes the vector s_cThe real and imaginary parts of the original complex-valued information symbols contained therein.

The decoder 300 may comprise a QR decomposition unit 302 configured to generate an orthogonal matrix Q and an upper triangular matrix R by applying QR decomposition to a real-valued channel matrix such that H ═ QR. The component of the upper triangular matrix is represented by R_ijWherein i, j is 1, …, n.

The decoder 300 may further comprise a multiplication unit 309 configured to determine the auxiliary signal by scaling the real-valued signal y with a transpose of an orthogonal matrix Q obtained from a QR decomposition of the real-valued channel matrix

Such that:

in the case of the equation (7),

representing the scaled noise vector. Given the orthogonality of the matrix Q, the system in equation (7) is equivalent to the system given in equation (6).

The recursive block decoding based on QR parallelization according to various embodiments is based on the real-valued system of equation (7).

ML decoding of information symbols can be formalized by the optimization problem given below:

in equation (8), a denotes a complex-valued vector s constituting a real number vector s_cThe real and imaginary parts of (a) belong to the letter. The ML metric related to the ML decoding problem can be defined as:

recursive block decoding according to embodiments of the present disclosure is based on dividing a vector of information symbols into two or more sub-vectors according to dividing an upper triangular matrix into a plurality of sub-matrices.

Thus, the decoder 300 may further comprise a block partitioning unit 303 configured to perform vector and matrix partitioning according to a set of partitioning parameters comprising a number of blocks at least equal to two (denoted by N ≧ 2) and a block length (denoted by l ≧ 2)_kWhere k is 1, …, N) such that the length l_k≧ 1 corresponds to the length of the number of elements/entries of the kth sub-vector of information symbols which is greater than or equal to 1, i.e., each sub-vector of information symbols comprises one or more symbols. The length of the block satisfies the equality given by:

using the set of partition parameters, the block partitioning unit 303 may be configured to partition the vector into a plurality of blocks

Is divided into N sub-vectors such that

Subvectors with index k

Has a length of l_k. Similarly, the block division unit 303 may be configured to divide the real-valued vector of information symbols s and the noise vector

Are respectively divided into lengths of l_kN subvectors s^(k)And N subvectors

So that

And

performing the vector pair according to the following by dividing the upper triangular matrix R into sub-matrices

s and

the method comprises the following steps:

in equation (10):

-a triangular submatrix R on a square^(k)Has a dimension of l_kxl_k(ii) a And

-submatrix B^(kj)Is of dimension l_kxl_jIs given, where j-k +1^(k)And s^(j)To the other.

According to some embodiments, the block dividing unit 303 may be configured to determine the set of division parameters in advance depending on a zero structure of the upper triangular matrix R, such that the set of division parameters divides the upper triangular matrix into sub-matrices that utilize the zero structure of the rectangular sub-matrices to reduce error propagation due to interference between sub-vectors. In fact, due to the sub-matrix B^(kj)Is represented in a sub-vector s^(k)And s^(j)Of the sub-vector s, so that the sub-vector s^(k)Depends on the sub-subvectors s^(j)A determined estimate of (j ═ k + 1.., N). Subvector s^(j)Any error in the estimation of (a) may cause the sub-vector s to be^(k)Error in the estimation of (2). Due to the presence of the subvector s^(k)And s^(j)The error propagation caused by the interference between (j + k + 1.. times.n) depends on the rectangular submatrix B^(kj)The zero structure of (3). The fewer the number of zeros in the rectangular sub-matrix, the less error propagation and the better the decoding error performance.

Thus, the block partitioning unit 303 may be configured to predetermine the set of partitioning parameters such that for a given upper channel matrix, the impact of interference between the sub-vectors of information symbols is minimized. The set of partition parameters may be determined based on an optimization (minimization or maximization) of a partition metric representing a zero structure of the rectangular sub-matrix.

Given a set of partition parameters, a partitioned sub-matrix R of an upper triangular matrix R^(k)And B^(kj)And the divided sub-vectors

Can be grouped into N blocks (SB)_kWhere k is 1, …, N.

Block (SB)_k(k-1, …, N-1) may be defined by a set of parameters such that

Wherein

For k-N, a block of index N may be defined as

Thereby to obtain

D^(k)Specifying a symbol estimation algorithm to be applied in the k-th block for determining the information symbol s^(k)Candidate estimation of the sub-vectors of (1).

From such a set, the ML decoding metric in equation (9) can be written as:

thus, the ML optimization system of equation (8) can be expressed as:

in the case of the equation (15),

indicating belonging to an information symbol s^(k)The letters of the subvectors of (1).

Parallelized recursive block decoding according to embodiments of the present disclosure is based on block-by-block decoding₁,…,Γ_NParallelized determination of a set of candidate subvectors of a representation such that the set Γ_kComprising information symbols s^(k)One or more candidate sub-vectors of the k-th sub-vector of (1)

Wherein Card (gamma)_k) Specifying a set Γ_kIs strictly lower than the cardinality of the letter a to which the real and imaginary parts of the complex-valued vector of the information symbol belong. Thus, a set of candidate sub-vectors may be determined in parallel using two or more processors (also referred to as "processing units"), thereby enabling faster decoding and lower decoding complexity. The two or more processors may be configured to operate in parallel to determine candidate sub-vectors and store the candidate sub-vectors in the first stack 310, each processor being configured to determine at least a candidate sub-vector by applying a symbol estimation algorithm, the candidate sub-vector representing an estimate of a sub-vector of information symbols. Each processor may be further configured to store each determined candidate sub-vector in the first stack 310, along with a decoding metric associated with the candidate sub-vector, and a block level representing a level of the candidate sub-vector having the upper triangular channel matrix. A processor among the two or more processors may be configured to determine at least one candidate vector from the candidate sub-vectors stored in the first stack 310, the candidate vector representing an estimate of a vector of information symbols and being associated with an accumulated decoding metric determined from the decoding metrics stored with the candidate sub-vectors and configured to update the decoding metric threshold according to the accumulated decoding metric.

According to some embodiments, the decoder 300 may include a first processor 304 and a second processor 305 among two or more processors configured to operate in parallel to use the candidate sub-vectors

Filling the first stack 310, where k has a value between 1 and N, the candidate subvectors

Representing an information symbol s^(k)Is estimated.

The candidate sub-vectors stored in the first stack 310 may be

Associated with a decoding metric defined as:

in equation (16), the term

Candidate subvectors corresponding to intersymbol interference

Is based on the set Γ_jThe candidate subvectors previously determined in (j ═ k +1, …, N) are known.

The symbol estimation algorithm D associated with the k-th block can be applied^(k)Determining candidate subvectors based on satisfaction of decoding metric conditions

Wherein the decoding metric associated with the candidate sub-vector is based on the above condition

Must be less than or equal to_thA decoding metric threshold of the representation such that

Candidate subvectors stored in the first stack 310

May be further associated with a block level representing the level of the sub-vectors within the upper triangular channel matrix. Using block division symbols, with candidate sub-vectors

The associated block level is the index k.

Parallelized recursive block decoding according to embodiments of the present disclosure provides parallelization processing of different blocks such that the parallelization determines candidate sub-vectors corresponding to different sub-vectors of an information symbol, thereby enabling faster transmission of complete vector candidates s on the vector of the information symbol. Furthermore, the parallelized processing of the different blocks enables updating of the decoding metric threshold to be observed during the estimation of the candidate subvectors, determining a global solution or estimate on the vector of information symbols s each time a candidate subvector is determined for each subvector

The decoding metric threshold is updated.

Parallelized recursive block decoding starts with processing the last block at the block level equal to N (SB)_NTo apply a symbol estimation algorithm D by satisfaction of the decoding conditions on the decoding metric^(N)To determine the information symbol s^(N)At least one candidate sub-vector of the Nth sub-vector of

And (6) estimating. Once the first candidate subvector is determined

The rest of the blocks (SB) can be started_k(k — N-1, …, 1). Multiple processors may be implemented to process different blocks (SB) simultaneously_kTo determine the set Γ_kCandidate subvectors in (k-N-1, …,1)

Thus, the first processor 304 may be configured to determine the information symbols associated with the lowest block level by applying the estimation algorithm recursively starting from the subvector of information symbols associated with the highest block level until the subvector of information symbols associated with the lowest block level is reachedOne or more candidate sub-vectors associated with each sub-vector of an information symbol. This means that the first processor 304 may be configured to start processing the nth block (SB)_NThe processing includes applying a symbol estimation algorithm D^(N)To determine the set Γ_NIs estimated from one or more sub-vectors

Wherein t is_NAssigning subvector estimates

Has a value between 1 and Card (Γ)_N) In the meantime. Each time the first processor 304 determines a subvector estimate

Then the first processor 304 will find the sub-vector estimates

Block level and decoding metric corresponding to N for a first processing block

Stored together in the first stack 310. After finding the first subvector estimate

Thereafter, the first processor 304 continues the estimation process to determine the sum set Γ_NAll corresponding candidate subvectors. Once the first processor 304 terminates processing the Nth block (SB)_NIt is moved up with respect to the level of the sub-vector of the information symbol in order to process the N-1 th block (SB)_N-1. Block N-1 (SB)_N-1Comprises for the set Γ_NEach candidate sub-vector determined in (a)

Determining in the set Γ_N-1Candidate subvectors of (1)

The first processor 304 may be configured to determine each candidate sub-vector by

-performing interference cancellation and determining sub-vectors,

applying a symbol estimation algorithm D^(N-1)To determine satisfaction of metric conditions

Is selected a sub-vector

According to some embodiments, the decoding metric threshold m_thCan be initially set (e.g., by the first processor 304) as the euclidean distance between the received signal and the ZF-DFE estimate determined by applying a zero-forcing decision feedback equalizer to the received signal.

Once the first processor has executed the first operation in block N-1 (SB)_N-1It will move up to process the (N-2) th block (SB)_N-2And so on until the first block (SB) is reached₁. For candidate sub-vectors associated with block levels other than the highest block level equal to N, the first processor 304 may be configured to store the candidate sub-vectors together with candidate sub-vectors of previously processed blocks used in the interference cancellation step to find the candidate sub-vectors.

In parallel with the processing performed by the first processor 304, the second processor 305 may be configured to determine one or more candidate sub-vectors by recursively selecting sub-vectors in the stack associated with the lowest block level and determining candidate sub-vectors associated with each sub-vector of information symbols associated with block levels lower than the lowest block level by applying an estimation algorithm until the lowest block level of the channel matrix is reached.

This means that once the first processor 304 has determined the first candidate sub-vector

And stored in the first stack 310, the second processor 305 is activated. At this time, the first stack 310 includes only the candidate sub-vectors

Thus, the lowest block level in this case corresponds to the candidate sub-vector

The associated block level N. The second processor 305 selects candidate subvectors

And by processing k-N-1, …,1 is lower than the selected candidate subvector

Each block (SB) of the associated block level N_kAnd moves upward. The second processor 305 may be configured to process the k-th block (SB) when it is processed in the following manner_kDetermining candidate sub-vector in time-recursive manner

-performing interference cancellation to determine sub-vectors

Applying a symbol estimation algorithm D^(k)To determine candidate subvectors

Satisfying the metric condition

By processing the first block with a block level k of 1, the second processor 305 selecting candidate subvectors according to

Sum and under sum selected candidate subvectors

Associated information symbol s at block level k-N-1, …,1 of associated block level N^(k)Is determined by correlating the sub-vectors of (a) to (b) to determine candidate sub-vectors

To determine candidate vectors

Candidate vector

Representing an estimate of a vector of information symbols s. The second processor 305 may be configured to select a candidate sub-vector by comparing it with the selected candidate sub-vector

Associated decoding metrics

And the candidate subvectors

Associated decoding metrics

Add to determine a cumulative metric associated with the candidate vector

Wherein the candidate subvectors

Candidate subvectors being AND-and-lower-than-AND-select

The associated block level k-1, …, which is the lowest block level equal to N, is determined in association with the subvector of the information symbols associated with N-1 such that:

the second processor 305 may be further configured to determine candidate vectors

And accumulated decoding metrics

Together in a second stack 307.

Advantageously, parallelized recursive block decoding also enables on-line updating of the decoding metric threshold from the accumulated decoding metrics associated with the determined candidate vectors. Thus, a processor among the two or more processors included in the decoder 300 may be configured to order the first stack 310 according to a given order (increasing or decreasing) of decoding metrics associated with the stored candidate sub-vectors, and to threshold m decoding metrics_thUpdating to and candidate vector

Associated cumulative decoding metrics

So that

The processor may be further configured to remove from the first stack 310 candidate sub-vectors associated with decoding metrics above the updated decoding metric threshold.

The online updating of the decoding metric threshold may be performed by the second processor 305 or the third processor 306 comprised in the decoder 300, whenever a candidate vector is found

The third processor 306 is activated. In application of hard output decoding, the third processor 306 may be configured to determine/pass an estimate of a vector of information symbols from the candidate vector stored in the stack associated with the lowest accumulated decoding metric.

In applications for soft output decoding, the third processor 306 may be configured to calculate log-likelihood ratio values using the candidate vectors stored in the second stack 307 for approximating extrinsic information of different information bits carried by the original information symbols.

The decoder 300 may further include a real-to-complex converter 308 configured to transmit a complex-valued vector

As a pair of complex valued symbols s_cIs estimated. The obtained candidate vectors may then be used

Conversion to a complex valued vector

Make component(s)

Given by:

in equation (18), (u)_jRepresenting the jth element of vector u.

According to some embodiments, one or more symbol estimation algorithms that may be previously determined or loaded from a memory locationMedium selection symbol estimation algorithm D^(k)。

According to some embodiments, the symbol estimation algorithm D for k 1, …, N is predetermined depending on the signal-to-noise ratio and/or the computational power of the device or system implementing parallelized recursive block decoding and/or the outage capacity of the transmission channel^(k). Furthermore, the symbol estimation algorithm D for k-1, …, N may be predetermined depending on the desired target quality of service metric (e.g., target achievable transmission rate)^(k)。

According to one embodiment, symbol estimation algorithm D^(k)May be similar.

According to another embodiment, the symbol estimation algorithm D^(k)May be different.

In some embodiments, symbol algorithm D may be selected in the group comprising sequential decoding algorithm, linear decoding algorithm (e.g., ZF or MMSE decoder), or non-linear ZF-DFE decoder^(k)Where k is 1, …, N.

At a given sub-block (SB)_kIn embodiments using a sequential decoding algorithm, the block metric is minimized by minimizing the block metric according to

Thus, the corresponding symbol estimation algorithm D^(k)Transferable estimation

Sequential decoding algorithms such as Sphere Decoder (SD), Stack decoder and SB Stack decoder (SB-Stack) can be used to solve equation (19).

Furthermore, in some embodiments, the upper triangular sub-matrix R may be subjected to prior to estimating the candidate sub-vectors, e.g., using lattice reduction and/or MMSE-GDFE filtering^(k)Pre-processing is performed.

With reference to fig. 4, there is also provided a method for determining an estimate of a vector of information symbols carried by a signal received over a transmission channel represented by a channel matrix. The received signal may be written into a real-valued system according to equation (6) and equivalently represented using QR decomposition as expressed by equation (7).

At step 401, partitioning the channel matrix R into sub-matrices may be performed to vector information symbols

Into two or more sub-vectors of information symbols. Vector quantity

Therefore, N ≧ 2 subvectors can be divided so that

Subvectors of index k

Has a length of l_kNot less than 1. The upper triangular matrix R may be divided into two or more sub-matrices according to equation (10).

At step 403, Γ may be determined by applying a symbol estimation algorithm₁,…,Γ_NSet of candidate subvectors of the representation such that the set Γ_kComprising information symbols s^(k)One or more candidate sub-vectors of the k-th sub-vector of (1)

Wherein Card (gamma)_k) Specifying a set Γ_kIs strictly lower than the cardinality of the letter a to which the real and imaginary parts of the complex-valued vector of the information symbol belong. The set of candidate subvectors may be determined by two or more processors operating in parallel. The step 403 of determining candidate subvectors may comprise the sub-steps of: for determining, by each of two or more processors, at least one candidate sub-vector by applying a symbol estimation algorithm, the candidate sub-vector tableAn estimate of a sub-vector of information symbols.

At step 405, at least one candidate sub-vector of information symbols may be stored in a first stack together with a decoding metric and a block level representing the level of the candidate sub-vector within the channel matrix R, the decoding metric being lower than or equal to a decoding metric threshold.

At step 407, at least one candidate vector may be determined from the candidate sub-vectors stored in the first stack, the candidate vector representing an estimate of a vector of information symbols and being associated with an accumulated decoding metric determined from the decoding metrics stored with the candidate sub-vectors, and a decoding metric threshold updated from the accumulated decoding metric.

The methods and apparatus described herein may be implemented in various ways, such as in hardware, software, or a combination thereof. In a hardware implementation, the processing elements of decoder 300 may be implemented, for example, in a hardware-only configuration (e.g., in one or more FPGA, ASIC, or VLSI integrated circuits with corresponding memory) or in a configuration using both VLSI and DSP.

Fig. 5 shows an exemplary hardware architecture of a decoder 300 according to some embodiments of the invention. The hardware architecture may be implemented in a machine or computer-implemented device. As shown, the decoder 300 may include various computing, storage, and communication units that may interact with each other through the data and address ports 59, and include:

an input peripheral 51 for receiving input data, e.g. from a receiving antenna;

processing peripherals 53 comprising one or more microprocessors (CPUs), such as FPGAs or ASICs, configured for example to execute corresponding instructions to execute the methods and algorithms according to embodiments of the invention;

a storage peripheral 55, possibly comprising a Random Access Memory (RAM) or a read-only memory, to store, for example, a first stack and a second stack comprising candidate sub-vectors of information symbols and candidate vectors of information symbols; and

output peripherals 57 including communication units such as displays enabling human-machine interaction between the receiver device 21 and a MIMO system administrator, for example, for configuration and maintenance purposes.

Although embodiments of the present invention have been manually described with reference to a symmetric MIMO configuration featuring the same number of transmit and receive antennas, it should be noted that the present invention is also applicable to n_t<n_rAsymmetric MIMO configuration of (1). A linear representation in the form of equation (6) can also be obtained by performing step 601 a complex to real conversion to an equivalent system:

in equation (20), the matrices U and V are derived from matrix H along with matrix D_c＝UDV^tThe unitary matrix obtained by singular value decomposition. D is a diagonal matrix with positive diagonal entries representing matrix H_cThe singular value of (a). Upper label

Representing the Hermitian pair transposer.

Furthermore, although some embodiments of the present invention have been described in relation to a wireless single-user MIMO system, it should be noted that the present invention is not limited to such applications. The invention may be integrated in any receiver device operating in any linear communication system characterized by a linear representation of the channel output. The communication system may be wired, wireless, or fiber optic-based, accommodating single or multiple users, employing single or multiple antennas, and single or multiple carrier communication techniques. For example, the invention may be integrated in a receiver device implemented in a wireless distributed MIMO system. Distributed MIMO may be used, for example, in cellular communications applied in 3G, 4G, LTE, and future 5G standards, among others. For example, cooperative communication applied in ad hoc networks (wireless sensor networks, machine-to-machine communication, internet of things (IoT), etc.) is also an example of a distributed MIMO system. In addition to wireless networks, the present invention may be integrated into optical receiver devices implemented in optical fiber-based communication systems, such as polarization division multiplexing-OFDM (PDM-OFDM) systems.

Furthermore, the invention is not limited to communication devices and may be integrated into signal processing devices, such as Finite Impulse Response (FIR) electronic filters used in audio applications such as audio dividers and audio mastering. Thus, given an output sequence of FIR filter of order M, some embodiments may be used to determine an estimate of the input sequence.

In another application, the methods, apparatus and computer program products according to some embodiments of the present invention may be implemented in Global Navigation Satellite Systems (GNSS) such as IRNSS, Beidou, GLONASS, Galileo; the GPS includes, for example, at least one GPS receiver for estimating positioning parameters using, for example, carrier phase measurements.

Furthermore, methods, apparatuses and computer program products according to some embodiments of the present invention may be implemented in a cryptographic system for determining an estimate of a private secret value for use in a cryptographic algorithm to encrypt/decrypt data or messages during their storage, processing or communication. In lattice-based encryption applications, data/messages are encrypted in lattice points. According to some embodiments of the present invention, decryption of such encrypted data may advantageously be performed, thereby achieving a high likelihood of successful recovery of the secret value with reduced complexity.

Further, the methods described herein may be implemented by computer program instructions provided to a processor of any type of computer to produce a machine having a processor that executes the instructions to implement the functions/acts specified herein. These computer program instructions may also be stored in a computer-readable medium that can direct a computer to function in a particular manner. To this end, the computer program instructions may be loaded onto a computer to cause a series of operational steps to be performed and to thereby produce a computer implemented process such that the instructions which execute provide processes for implementing the functions specified herein.

While embodiments of the invention have been illustrated by a description of various examples and while these embodiments have been described in considerable detail, it is not the intention of the applicants to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, and representative methods and illustrative examples are shown and described.

Claims (9)

1. A decoder (300) for determining an estimate of a vector of information symbols carried by a signal received over a transmission channel represented by a channel matrix, wherein the decoder comprises:

-a block dividing unit (303) configured to divide the vector of information symbols into two or more sub-vectors of information symbols in accordance with dividing the channel matrix into sub-matrices, each sub-vector being associated with a block level, the block level representing a level of the sub-vectors in the channel matrix;

-two or more processors configured to operate in parallel for determining candidate sub-vectors and storing the candidate sub-vectors in a first stack (310), each of the two or more processors being configured to determine at least one candidate sub-vector representing an estimate of a sub-vector of an information symbol by applying a symbol estimation algorithm and to store the at least one candidate sub-vector of the information symbol in the first stack (310) with a decoding metric and a block level representing a level of the candidate sub-vector within the channel matrix, the decoding metric being lower than or equal to a decoding metric threshold, a processor among the two or more processors being configured to determine at least one candidate vector from the candidate sub-vectors stored in the first stack (310), the candidate vector represents an estimate of the vector of information symbols and is associated with an accumulated decoding metric determined from decoding metrics stored with the candidate sub-vectors and configured to update the decoding metric threshold in accordance with the accumulated decoding metric.

2. The decoder of claim 1, wherein the two or more processors comprise:

-a first processor (304) configured to determine one or more candidate sub-vectors associated with each sub-vector of information symbols by applying an estimation algorithm recursively starting from the sub-vector of information symbols associated with the highest block level until reaching the sub-vector of information symbols associated with the lowest block level, the first processor (304) being configured to store each candidate sub-vector in the first stack (310);

-a second processor (305) configured to determine a candidate sub-vector associated with each sub-vector of information symbols associated with a block level below the lowest block level by recursively selecting the sub-vector associated with the lowest block level in the first stack (310) and by applying a symbol estimation algorithm until the lowest block level of the channel matrix is reached, the second processor (305) being further configured to determine a candidate vector from the selected candidate sub-vector and candidate sub-vectors determined in association with sub-vectors of information symbols associated with block levels below the lowest block level, the candidate vector representing an estimate of a vector of the information symbols, the second processor (305) being further configured to determine a candidate vector by correlating a decoding metric associated with the selected candidate sub-vector with sub-vectors of information symbols determined in association with sub-vectors of information symbols associated with block levels below the lowest block level, the second processor (305) being further configured to determine a candidate vector from the selected candidate sub-vector and candidate sub-vectors determined in association with sub-vectors of information symbols associated with block levels below the lowest block level Selecting a sub-vector associated decoding metric to add to determine an accumulated metric associated with the candidate vector, the second processor (305) being configured to store the candidate vector in a second stack (307) with the accumulated decoding metric, the decoding metric threshold being updated to the accumulated decoding metric.

3. The decoder of claim 2, wherein a processor among the two or more processors is configured to:

-ordering the first stack (310) according to a given order of decoding metrics associated with the candidate sub-vectors,

-updating the decoding metric threshold to the accumulated decoding metric associated with the candidate vector,

-removing candidate sub-vectors associated with decoding metrics above an updated decoding metric threshold from the first stack (310), and

-determining an estimate of a vector of information symbols from the candidate vector associated with the lowest accumulated decoding metric stored in the second stack (307).

4. Decoder according to any of the preceding claims 1 and/or 2, wherein the symbol estimation algorithm is selected in the group comprising: a trellis decoding algorithm, a zero forcing algorithm, a minimum mean square error algorithm, and a zero forcing decision feedback equalizer.

5. Decoder according to claim 4, wherein the symbol estimation algorithm comprises a pre-processing step using a lattice reduction algorithm and/or MMSE-GDFE filtering.

6. Decoder according to any of the preceding claims 1 and/or 2, wherein the symbol estimation algorithm is predetermined depending on a signal-to-noise ratio and/or an outage capacity.

7. Decoder according to any of the preceding claims 1 and/or 2, wherein the symbol estimation algorithm is predetermined in dependence on a target quality of service metric selected in the group comprising a target achievable transmission rate.

8. Decoder according to claim 1, wherein the block division unit (303) is configured to divide the vector of information symbols according to a set of division parameters comprising a number of blocks at least equal to two representing the number of sub-vectors of information symbols and a block length representing the number of information symbols comprised in a sub-vector of information symbols.

9. A method for determining an estimate of a vector of information symbols carried by a signal received over a transmission channel represented by a channel matrix, wherein the method comprises:

-dividing the vector of information symbols into two or more sub-vectors of information symbols, each sub-vector being associated with a block level representing a level of the sub-vector in the channel matrix, in dependence on dividing the channel matrix into sub-matrices;

-determining, by two or more processors operating in parallel, candidate sub-vectors and storing the candidate sub-vectors in a first stack, the step of determining candidate sub-vectors comprising:

determining, by each processor of the two or more processors, at least one candidate sub-vector by applying a symbol estimation algorithm, the candidate sub-vector representing an estimate of a sub-vector of information symbols, and

storing at least one candidate sub-vector of the information symbols in the first stack with a decoding metric and a block level representing a level of the candidate sub-vector within the channel matrix, the decoding metric being lower than or equal to a decoding metric threshold,

the method further comprises determining at least one candidate vector from candidate sub-vectors stored in the first stack, the candidate vector representing an estimate of a vector of the information symbols and being associated with an accumulated decoding metric determined from decoding metrics stored with the candidate sub-vectors, and updating the decoding metric threshold from the accumulated decoding metric.

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