CN113472701A - Method, device and equipment for processing routing information and storage medium - Google Patents
Method, device and equipment for processing routing information and storage medium Download PDFInfo
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- CN113472701A CN113472701A CN202010244932.6A CN202010244932A CN113472701A CN 113472701 A CN113472701 A CN 113472701A CN 202010244932 A CN202010244932 A CN 202010244932A CN 113472701 A CN113472701 A CN 113472701A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/54—Organization of routing tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The application provides a method, a device, equipment and a storage medium for processing routing information. The method comprises the following steps: acquiring an identification code ID of an effective target chip; acquiring a link connection relation between a source chip and the target chip from a route sending table according to the ID of the target chip in sequence, and processing route information under the ID of the target chip according to the link connection relation; when the effective signal down-hop of the link is detected, acquiring the ID of a target chip where the link with the effective signal down-hop is located; and skipping processing the routing information under the ID of the target chip of the link where the effective signal is skipped.
Description
Technical Field
The present application relates to the field of routing data exchange technologies, and in particular, to a method, an apparatus, a device, and a storage medium for processing routing information.
Background
The routing system is a key component in the packet switching system, and comprises the parts of updating routing information, sending routing information, searching routing and the like. The transmission process of the routing information is mainly to complete the generation and transmission functions of routing protocol cells by operating a routing transmission table. Each line content of the routing sending table shows the link connection relation of a path between a source chip and a destination chip, the on-off link relation is calculated to obtain reachable information DR of the link, the DR information is filled into a routing protocol cell and sent to the upstream, the upstream routing table is updated, and the self-routing process of the switching system is realized.
The routing information transmission is to read the routing transmission table by using the ID number DST _ ID of the destination chip as a row address, generally, the routing transmission table is read from the ID number of the minimum destination chip to obtain the link connection relation, and the link connection relation and the effective signal of the current link are used for completing the calculation of DR information. And when the timing of the routing protocol cell sending interval counter reaches a preset sending interval, sequentially assembling routing protocol cells which accord with the definition according to the version number of the sending cell, the calculated DR information, the ID number of the destination chip, the level of the source chip, the ID number of the link and the like, and sending the routing protocol cells out from the current link. And for the destination chip address, after the routing protocol cell sending operation of the current LINK is completed from the minimum LINK number LINK _ ID being 0, jumping to the next LINK, namely the LINK _ ID being LINK _ ID +1, and continuing to complete the routing sending process. And after the destination chip address completes a round of traversal of the LINK _ ID, reading the routing sending table by taking the DST _ ID +1 as the row address, and also completing a round of routing sending process of the LINK _ ID, thus circularly completing the generation and sending of routing protocol cells of the whole routing sending table.
For the effective signal down-hop condition caused by the board pulling operation or the system hardware environment abnormality, the system cannot respond to the abnormality in time, which causes a large amount of packet loss of the switching system, and needs to execute the generation and sending operation of the routing protocol cell of the whole routing sending table, which consumes a large amount of time.
Disclosure of Invention
The application provides a processing method, a processing device and a storage medium for routing information, which can reduce the packet loss rate of a switching system and improve the efficiency of routing information processing.
An embodiment of the present application provides a method for processing routing information, including:
acquiring an identification code ID of an effective target chip;
acquiring a link connection relation between a source chip and the target chip from a route sending table according to the ID of the target chip in sequence, and processing route information under the ID of the target chip according to the link connection relation;
when the effective signal down-hop of the link is detected, acquiring the ID of a target chip where the link with the effective signal down-hop is located;
and skipping processing the routing information under the ID of the target chip of the link where the effective signal is skipped.
An embodiment of the present application provides a processing apparatus for routing information, including:
the effective target chip ID acquisition module is used for acquiring the identification code ID of the effective target chip;
the first routing information processing module is used for acquiring the link connection relation between a source chip and the destination chip from a routing sending table according to the ID of the destination chip in sequence and processing the routing information under the ID of the destination chip according to the link connection relation;
the effective signal down-hop detection module is used for acquiring the ID of a target chip where the link with the effective signal down-hop occurs when the link is detected to have the effective signal down-hop;
and the second routing information processing module is used for skipping the routing information under the ID of the destination chip of the link where the effective signal is skipped.
The embodiment of the present application provides a communication device, which includes a memory, a processor, and a computer program stored on the memory and capable of running on the processor, and when the processor executes the program, the processor implements the method for processing the routing information according to the embodiment of the present application.
The embodiment of the present application provides a storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for processing routing information in any embodiment of the present application is implemented.
Drawings
Fig. 1 is a flowchart of a method for processing routing information in an embodiment of the present application;
fig. 2 is a schematic diagram of a routing table in an embodiment of the present application;
FIG. 3 is a schematic block diagram of a single stage switching system in an embodiment of the present application;
fig. 4 is a schematic diagram of a routing table in an embodiment of the present application;
fig. 5 is a schematic structural diagram of a routing information processing apparatus in an embodiment of the present application;
fig. 6 is a schematic structural diagram of an apparatus in an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
In an embodiment, fig. 1 is a flowchart of a method for processing routing information according to an embodiment of the present application, and the embodiment is suitable for a case of processing routing information. This embodiment may be implemented by a switching device. As shown in fig. 1, the method provided by the present embodiment includes S110-S140.
S110, obtaining the identification code ID of the effective target chip.
And S120, acquiring the link connection relation between the source chip and the destination chip from the route sending table according to the ID of the destination chip in sequence, and processing the route information under the ID of the destination chip according to the link connection relation.
S130, when the link is detected to have the effective signal down-hop, the ID of the destination chip of the link where the effective signal down-hop occurs is obtained.
S140, the routing information under the ID of the target chip of the link where the effective signal is down-hopped is processed in a skipping mode.
The effective target chip may be understood as a chip used in the context of the present application, and the target chip may be an SA chip. The ID of the destination chip may be written as DST _ ID.
In one embodiment, the manner of obtaining the identification code ID of the valid destination chip may be: determining an invalid destination chip according to the physical connection information of the route; and adopting a mode of configuring a mask to shield the invalid destination chip ID.
Wherein the invalid destination chip may be a destination chip to which no physical connection is made. After the invalid target chip ID is shielded, the routing information under the invalid target chip ID does not need to be processed, so that the efficiency of routing convergence is improved.
In an embodiment, the routing table may be set in advance or established by a routing update method, and fig. 2 is a schematic diagram of a routing table in the embodiment of the present application, where as shown in fig. 2, each row in the routing table is a link connection relationship corresponding to a destination chip ID, and each column is link information.
In one embodiment, after obtaining the ID of the valid destination chip, the ID of the destination chip is sequentially used as the row address to read the routing table according to the sequence from small to large or from large to small of the ID number, so as to obtain the link connection relationship under the ID of the current destination chip, and then the routing information under the current destination chip is processed according to the link connection relationship.
In one embodiment, the process of processing the routing information under the destination chip ID according to the link connection relationship may be: traversing a link contained in the ID of the destination chip; when traversing to the current link, generating a routing protocol cell of the current link; and sending out the routing protocol cell through the current link and continuously traversing the next link.
In one embodiment, when traversing to the LINK _ ID of the current LINK, DR information is obtained by calculation according to the traffic information of the current LINK and the LINK connection relationship, and a routing protocol cell conforming to the definition is assembled in sequence according to the version number of the sending cell, the calculated DR information, the ID number of the destination chip, the level of the source chip, the ID number of the LINK, and the like, and the routing protocol cell is sent out through the current LINK. And continuously traversing the next LINK LINK _ ID +1 until the LINK under the current target chip ID is traversed and the routing information under the current target chip ID is processed.
In one embodiment, a valid signal down-jump may be caused by a unplugging operation or a hardware environment exception. And when the effective signal is detected to be down-hopped, acquiring the ID of the target chip of the link where the effective signal is down-hopped, and if the routing information under the current target chip ID is not processed, continuing to process the routing information under the current target chip ID until the routing information under the current target chip ID is processed.
In one embodiment, if it is detected that there is one link having a valid signal down-hop, after the routing information under the current destination chip ID is processed, the routing information under the destination chip ID of the link having the valid signal down-hop is processed by skipping.
In one embodiment, after the jump processing is performed on the routing information under the destination chip ID of the link where the effective signal down-hop occurs, the method further includes the following steps: and after the routing information under the ID of the target chip of the link with the effective signal down-hop is processed, continuing to process the routing information under the ID of the next effective target chip of the link with the effective signal down-hop.
In one embodiment, if a plurality of links in which effective signal hops down occur are detected, a cache with a set depth is created; and storing the ID of the destination chip where the unprocessed link with the effective signal down-hop is located into a cache.
Wherein, a plurality of links in which effective signal down-hopping occurs may or may not be detected simultaneously. For example: it may be that another valid signal down-hop is detected while processing the routing information under the destination chip ID of the link where the valid signal down-hop occurred. The set depth may be determined by the number of links.
In one embodiment, the ID of the destination chip where the unprocessed link with the effective signal down-hopping occurs is stored in the cache, and the skipping sequentially processes the routing information under the ID of the destination chip in the cache according to the sequence from small to large of the ID of the destination chip. In this embodiment, the lowest DST _ ID corresponding to the down link is processed first, and the others are also processed one by one according to the order of the DST _ ID addresses.
In one embodiment, before the jump processing is performed on the routing information under the destination chip ID of the link where the effective signal down-jump occurs, the method further includes the following steps: if the routing information under the current target chip ID is not processed, continuing to process the routing information under the current target chip ID; until the routing information processing under the current destination chip ID is completed.
In one embodiment, after acquiring the ID of the destination chip of the link where the valid signal down-hop occurs, the method further includes the following steps: judging whether a target chip where a link with the effective signal down-hopping occurs is the first effective signal down-hopping in the current period; if not, the effective signal down-jump is ignored. And after the routing information under the current target chip ID is processed, continuing to process the routing information under the next effective target chip ID of the current target chip. This is to ensure that the same destination chip ID can only be interrupted once in a cycle.
In one embodiment, after the routing information under all the destination chip IDs in the cache is processed, the routing information under the next valid destination chip ID of the last destination chip in the cache is continuously processed.
Illustratively, fig. 3 is a schematic diagram of a single-stage switching system, as shown in fig. 3, including 4 effective destination chips with DST _ IDs of 0, 1, 1021, and 1023, two switching units, switching unit 0# and switching unit 12 #. The switching unit 0# and the switching unit 12# in the switching system respectively have a link to be connected with 4 destination chips. After the system routing information is updated, the routing table established by the switching unit 0# is as shown in fig. 4, the row of the routing table in the black frame indicates an effective link between the switching unit 0# and the SA chips whose DST _ IDs are 0, 1, 1021, and 1023, and the other rows all 0 indicate that the switching unit 0# and the destination chip corresponding to the address have no effective link. In the process of processing the routing information, the switching unit 0# masks a destination chip DST _ ID which is not used in an actual application scene by using a mask, and responds by interrupting the DST _ ID address jump when an effective signal jumps down, wherein the processing process is processed according to the following steps:
step 1: and reading the routing table by taking the DST _ ID as 0 as a row address to obtain the link connection relation of the DST _ ID. And finishing the generation and transmission operation of the routing protocol information element from the time when the LINK _ ID is 0. And after the LINK is completed, jumping to the LINK with the LINK _ ID being equal to LINK _ ID +1 number to continue to complete the generation and sending processes of the routing protocol cells. After the LINK _ ID-191 LINK processing procedure is completed, sending of all LINK routing protocol cells with the addresses DST _ ID-0 is completed;
step 2: and reading the routing transmission table by taking the DST _ ID as 1 to finish the routing cell transmission process under the DST _ ID. Then, the above process is repeated with the row address of DST _ ID 1021 and DST _ ID 1023, respectively.
And step 3: in step 1, when detecting that valid signal down-jump occurs in DST _ ID 1021, immediately after completing step 1, jump to DST _ ID 1021 and process. After all the link routing protocol cells are finished under the condition that DST _ ID is 1021, the route sending table is read by taking the DST _ ID as 1023 as a row address to finish the generation and sending of the routing protocol cells without carrying out address jump back to the condition that DST _ ID is 1.
And 4, step 4: when detecting the link down-jump in step 3, detecting that other links generate effective signal down-jumps, setting a buffer with a depth of 192 according to the maximum value of the link number to store unprocessed DST _ ID, wherein the same DST _ ID can only be interrupted once, and then processing one by one according to the order of the DST _ ID address size. For the situation that several links LV are detected to be down-hopped at the same time, the one with the minimum DST _ ID corresponding to the down-hopped link is processed first, and the others are processed one by one according to the order of the DST _ ID addresses.
In an embodiment, fig. 5 is a schematic structural diagram of a routing information processing apparatus provided in an embodiment of the present application. As shown in fig. 5, the apparatus includes: a valid destination chip ID obtaining module 210, a first routing information processing module 220, a valid signal down-hop detecting module 230, and a second routing information processing module 240.
A valid destination chip ID obtaining module 210, configured to obtain an identification code ID of a valid destination chip;
a first routing information processing module 220, configured to sequentially obtain a link connection relationship between a source chip and a destination chip from a routing sending table according to the ID of the destination chip, and process routing information under the ID of the destination chip according to the link connection relationship;
the valid signal down-hop detection module 230 is configured to, when it is detected that a link is down-hopped by a valid signal, obtain an ID of a destination chip where the link is located where the valid signal is down-hopped;
and a second routing information processing module 240, configured to skip the routing information under the destination chip ID of the link where the effective signal is skipped.
In one embodiment, the valid destination chip ID obtaining module 210 is further configured to:
determining an invalid destination chip according to the physical connection information of the route;
and shielding the invalid destination chip by adopting a mode of configuring a mask.
In one embodiment, further comprising:
if one link in which the effective signal is down-hopped is detected and the routing information under the current target chip ID is not processed, continuing to process the routing information under the current target chip ID; until the routing information processing under the current destination chip ID is completed.
In one embodiment, the valid signal down-hop detection module 230 is further configured to:
if a plurality of links with effective signal down-hopping are detected, establishing a cache with a set depth;
and storing the ID of the destination chip where the unprocessed link with the effective signal down-hop to the cache.
In one embodiment, the second routing information processing module 240 is further configured to:
and skipping to sequentially process the routing information under the target chip in the cache according to the sequence from small ID to large ID of the target chip.
In one embodiment, after acquiring the ID of the destination chip where the link where the valid signal down-hop occurs, the method further includes:
judging whether a target chip where a link with the effective signal down-hopping occurs is the first effective signal down-hopping in the current period; if not, the effective signal down-jump is ignored.
In one embodiment, after the jump processing is performed on the routing information under the destination chip ID of the link where the effective signal down-jump occurs, the method further includes:
and after the routing information under the ID of the target chip of the link with the effective signal down-hop is processed, continuing to process the routing information under the ID of the next effective target chip of the link with the effective signal down-hop.
In one embodiment, the first routing information processing module 220 is further configured to:
traversing a link contained in the ID of the destination chip;
when traversing to the current link, generating a routing protocol cell of the current link;
and sending the routing protocol cell out through the current link and continuously traversing the next link.
Fig. 6 is a schematic structural diagram of an apparatus provided in an embodiment of the present application. As shown in fig. 6, the present application provides an apparatus comprising: a processor 310 and a memory 320. The number of the processors 310 in the device may be one or more, and one processor 310 is taken as an example in fig. 6. The number of the memories 320 in the device may be one or more, and one memory 320 is taken as an example in fig. 6. The processor 310 and the memory 320 of the device may be connected by a bus or other means, as exemplified by the bus connection in fig. 6. In an embodiment, the device is a receiving end. The receiving end may be one of a scheduling node, a base station, or a UE.
The memory 320, as a computer-readable storage medium, may be configured to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the apparatus of any embodiment of the present application (e.g., the encoding module and the first transmitting module in the data transmission device). The memory 320 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the device, and the like. Further, the memory 320 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 320 may further include memory located remotely from the processor 310, which may be connected to the device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The apparatus provided above may be configured to execute the processing method applied to the routing information provided in any of the embodiments above, and has corresponding functions and effects.
The program stored in the corresponding memory 320 may be program instructions/modules corresponding to the signal processing method provided in the embodiment of the present application, and the processor 310 executes one or more functional applications and data processing of the computer device by executing the software program, instructions and modules stored in the memory 320, that is, implementing the signal processing method applied in the embodiment of the method described above. It can be understood that, when the device is a receiving end, the method applied to signal processing provided in any embodiment of the present application may be performed, and has corresponding functions and effects. The device may be one of a base station or a UE.
Embodiments of the present application also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a method for processing routing information, the method including: acquiring an identification code ID of an effective target chip; acquiring a link connection relation between a source chip and the target chip from a route sending table according to the ID of the target chip in sequence, and processing route information under the ID of the target chip according to the link connection relation; when the link is detected to have the effective signal down-hop, acquiring the ID of the target chip of the link where the effective signal down-hop occurs, and continuously processing the routing information under the ID of the current target chip; and after the routing information under the current target chip ID is processed, skipping the routing information under the target chip ID of the link with the effective signal skipping.
It will be clear to a person skilled in the art that the term user equipment covers any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers or vehicle-mounted mobile stations.
In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages.
Any logic flow block diagrams in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The Memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read-Only Memory (ROM), Random Access Memory (RAM), optical storage devices and systems (Digital Video Disc (DVD) or Compact Disc (CD)), etc. The computer readable medium may include a non-transitory storage medium. The data processor may be of any type suitable to the local technical environment, such as but not limited to general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Programmable logic devices (FGPAs), and processors based on a multi-core processor architecture.
The above description is only exemplary embodiments of the present application, and is not intended to limit the scope of the present application.
Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine related instructions, microcode, firmware instructions, state setting data, or source code or destination code written in any combination of one or more programming languages.
The foregoing has provided by way of exemplary and non-limiting examples a detailed description of exemplary embodiments of the present application. Various modifications and adaptations to the foregoing embodiments may become apparent to those skilled in the relevant arts in view of the following drawings and the appended claims without departing from the scope of the invention. Therefore, the proper scope of the invention is to be determined according to the claims.
Claims (11)
1. A method for processing routing information is characterized by comprising the following steps:
acquiring an identification code ID of an effective target chip;
acquiring a link connection relation between a source chip and the target chip from a route sending table according to the ID of the target chip in sequence, and processing route information under the ID of the target chip according to the link connection relation;
when the effective signal down-hop of the link is detected, acquiring the ID of a target chip where the link with the effective signal down-hop is located;
and skipping processing the routing information under the ID of the target chip of the link where the effective signal is skipped.
2. The method of claim 1, wherein obtaining the identification code ID of the valid destination chip comprises:
determining an invalid destination chip according to the physical connection information of the route;
and shielding the invalid destination chip ID by adopting a mode of configuring a mask.
3. The method of claim 1, wherein before the forwarding process the routing information under the destination chip ID of the link where the valid signal down-hop occurs, further comprising:
if the routing information under the current target chip ID is not processed, continuing to process the routing information under the current target chip ID; and finishing the processing of the routing information under the current destination chip ID.
4. The method of claim 1, wherein when it is detected that a valid signal down-hop occurs in a link, acquiring an ID of a destination chip where the link where the valid signal down-hop occurs is located, includes:
if a plurality of links with effective signal down-hopping are detected, establishing a cache with a set depth;
and storing the ID of the destination chip where the unprocessed link with the effective signal down-hop to the cache.
5. The method of claim 4, wherein the skipping processes the routing information under the destination chip ID of the link where the effective signal is skipped, including:
and skipping to sequentially process the routing information under the target chip ID in the cache according to the sequence from small to large of the target chip ID.
6. The method of claim 1, after obtaining the ID of the destination chip of the link where the valid signal down-hop occurs, further comprising:
judging whether a target chip where a link with the effective signal down-hopping occurs is the first effective signal down-hopping in the current period; if not, the effective signal down-jump is ignored.
7. The method of claim 1, wherein after the forwarding process the routing information under the destination chip ID of the link where the effective signal down-hop occurs, further comprising:
and after the routing information under the ID of the target chip of the link with the effective signal down-hop is processed, continuing to process the routing information under the ID of the next effective target chip of the ID of the target chip of the link with the effective signal down-hop.
8. The method according to any one of claims 1 to 7, wherein processing the routing information under the destination chip ID according to the link connection relationship comprises:
traversing a link contained in the ID of the destination chip;
when traversing to the current link, generating a routing protocol cell of the current link;
and sending the routing protocol cell out through the current link and continuously traversing the next link.
9. An apparatus for processing routing information, comprising:
the effective target chip ID acquisition module is used for acquiring the identification code ID of the effective target chip;
the first routing information processing module is used for acquiring the link connection relation between a source chip and the destination chip from a routing sending table according to the ID of the destination chip in sequence and processing the routing information under the ID of the destination chip according to the link connection relation;
the effective signal down-hop detection module is used for acquiring the ID of a target chip where the link with the effective signal down-hop occurs when the link is detected to have the effective signal down-hop;
and the second routing information processing module is used for skipping the routing information under the ID of the destination chip of the link where the effective signal is skipped.
10. A communication device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of processing routing information according to any of claims 1-8 when executing the program.
11. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method of processing routing information according to any one of claims 1 to 8.
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| CN202010244932.6A CN113472701B (en) | 2020-03-31 | 2020-03-31 | Processing method, device, equipment and storage medium of route information |
| PCT/CN2021/083384 WO2021197234A1 (en) | 2020-03-31 | 2021-03-26 | Method, apparatus and device for processing routing information, and storage medium |
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| CN202010244932.6A CN113472701B (en) | 2020-03-31 | 2020-03-31 | Processing method, device, equipment and storage medium of route information |
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| CN113472701B (en) | 2023-10-10 |
| WO2021197234A1 (en) | 2021-10-07 |
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