CN113471093B - Film morphology prediction method and device for semiconductor device - Google Patents
Film morphology prediction method and device for semiconductor device Download PDFInfo
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- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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Abstract
The invention discloses a film morphology prediction method and device for a semiconductor device. The film morphology prediction method comprises the following steps: and reading a substrate image, wherein the substrate image is provided with a micro-nano structure pattern. And extracting a plurality of surface contour sites from the substrate image, wherein the plurality of surface contour sites are all position points positioned at the edge of the micro-nano structure pattern. The expected reaction rate for each surface profile site is determined based on the location of the surface profile site and the target process parameters. The film thickness variation of each surface profile site was calculated using the preset process time and the expected reaction rate. And updating the interface of the micro-nano structure graph edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology of the semiconductor device. The invention provides a film morphology prediction result for guiding the design, development and optimization of a film process, and the technical purposes of realizing process design expectation, reducing research and development cost, promoting research and development progress and the like can be achieved based on the scheme of the invention.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method and a device for predicting the morphology of a thin film of a semiconductor device.
Background
Currently, the manufacturing process of large-scale integrated circuits mainly comprises a thin film process, a photolithography process, a high temperature process, a doping process, a wiring process and the like. The photoetching process, the doping process and the interconnection metal wiring process are all completed on the basis of the assistance of a thin film process, and the thin film process has a critical influence on the design and the manufacture of an integrated circuit. The thin film process mainly includes a deposition process, which is to grow a thin film having a specific function on a semiconductor substrate, and an etching process, which is to remove a thin film having a certain thickness by dry etching or wet etching.
As transistor dimensions continue to approach physical limits, integrated circuit fabrication process difficulties and costs continue to increase, and technology iteration speed and mass production efficiency requirements increase year by year. This is becoming more and more difficult for thin film processes that are the basis and core of integrated circuit fabrication. Therefore, how to reduce the difficulty of developing and designing the thin film process and reduce the input cost of the thin film process becomes the key point of technical problems and researches to be solved urgently by those skilled in the art.
Disclosure of Invention
In order to solve the problems of high difficulty, high cost and the like in the conventional thin film process design, one or more embodiments of the present invention can provide a thin film morphology prediction method and apparatus for a semiconductor device, so as to reduce the difficulty of thin film process development and reduce the cost input of thin film process development.
To achieve the above technical object, the present invention can provide a thin film profile prediction method for a semiconductor device, which specifically includes, but is not limited to, one or more of the following steps.
And reading a substrate image, wherein the substrate image is provided with a micro-nano structure pattern.
And extracting a plurality of surface contour sites from the substrate image, wherein the plurality of surface contour sites are all position points positioned at the edge of the micro-nano structure graph.
The expected reaction rate for each surface profile site is determined based on the location of the surface profile site and the target process parameters.
And calculating the film thickness variation of each surface contour site by using the preset process time and the expected reaction rate.
And updating the interface of the micro-nano structure graph edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology for the semiconductor device.
Further, the determining the expected reaction rate for each surface profile site based on the location of the surface profile site and the target process parameter comprises:
and determining an ideal reaction rate according to the target process parameters.
And correcting the ideal reaction rate according to the position of the surface profile locus to obtain the expected reaction rate.
Further, the determining the ideal reaction rate according to the target process parameter includes:
All process parameters for processing the current film are obtained.
And screening target process parameters from all the process parameters according to the correlation degree of the process parameters and the reaction rate.
And determining an ideal reaction rate by utilizing the relation between the target process parameter and the reaction rate.
Further, the determining an ideal reaction rate using the relationship between the target process parameter and the reaction rate comprises:
And reading the data fitting relation between the target process parameters and the reaction rate.
And calculating the ideal reaction rate by using the data fitting relation.
Further, said modifying said ideal reaction rate in accordance with the location of said surface contour site comprises:
the visual window angle and the normal angle of the surface contour site are determined by the position of the surface contour site.
And correcting the ideal reaction rate according to the visual window angle and the normal angle.
Further, the determining the visual window angle and the normal angle of the surface contour site from the position of the surface contour site includes:
and respectively numbering each surface contour site in sequence according to the coordinates of the surface contour site.
Traversing each surface contour site in the order of the numbers, and calculating the visual window angle and the normal angle of each surface contour site.
Further, the extracting a plurality of surface contour sites from the substrate image includes:
And performing edge detection processing on the substrate image to obtain an edge detection curve of the micro-nano structure graph.
And carrying out at least one smoothing treatment on the edge detection curve to obtain a smooth continuous curve.
And selecting a plurality of surface profile sites on the smooth continuous curve by means of mean value dotting.
In order to achieve the technical purpose, the invention also provides a film morphology prediction device for the semiconductor device.
The film morphology prediction device may include, but is not limited to, a substrate image reading module, a contour site extraction module, a reaction rate determination module, a film thickness calculation module, and an edge interface updating module.
The substrate image reading module is used for reading the substrate image; the substrate image has a micro-nanostructure pattern thereon.
The contour locus extraction module is used for extracting a plurality of surface contour loci from the substrate image; the plurality of surface contour sites are all position points at the edge of the micro-nano structure pattern.
The reaction rate determination module is configured to determine an expected reaction rate for each surface contour site based on the location of the surface contour site and the target process parameter.
The film thickness calculation module is used for calculating the film thickness change of each surface profile site by using the preset process time and the expected reaction rate.
And the edge interface updating module is used for updating the interface of the micro-nano structure graphic edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology for the semiconductor device.
To achieve the above object, the present invention also provides a computer apparatus, including a memory and a processor, where the memory stores computer readable instructions that, when executed by the processor, cause the processor to perform the steps of the film morphology prediction method for a semiconductor device according to any of the embodiments of the present invention.
To achieve the above object, the present invention also provides a storage medium storing computer readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of the film morphology prediction method for a semiconductor device according to any one of the embodiments of the present invention.
The beneficial effects of the invention are as follows:
The invention can provide the film morphology prediction result for guiding the development and optimization of the film process design, and continuously optimizes the process conditions based on the invention, so that the film processing result meets the film process design expectation. Therefore, the invention can obtain the processing result before the actual processing of the thin film of the semiconductor device, is beneficial to avoiding the problem that the processed thin film does not meet the processing requirement of the device due to errors, faults and the like, and further can reduce the research and development cost of the semiconductor device and promote the research and development progress of the semiconductor device.
According to the method, the film growth or etching reaction rate is determined based on various process parameters, so that the accuracy of film morphology prediction is effectively improved, and the speed and accuracy of film morphology prediction can be considered through the optimized target process parameters; therefore, the technical scheme of the invention is beneficial to reducing the execution time of the film morphology prediction scheme, reduces the calculated amount and the calculated time in the film morphology prediction process, and further reduces the requirement on the hardware configuration of computer equipment.
The invention can express the relation and trend between various process parameters and reaction rates through a functional formula after data fitting, and can optimize the accuracy of film morphology coverage by adjusting related parameters or coefficients, so that the technical scheme provided by the invention is more suitable for the requirements of actual process production.
Drawings
FIG. 1 is a flow diagram illustrating a method of predicting film morphology for a semiconductor device in accordance with one or more embodiments of the present invention.
FIG. 2 illustrates a flow diagram of a method for predicting film morphology in one or more embodiments of the invention, particularly for a plasma vapor deposition process.
Fig. 3 shows a schematic diagram of the visible window angles (including theta 1 and theta 2) and normal angles (theta 0) of surface profile sites on a micro-nanostructure pattern in accordance with one or more embodiments of the invention.
Detailed Description
The method and the device for predicting the morphology of the thin film for the semiconductor device provided by the invention are explained and illustrated in detail below with reference to the attached drawings.
As shown in fig. 1, one or more embodiments of the present invention can provide a thin film topography prediction method for a semiconductor device, which can be used to assist in designing a thin film deposition process or a thin film etching process. Specifically, the film morphology prediction method includes, but is not limited to, at least one of the following steps.
First, a substrate image is read, the substrate image having thereon a micro-nanostructure pattern. The substrate image in one or more embodiments of the present invention is, for example, a scanning electron microscope (SEM, scanning Electron Microscope) image of a substrate structure after a precursor process, and the present invention can also customize the related parameters of micro-nano structure patterns in the image according to the thin film process design requirements, wherein the related parameters include, for example, but not limited to, the structure parameters such as the depth of the unit pattern, the width of the unit pattern, and the spacing between the dense patterns. The micro-nano structure pattern of the present embodiment may be a step, a trench, or a more complex single or periodic pattern, such as the one illustrated in fig. 3. The micro-nano structure pattern in this embodiment may have a minimum size of several nanometers and a maximum size of several tens of micrometers, but is not limited thereto.
It can be understood that the micro-nano structure pattern in the invention includes, but is not limited to, micro-nano structure patterns in images in a certain process or step in the manufacturing process of semiconductor devices such as integrated circuit microelectronic devices, optoelectronic devices, micro-electromechanical system devices and the like, and the application range of the invention is wider.
And secondly, extracting a plurality of surface contour sites from the substrate image, wherein the plurality of surface contour sites are all position points positioned at the edge of the micro-nano structure pattern. In the surface profile locus extraction process, the present invention can determine positional information of loci, number information of loci, and the like, as described in detail below.
The extraction of a plurality of surface contour sites from a substrate image in an embodiment of the present invention includes the following process. Edge detection processing is performed on the substrate image, and in this embodiment, edge detection is performed by using a canny (canny) edge detection method, a first-order differential operator method, a second-order differential operator method, or the like, so as to obtain an edge detection curve of the micro-nano structure graph; then carrying out at least one smoothing treatment on the edge detection curve to obtain a smooth continuous curve; and sequentially selecting a plurality of surface profile loci on the smooth continuous curve in a mean value point-taking mode, and determining locus coordinate information in the selecting process so as to form locus coordinate matrixes [ X, Y ].
Again, the present invention determines the expected reaction rate for each surface profile site based on the location of the surface profile site and the target process parameters, wherein the expected reaction rate is either a deposition reaction rate or an etch reaction rate. In the case of using the present invention for optimization of a thin film deposition process, the expected reaction rate is specifically a deposition reaction rate; under the optimized condition of the film etching process, the expected reaction rate is specifically the etching reaction rate. The target process parameters in the embodiment of the invention may include, but are not limited to, at least one of a reaction temperature (T), a pressure (P), a gas type, a reaction gas Flow rate (Flow), a reaction gas Flow ratio (Flow ratio), a radio frequency power (W), etc., taking silicon nitride or oxide deposited in the integrated circuit manufacturing process as an example, the reaction gas in the embodiment includes, but is not limited to, silane (SiH 4), ammonia (NH 3), nitrogen (N 2), argon (Ar), nitrous oxide (N 2 O), hydrogen (H 2), etc.
Wherein, the invention determines the expected reaction rate of each surface contour site according to the position of the surface contour site and the target process parameter comprises the following steps: and determining an ideal reaction rate according to the target process parameters, and correcting the ideal reaction rate according to the position of the surface profile locus to obtain an expected reaction rate.
As shown in fig. 2, the present invention determines an ideal reaction rate based on target process parameters comprising: obtaining all process parameters for processing the current film, and screening target process parameters from all process parameters according to the correlation degree of the process parameters and the reaction rate, wherein the screening mode can be at least one of main effect factor analysis, single factor analysis and correlation significance analysis; the target process parameter obtained is the process parameter which is most sensitive to the reaction rate, and then the invention utilizes the relation between the target process parameter and the reaction rate to determine the ideal reaction rate.
Optionally, determining the ideal reaction rate using the relationship between the target process parameter and the reaction rate comprises: and reading a data fitting relation between the target process parameters and the reaction rates, calculating an ideal reaction rate by using the data fitting relation, and forming an ideal reaction rate matrix of all edge contour sites. This example exemplifies plasma deposited silicon nitride (SiN x) and enables determination of an ideal reaction rate dep_rate by a data fit relationship of target process parameters and reaction rates as follows.
Dep_rate＝a1*f1(P)+a2*f2(W)+...+an-1*fn-1(T)+an
Wherein P represents pressure, W represents radio frequency power, and T represents reaction temperature; the n correlation coefficients a 1、a2……an can be obtained by a curve fitting method based on the related known process parameter data and the known reaction rate data.
The curve fitting method may be, for example, polynomial fitting, linear fitting, special function fitting, least square fitting, etc., and will not be described in detail in this embodiment.
It can be seen that the invention establishes a great deal of relation between the technological parameter data and the reaction rate, and can obtain the relation and trend between the macroscopic technological parameter and the deposition reaction rate or the etching reaction rate. Therefore, the technical scheme of the invention can better guide the process optimization of film deposition or film etching.
As shown in fig. 3, and in conjunction with fig. 2, modifying the ideal reaction rate based on the location of the surface contour sites may include: and determining the visual window angle and the normal angle of the surface contour site through the position of the surface contour site, and correcting the ideal reaction rate according to the visual window angle and the normal angle.
Optionally, determining the visual window angle and the normal angle of the surface contour site from the position of the surface contour site in the embodiment of the present invention includes: based on the site coordinate matrix [ X, Y ], the embodiment of the invention can respectively number each surface contour site in sequence according to the coordinates of the surface contour site, for example, the number is from 1 to N in ascending or descending order of the coordinates of X or Y, and N represents the number of sites; each surface contour site is traversed in the order of numbering and the visual window angle and normal angle (i.e., the site normal vector) for each surface contour site are calculated. Taking a thin film deposition process as an example, the angle of the visible window in the embodiment of the present invention includes angles θ 1 and θ 2 in the visible window where the deposited particles can reach at each site, and the normal angle is an angle θ 0 of the growth normal of each site, as shown in fig. 3.
Embodiments of the present invention may determine the expected reaction rate dep_rate i as follows.
Dep_ratei＝Dep_rate*(b0+b1*f1(θ)+b2*f2(θ)+b3*f3(θ)+…+bn*fn(θ))
Wherein, f n (theta) can represent a relation function of various physical or chemical reactions on the film morphology, b 0、b1、b2、……、bn represents a semi-empirical parameter for adjusting the film morphology, and the semi-empirical parameter can be obtained by solving after fitting calculation of actual morphology graph data; in this embodiment, θ=f (θ 0,θ1,θ2), that is, θ may be obtained through θ 0、θ1、θ2, and a specific calculation formula is determined according to the thin film process requirement, for example, θ=α 0θ0+α1θ1+α2θ2, where α 0、α1、α2 can represent a window shading coefficient, and specific values thereof are subject to achieving the technical purpose of the present invention and will not be described again.
Then, the embodiment of the invention calculates the film thickness variation of each surface profile site by using the preset process time and the expected reaction rate, namely, simulates the situation of film thickness increase (deposition process) or film thickness decrease (etching process) in the preset process time.
As shown in fig. 2, taking a film deposition process as an example, the growth profile evolution in unit time is performed in this step in the present invention, that is, the film thickness of each site corresponding to growth is calculated according to the growth rate, growth time and growth direction of each site in one unit deposition time, and then a continuous curve can be drawn according to the film thicknesses and growth directions of N sites, that is, the profile after growth in unit deposition time. The embodiment of the invention can simulate the film deposition result by means of a level set algorithm, a cellular automaton growth algorithm, a geometric line algorithm and the like. The thin film deposition process is specifically chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), or the like.
Finally, the interface of the micro-nano structure graph edge in the substrate image can be updated according to the film thickness change of each surface contour site, namely, the drawn continuous curve is used as the interface of the new edge of the micro-nano structure graph, so that the film morphology for the semiconductor device in unit time can be predicted. Wherein the preset process time comprises at least one unit time, the site acquisition step is returned on the basis of the updated micro-nano structure graph under the condition that the preset process time comprises a plurality of unit times, and re-executing the related steps until the accumulated process time reaches the preset process time to form a final simulated film growth profile, and outputting the image after updating the film growth profile.
One or more embodiments of the present invention can also provide a thin film profile prediction apparatus for a semiconductor device based on the same technical idea as a thin film profile prediction method for a semiconductor device. Film morphology prediction apparatus for semiconductor devices may include, but are not limited to, a substrate image reading module, a profile site extraction module, a reaction rate determination module, a film thickness calculation module, and an edge interface update module, as described in detail below.
The substrate image reading module is used for reading the substrate image. The substrate image is provided with a micro-nano structure pattern, and the micro-nano structure pattern can be a step, a groove or a more complex single or periodic pattern.
The contour locus extraction module is used for extracting a plurality of surface contour loci from the substrate image. The plurality of surface contour sites are all the position points at the edge of the micro-nano structure pattern. The contour locus extraction module can be specifically used for carrying out edge detection processing on the substrate image to obtain an edge detection curve of the micro-nano structure graph, carrying out at least one smoothing processing on the edge detection curve to obtain a smooth continuous curve, and selecting a plurality of surface contour loci on the smooth continuous curve in a mean value point taking mode.
The reaction rate determination module may be configured to determine an expected reaction rate for each surface profile site based on the location of the surface profile site and the target process parameter. The reaction rate determination module is specifically configured to determine an ideal reaction rate according to the target process parameter, and to correct the ideal reaction rate according to the position of the surface profile site, so as to obtain an expected reaction rate. More specifically, the reaction rate determination module is configured to obtain all process parameters for processing the current film, to screen a target process parameter from all process parameters based on a degree of correlation between the process parameter and the reaction rate, and to determine an ideal reaction rate using a relationship between the target process parameter and the reaction rate.
Alternatively, the reaction rate determination module can be configured to read a data fit relationship of the target process parameter to the reaction rate and to calculate the ideal reaction rate using the data fit relationship.
Alternatively, the reaction rate determination module may be configured to determine a visual window angle and a normal angle of the surface contour site from the position of the surface contour site, and to modify the ideal reaction rate as a function of the visual window angle and the normal angle. The reaction rate determining module is used for numbering each surface contour site in sequence according to the coordinates of the surface contour site, traversing each surface contour site according to the sequence of the numbering, and calculating the visible window angle and the normal angle of each surface contour site.
The film thickness calculation module is used for calculating the film thickness variation of each surface profile site by using the preset process time and the expected reaction rate.
And the edge interface updating module is used for updating the interface of the micro-nano structure graph edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology for the semiconductor device.
One or more embodiments of the present invention can also provide a computer apparatus including a memory and a processor, the memory having stored therein computer-readable instructions that, when executed by the processor, cause the processor to perform the steps of the film morphology prediction method for a semiconductor device of any of the embodiments of the present invention, based on the same technical concept as the film morphology prediction method for a semiconductor device. The film morphology prediction method comprises the following steps: first, a substrate image is read, the substrate image having thereon a micro-nanostructure pattern. And secondly, extracting a plurality of surface contour sites from the substrate image, wherein the plurality of surface contour sites are all position points positioned at the edge of the micro-nano structure pattern. Wherein extracting a plurality of surface contour sites from the substrate image comprises: performing edge detection processing on the substrate image to obtain an edge detection curve of the micro-nano structure graph; performing at least one smoothing treatment on the edge detection curve to obtain a smooth continuous curve; and selecting a plurality of surface profile sites on the smooth continuous curve by means of mean value dotting. Again, the expected reaction rate for each surface profile site is determined based on the location of the surface profile site and the target process parameters. Wherein determining the expected reaction rate for each surface contour site based on the location of the surface contour site and the target process parameter comprises: and determining an ideal reaction rate according to the target process parameters, and correcting the ideal reaction rate according to the positions of the surface profile sites to obtain an expected reaction rate. Wherein determining the ideal reaction rate based on the target process parameter comprises: acquiring all process parameters for processing the current film, and screening target process parameters from all process parameters according to the correlation degree of the process parameters and the reaction rate; the ideal reaction rate is determined using the relationship between the target process parameter and the reaction rate. Optionally, determining the ideal reaction rate using the relationship between the target process parameter and the reaction rate comprises: and reading a data fitting relation between the target process parameter and the reaction rate, and calculating the ideal reaction rate by using the data fitting relation. Optionally, modifying the ideal reaction rate based on the location of the surface profile sites comprises: and determining the visual window angle and the normal angle of the surface contour site through the position of the surface contour site, and correcting the ideal reaction rate according to the visual window angle and the normal angle. Wherein determining the visual window angle and the normal angle of the surface contour site from the position of the surface contour site comprises: and respectively numbering each surface contour site in sequence according to the coordinates of the surface contour site, traversing each surface contour site according to the sequence of the numbering, and calculating the visible window angle and the normal angle of each surface contour site. Then, the film thickness variation of each surface profile site was calculated using the preset process time and the expected reaction rate. And finally, updating the interface of the micro-nano structure graph edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology for the semiconductor device.
One or more embodiments of the present invention can also provide a storage medium storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of the thin film profile prediction method for a semiconductor device in any of the embodiments of the present invention, based on the same technical idea as the thin film profile prediction method for a semiconductor device. The film morphology prediction method comprises the following steps: first, a substrate image is read, the substrate image having thereon a micro-nanostructure pattern. And secondly, extracting a plurality of surface contour sites from the substrate image, wherein the plurality of surface contour sites are all position points positioned at the edge of the micro-nano structure pattern. Wherein extracting a plurality of surface contour sites from the substrate image comprises: performing edge detection processing on the substrate image to obtain an edge detection curve of the micro-nano structure graph; performing at least one smoothing treatment on the edge detection curve to obtain a smooth continuous curve; and selecting a plurality of surface profile sites on the smooth continuous curve by means of mean value dotting. Again, the expected reaction rate for each surface profile site is determined based on the location of the surface profile site and the target process parameters. Wherein determining the expected reaction rate for each surface contour site based on the location of the surface contour site and the target process parameter comprises: and determining an ideal reaction rate according to the target process parameters, and correcting the ideal reaction rate according to the positions of the surface profile sites to obtain an expected reaction rate. Wherein determining the ideal reaction rate based on the target process parameter comprises: acquiring all process parameters for processing the current film, and screening target process parameters from all process parameters according to the correlation degree of the process parameters and the reaction rate; the ideal reaction rate is determined using the relationship between the target process parameter and the reaction rate. Optionally, determining the ideal reaction rate using the relationship between the target process parameter and the reaction rate comprises: and reading a data fitting relation between the target process parameter and the reaction rate, and calculating the ideal reaction rate by using the data fitting relation. Optionally, modifying the ideal reaction rate based on the location of the surface profile sites comprises: and determining the visual window angle and the normal angle of the surface contour site through the position of the surface contour site, and correcting the ideal reaction rate according to the visual window angle and the normal angle. Wherein determining the visual window angle and the normal angle of the surface contour site from the position of the surface contour site comprises: and respectively numbering each surface contour site in sequence according to the coordinates of the surface contour site, traversing each surface contour site according to the sequence of the numbering, and calculating the visible window angle and the normal angle of each surface contour site. Then, the film thickness variation of each surface profile site was calculated using the preset process time and the expected reaction rate. And finally, updating the interface of the micro-nano structure graph edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology for the semiconductor device.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable storage medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection (electronic device) with one or more wires, a portable computer cartridge (magnetic device), a random access Memory (RAM, random Access Memory), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (EPROM, erasable Programmable Read-Only Memory, or flash Memory), an optical fiber device, and a portable compact disc Read-Only Memory (CDROM, compact Disc Read-Only Memory). In addition, the computer-readable storage medium may even be paper or other suitable medium upon which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable gate arrays (PGA, programmable GATE ARRAY), field Programmable gate arrays (FPGA, field Programmable GATE ARRAY), and the like.
In the description of the present specification, a description referring to the terms "present embodiment," "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
The above description is only of the preferred embodiments of the present invention, and is not intended to limit the invention, but any modifications, equivalents, and simple improvements made within the spirit of the present invention should be included in the scope of the present invention.
Claims (8)
1. A film morphology prediction method for a semiconductor device, comprising:
reading a substrate image, wherein the substrate image is provided with a micro-nano structure pattern;
Extracting a plurality of surface contour sites from the substrate image, wherein the plurality of surface contour sites are all position points positioned at the edge of the micro-nano structure graph;
Determining an ideal reaction rate according to the target process parameters; correcting the ideal reaction rate according to the position of the surface profile locus to obtain an expected reaction rate; the expected reaction rate is a deposition reaction rate or an etching reaction rate;
Wherein said determining an ideal reaction rate based on the target process parameter comprises: acquiring all process parameters for processing the current film; screening target process parameters from all the process parameters according to the correlation degree of the process parameters and the reaction rate; determining an ideal reaction rate by utilizing the relation between the target process parameter and the reaction rate; the ideal reaction rate is obtained by the formula (1), and the expected reaction rate is obtained by the formula (2);
Dep_rate＝a1*f1(P)+a2*f2(W)+...+an-1*fn-1(T)+an (1)
wherein, dep_rate is an ideal reaction rate, P represents pressure, W represents radio frequency power, and T represents reaction temperature; f 1、f2……fn-1 is a curve fitting function, and a 1、a2……an is a correlation coefficient obtained by a curve fitting method based on process parameter data and known reaction rate data;
Dep_ratei＝Dep_rate*(b0+b1*f1(θ)+b2*f2(θ)+b3*f3(θ)+…+bn*fn(θ)) (2)
Wherein, dep_ tate i is the expected reaction rate, dep_rate is the ideal reaction rate, f n (theta) represents the relation function of various physical or chemical reactions on the film morphology, b 0、b1、b2、……、bn represents the semi-empirical parameters for adjusting the film morphology, and theta represents the angle obtained according to the window shading effect coefficient, the visual window angle and the normal angle; calculating the thickness variation of the film at each surface contour site by using the preset process time and the expected reaction rate;
And updating the interface of the micro-nano structure graph edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology for the semiconductor device.
2. The method of claim 1, wherein determining an ideal reaction rate using the relationship between the target process parameter and the reaction rate comprises:
Reading the data fitting relation between the target technological parameter and the reaction rate;
and calculating the ideal reaction rate by using the data fitting relation.
3. The thin film topography prediction method for a semiconductor device according to any one of claims 1 to 2, wherein the modifying the ideal reaction rate according to the position of the surface profile site comprises:
Determining a visual window angle and a normal angle of the surface contour site through the position of the surface contour site;
And correcting the ideal reaction rate according to the visual window angle and the normal angle.
4. The thin film topography prediction method for a semiconductor device of claim 3, wherein the determining the visual window angle and the normal angle of the surface profile site from the position of the surface profile site comprises:
sequentially numbering each surface contour site according to the coordinates of the surface contour site;
Traversing each surface contour site in the order of the numbers, and calculating the visual window angle and the normal angle of each surface contour site.
5. The thin film topography prediction method for a semiconductor device of claim 1, wherein the extracting a plurality of surface profile sites from the substrate image comprises:
Performing edge detection processing on the substrate image to obtain an edge detection curve of the micro-nano structure graph;
Carrying out at least one smoothing treatment on the edge detection curve to obtain a smooth continuous curve;
and selecting a plurality of surface profile sites on the smooth continuous curve by means of mean value dotting.
6. A thin film topography prediction apparatus for a semiconductor device, comprising:
The substrate image reading module is used for reading a substrate image, and the substrate image is provided with a micro-nano structure pattern;
The contour locus extraction module is used for extracting a plurality of surface contour loci from the substrate image, wherein the plurality of surface contour loci are all position points positioned at the edge of the micro-nano structure graph;
The reaction rate determining module is used for determining an ideal reaction rate according to the target process parameters; correcting the ideal reaction rate according to the position of the surface profile locus to obtain an expected reaction rate; the expected reaction rate is a deposition reaction rate or an etching reaction rate; wherein said determining an ideal reaction rate based on the target process parameter comprises: acquiring all process parameters for processing the current film; screening target process parameters from all the process parameters according to the correlation degree of the process parameters and the reaction rate; determining an ideal reaction rate by utilizing the relation between the target process parameter and the reaction rate; the ideal reaction rate is obtained by the formula (1), and the expected reaction rate is obtained by the formula (2);
Dep_rate＝a1*f1(P)+a2*f2(W)+...+an-1(T)+an (1)
wherein, dep_rate is an ideal reaction rate, P represents pressure, W represents radio frequency power, and T represents reaction temperature; f 1、f2……fn-1 is a curve fitting function, and a 1、a2……an is a correlation coefficient obtained by a curve fitting method based on process parameter data and known reaction rate data;
Dep_ratei＝Dep_rate*(b0+b1*f1(θ)+b2*f2(θ)+b3*f3(θ)+…+bn*fn(θ)) (2)
Wherein, dep_rate i is the expected reaction rate, dep_rate is the ideal reaction rate, f n (θ) represents the relation function of various physical or chemical reactions affecting the film morphology, b 0、b1、b2、……、bn represents the semi-empirical parameters used for adjusting the film morphology, θ represents the angle obtained according to the window shading effect coefficient, the visual window angle and the normal angle;
The film thickness calculation module is used for calculating the film thickness change of each surface profile site by using the preset process time and the expected reaction rate;
and the edge interface updating module is used for updating the interface of the micro-nano structure graph edge in the substrate image according to the film thickness change of each surface contour site so as to predict the film morphology for the semiconductor device.
7. A computer device comprising a memory and a processor, the memory having stored therein computer readable instructions which, when executed by the processor, cause the processor to perform the steps of the film morphology prediction method for a semiconductor device of any one of claims 1 to 5.
8. A storage medium storing computer readable instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of the thin film topography prediction method for a semiconductor device as claimed in any one of claims 1 to 5.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06196405A (en) * | 1992-11-17 | 1994-07-15 | Ricoh Co Ltd | Estimation of shape of deposited thin film |
| CN102427046A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Electro-chemical deposition result determination method |
| CN105908151A (en) * | 2016-03-01 | 2016-08-31 | 江南大学 | Nano-film atomic layer deposition quantitative modeling method |
| CN107153718A (en) * | 2016-03-02 | 2017-09-12 | 中国科学院微电子研究所 | A kind of method and system of high-k/metal gate surface topography emulation |
| CN108154004A (en) * | 2017-12-26 | 2018-06-12 | 哈尔滨工业大学 | Based on transition zone to the buffer layer material selection method of epitaxial film and the evaluation of substrate binding force |
| CN109084721A (en) * | 2017-06-13 | 2018-12-25 | 睿励科学仪器（上海）有限公司 | Method and apparatus for determining the structural parameters of the object construction in semiconductor devices |
| CN112136135A (en) * | 2018-04-06 | 2020-12-25 | 朗姆研究公司 | Process simulation model correction using critical dimension scanning electron microscope |
| WO2021001109A1 (en) * | 2019-07-03 | 2021-01-07 | Asml Netherlands B.V. | Method for applying a deposition model in a semiconductor manufacturing process |
| CN113051863A (en) * | 2021-03-12 | 2021-06-29 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor modeling method, semiconductor modeling device, storage medium, and computer apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100809705B1 (en) * | 2006-09-26 | 2008-03-06 | 삼성전자주식회사 | Formation method of image contour for prediction of semiconductor device pattern |
| US8423917B2 (en) * | 2009-07-30 | 2013-04-16 | Synopsys, Inc. | Modeling thin-film stack topography effect on a photolithography process |
-
2021
- 2021-06-08 CN CN202110639484.4A patent/CN113471093B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06196405A (en) * | 1992-11-17 | 1994-07-15 | Ricoh Co Ltd | Estimation of shape of deposited thin film |
| CN102427046A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Electro-chemical deposition result determination method |
| CN105908151A (en) * | 2016-03-01 | 2016-08-31 | 江南大学 | Nano-film atomic layer deposition quantitative modeling method |
| CN107153718A (en) * | 2016-03-02 | 2017-09-12 | 中国科学院微电子研究所 | A kind of method and system of high-k/metal gate surface topography emulation |
| CN109084721A (en) * | 2017-06-13 | 2018-12-25 | 睿励科学仪器（上海）有限公司 | Method and apparatus for determining the structural parameters of the object construction in semiconductor devices |
| CN108154004A (en) * | 2017-12-26 | 2018-06-12 | 哈尔滨工业大学 | Based on transition zone to the buffer layer material selection method of epitaxial film and the evaluation of substrate binding force |
| CN112136135A (en) * | 2018-04-06 | 2020-12-25 | 朗姆研究公司 | Process simulation model correction using critical dimension scanning electron microscope |
| WO2021001109A1 (en) * | 2019-07-03 | 2021-01-07 | Asml Netherlands B.V. | Method for applying a deposition model in a semiconductor manufacturing process |
| CN113051863A (en) * | 2021-03-12 | 2021-06-29 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor modeling method, semiconductor modeling device, storage medium, and computer apparatus |
Non-Patent Citations (5)
| Title |
|---|
| Fast mask near-field calculation using fully convolution;Jiaxin Lin;2020 International Workshop on Advanced Patterning Solutions(IWAPS);全文 * |
| GaN MOCVD生长速率及表面形貌随生长参数的变化;符凯;张禹;陈敦军;韩平;谢自力;张荣;;稀有金属(第01期);全文 * |
| 基于Monte Carlo方法的PECVD模拟研究;丁文虎等;微纳电子与智能制造;全文 * |
| 相场法模拟GaAs衬底上InGaAs异质结表面形貌;王冠;翁燕华;吴平平;;材料导报(第S1期);全文 * |
| 针对更精确电迁移预测应用的热耦合模型建模;杨双等;微电子学;全文 * |
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