CN113467930B - Processing method and device for hardware management shared memory - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
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- G06F9/5022—Mechanisms to release resources
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
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Abstract
The application discloses a processing method of a shared memory. And dividing the shared memory into a plurality of memory blocks according to the fixed block size. The memory allocation controller provides a dedicated register for each processor or for different modules of the same processor, and the memory allocation controller implements mutual exclusion between the registers. When a processor needs to use the shared memory, the processor reads a corresponding special register in the memory allocation controller, the register returns the starting address information of an available memory block, and the processor is allocated with the available memory block. When a certain data packet is used by the processor and needs to be released, the data packet needing to be released is delivered to the memory release controller to release the data packet uniformly; the memory release controller decrements the ref-cnt value for that memory block by 1. When the ref-cnt value of a memory block is reduced to 0, the memory release controller releases the memory block. The method and the device solve the problem that a plurality of processors compete with each other when using the shared memory.
Description
Technical Field
The application relates to a processing method for managing a shared memory by hardware.
Background
In smart devices such as mobile phones, a plurality of processors such as a CP (communication processor), an AP (application processor), a DSP (digital signal processor), a Wi-Fi control unit, and the like are generally present. In the application, a scenario that a data packet received by one processor is handed to another processor for processing exists, for example, a data packet received by a CP is handed to an AP for processing, or forwarded to other devices for processing through Wi-Fi, which involves the problem of shared memory usage and release. For example, an application plays a video through mobile phone traffic, and in the downlink direction, the CP allocates a memory space to receive video content of the other party from the mobile communication network. And after the receiving is finished, the CP delivers the memory space to the AP for playing. And after the playing is finished, the AP directly or indirectly releases the memory space. In the uplink direction, the AP allocates a memory space to receive the video content of the local camera and sends the video content to the CP. And then the CP transmits the data to the opposite terminal through the mobile communication network for display, and directly or indirectly releases the memory space after the CP finishes transmitting the data. In the exemplary usage scenario, there are multiple users CP and AP in the memory, and when allocating and releasing the memory, a method needs to be adopted to manage the memory, so as to avoid multiple parties competing to use the memory space in the same block, or one party accidentally destroying the memory space being used by other users. The general method adopts software locks among various processors or hardware interlocking mechanisms provided by the processors and hardware to avoid competition, thereby achieving the purposes of meeting the use requirements of various parties on the memory and properly managing the memory.
However, in the current 5G and high-rate network applications, the transmission rate of the data packets is very fast, the requirement on the processing time of each data packet is very short, and the above-mentioned mechanism of using software and hardware to achieve mutual exclusion lock brings very large delay to the processing of the data packets, occupies very much CPU resources, and limits the throughput rate of the data packets; or processors requiring higher processing power to operate, increasing system power consumption and cost.
Disclosure of Invention
The technical problem to be solved by the present application is to provide a processing method for hardware management shared memory, which does not use a mutual exclusion lock mechanism, thereby not bringing about a large delay and not occupying too much CPU resources. The hardware includes a memory allocation controller and a memory release controller.
In order to solve the above technical problem, the present application provides a processing method for managing a shared memory by hardware, which includes the following steps. Step S1: dividing the shared memory into a plurality of memory blocks according to a fixed block size; recording the number of the data packets actually stored in each memory block as ref-cnt; the memory block with ref-cnt value of 0 is an available memory block; the memory allocation controller provides available memory block information to each processor; the memory allocation controller provides a special register for each processor or different modules of the same processor, and mutual exclusion among the registers is realized by the memory allocation controller. Step S2: when a processor needs to use a shared memory, the processor reads a corresponding special register in the memory allocation controller, the register returns the initial address information of an available memory block, and the processor is allocated with the available memory block; the processor records the address of each allocated block of memory, as well as the ref-cnt value for each allocated block of memory. And step S3: when the processor finishes using a certain data packet and needs to release the data packet, the processor delivers the data packet needing to be released to the memory release controller to uniformly release the data packet; the memory release controller calculates the memory block to which the memory release controller belongs according to the starting address of the data packet to be released, and subtracts 1 from the ref-cnt value of the memory block. And step S4: when the ref-cnt value of a memory block is reduced to 0, the memory release controller releases the memory block.
Further, in step S1, the following are stored in the memory or in the internal cache of the memory release controller: the starting address and size of the shared memory, and the size of the memory block.
Further, in the step S1, the start addresses of all available memory blocks are recorded in the available memory block table. In step S2, the memory allocation controller deletes the allocated memory block from the available memory block table. In step S4, the memory release controller writes the start address of the released memory block into the available memory block table.
Further, the ref-cnt value for each memory block is stored in memory or in an internal cache of the memory release controller.
Further, in step S3, when the processor releases the data packet, the processor informs the memory release controller of the start address information of the data packet, and the memory release controller completes releasing the memory block occupied by the data packet.
Further, a third table is set in the memory or an internal cache of the memory release controller, and the third table is used for storing the initial address of the data packet to be released, which is filled in by the processor; or table three is used to store: a pointer pointing to the initial address of the data packet to be released and the number of the data packets to be released; and the memory release controller determines the data packets to be released, reads the contents corresponding to the data packets to be released in the table III into the internal cache for processing, and releases the memory blocks occupied by the data packets to be released.
Further, each processor corresponds to one table three, or a plurality of processors share one table three.
Further, storing in an internal cache of the memory release controller: the address of the block of memory to be released, the ref-cnt value of the block of memory to be released.
Further, the memory release controller outputs abnormal information which is stored in the memory or an internal cache of the memory release controller; each processor is responsible for processing the abnormal information output by the memory release controller.
The application also provides a processing device for sharing the memory, which comprises a configuration unit, a memory allocation unit, a data packet release unit and a memory release unit. The configuration unit is used for dividing the shared memory into a plurality of memory blocks according to a fixed block size; recording the number of the data packets actually stored in each memory block as ref-cnt; the memory block with ref-cnt value of 0 is an available memory block; the memory allocation controller provides the available memory block information to each processor; the memory allocation controller provides a special register for each processor or different modules of the same processor, and mutual exclusion among the registers is realized by the memory allocation controller. The memory allocation unit is used for reading a corresponding special register in the memory allocation controller when the processor needs to use the shared memory, the register returns the starting address information of an available memory block, and the processor is allocated with the available memory block; the address of each memory block allocated is also recorded, as well as the ref-cnt value for each memory block allocated. The data packet release unit is used for giving the data packet to be released to the memory release controller by the processor for releasing the data packet uniformly when the processor uses a certain data packet and needs to release the data packet; the memory release controller calculates the memory block to which the memory release controller belongs according to the starting address of the data packet, and subtracts 1 from the ref-cnt value of the memory block. The memory release unit is used to release a memory block when the ref-cnt value of the memory block is reduced to 0.
The method and the device have the technical effect of solving the problem of mutual competition when the shared memory is allocated and released by the processors.
Drawings
Fig. 1 is a flowchart illustrating a processing method for managing a shared memory by hardware according to the present application.
Fig. 2 is a schematic structural diagram of a processing device for managing a shared memory by hardware according to the present disclosure.
The reference numbers in the figures illustrate: configuration unit 1, memory allocation unit 2, packet release unit 3, and memory release unit 4.
Detailed Description
Referring to fig. 1, a processing method for managing a shared memory by hardware according to the present disclosure includes the following steps.
Step S1: the shared memory is divided into a plurality of memory blocks (blocks) according to a fixed block size (block size). The number of packets actually stored in each block is denoted as ref-cnt. The memory block with ref-cnt value 0 is the available memory block. Information for all available memory blocks is initially configured by software into the memory allocation controller. The memory allocation controller maintains information of the available memory blocks and provides the available memory block information to the processors. The memory allocation controller provides a special register for each processor or different modules of the same processor, and mutual exclusion among the registers is realized by the memory allocation controller, so that the software is prevented from needing interlocking operation.
Step S2: when a processor needs to use the shared memory, the processor reads a corresponding special register in the memory allocation controller, the register returns the starting address information of an available memory block, and the processor is allocated with the available memory block. The processor records the address of each allocated block of memory, as well as the ref-cnt value for each allocated block of memory.
And step S3: when the processor finishes using a certain data packet and needs to release the data packet, the processor delivers the data packet needing to be released to the memory release controller to release the data packet uniformly. The memory release controller calculates the memory block to which the memory release controller belongs according to the starting address of the data packet to be released, and subtracts 1 from the ref-cnt value of the memory block.
And step S4: the memory release controller releases a memory block only when its ref-cnt value decreases to 0.
Preferably, in the step S1, a start address and a size of the shared memory and a size of the memory block (for example, 2KB, 4KB, 16KB, etc.) are stored in the memory or in an internal cache of the memory release controller.
Preferably, in step S1, the start addresses of all the available memory blocks are recorded in the available memory block table. In step S2, the memory allocation controller deletes the allocated memory block from the available memory block table. In step S4, the memory release controller rewrites the start address of the released memory block into the available memory block table. The available memory block table is used for assisting in completing the memory allocation and memory release processes required by the system.
Preferably, the read pointer when the available memory block table is initialized is a header. In step S2, when the processor applies for the available memory block, the memory allocation controller obtains one available memory block from the position of the read pointer and hands the available memory block to the processor, and then the read pointer moves forward. If the read pointer is equal to the write pointer, then an error is made indicating that there is currently no available memory block. In step S4, when the memory release controller releases one available memory block, the available memory block is filled in the position corresponding to the write pointer of the available memory block table, and then the write pointer moves forward. If the write pointer equals or exceeds the read pointer, an error is made indicating that the available memory block information is over-flown.
Preferably, the number ref-cnt of packets actually stored in each memory block is stored in the memory or in an internal cache of the memory release controller. The ref-cnt value is filled in by each processor after the memory block has been used.
Preferably, in step S3, when the processor releases the data packet, the processor informs the memory release controller of the start address information of the data packet, and the memory release controller completes the action of releasing the memory block occupied by the data packet.
Preferably, a third table is set in the memory or in an internal cache of the memory release controller, and the third table is used for storing the starting address of the data packet to be released, which is filled by the processor. Or table three is used to store: a pointer pointing to the initial address of the data packet to be released and the number of the data packets to be released. Each processor corresponds to a table three (preferably, it can avoid that each processor needs to be locked to achieve the purpose of mutual exclusion), or a plurality of processors share a table three. And the memory release controller determines the number of the data packets to be released, reads the content corresponding to the data packets to be released in the table III into the internal cache of the memory release controller for processing, and releases the memory blocks occupied by the data packets to be released.
Preferably, the internal cache of the memory release controller stores: the address of the memory block to be released, the value of the memory block ref-cnt to be released. This is to avoid the memory release controller from frequently reading the memory, and to reduce latency.
Preferably, the memory release controller output exception information is stored in the memory or in an internal cache of the memory release controller, and is used for indicating the exception information in the processing process of the memory release controller. Preferably, each processor is responsible for processing exception information in the memory release controller processing process.
Referring to fig. 2, the processing apparatus for hardware management of a shared memory provided in the present application includes a configuration unit 1, a memory allocation unit 2, a packet release unit 3, and a memory release unit 4. The apparatus shown in fig. 2 corresponds to the method shown in fig. 1.
The configuration unit 1 is configured to divide the shared memory into a plurality of memory blocks according to a fixed block size. The number of packets actually stored in each block is denoted as ref-cnt. The memory block with ref-cnt value 0 is the available memory block. The memory allocation provides information on the available memory blocks to each processor. The memory allocation controller provides a special register for each processor or different modules of the same processor, and mutual exclusion among the registers is realized by the memory allocation controller.
The memory allocation unit 2 is configured to, when the processor needs to use the shared memory, read a corresponding dedicated register in the memory allocation controller, where the register returns start address information of an available memory block, and the processor is allocated an available memory block accordingly. The memory allocation unit 2 also records the address of each allocated memory block, and the ref-cnt value of each allocated memory block.
The data packet releasing unit 3 is used for, when the processor finishes using a certain data packet and needs to release the data packet, the processor gives the data packet needing to be released to the memory release controller for releasing the data packet in a unified manner. The memory release controller calculates the memory block to which the memory release controller belongs according to the starting address of the data packet to be released, and subtracts 1 from the ref-cnt value of the memory block.
The memory release unit 4 is used to release a memory block only when its ref-cnt value is reduced to 0.
The present application has the following advantageous technical effects. First, the problem of mutual competition when a plurality of processors allocate and release the shared memory is solved, and the problems of high delay, low processing speed and high processor utilization rate caused by the scheme of adding the mutual exclusion lock are avoided. Second, the memory is released by the hardware of the memory release controller, which reduces the utilization rate of each processor. Thirdly, the method is simple, flexible and convenient to expand.
The above are merely preferred embodiments of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art to which the present application pertains. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A processing method of hardware management shared memory is characterized by comprising the following steps;
step S1: dividing the shared memory into a plurality of memory blocks according to a fixed block size; recording the number of data packets actually stored in each memory block as ref-cnt; the memory blocks with ref-cnt values of 0 are available memory blocks; the memory allocation controller provides available memory block information to each processor; the memory allocation controller provides a special register for each processor or different modules of the same processor, and mutual exclusion among the registers is realized by the memory allocation controller;
step S2: when a processor needs to use a shared memory, the processor reads a corresponding special register in the memory allocation controller, the register returns the starting address information of an available memory block, and the processor is allocated with the available memory block; the processor records the address of each allocated memory block and the ref-cnt value of each allocated memory block;
and step S3: when the processor finishes using a certain data packet and needs to release the data packet, the processor gives the data packet needing to be released to the memory release controller to release the data packet uniformly; the memory release controller calculates the memory block to which the memory release controller belongs according to the initial address of the data packet to be released, and subtracts 1 from the ref-cnt value of the memory block;
and step S4: when the ref-cnt value of a memory block is reduced to 0, the memory release controller releases the memory block.
2. The method as claimed in claim 1, wherein in step S1, the following are stored in the memory or the internal cache of the memory release controller: the starting address and size of the shared memory, and the size of the memory block.
3. The method as claimed in claim 1, wherein in step S1, the starting addresses of all the available memory blocks are recorded in an available memory block table;
in step S2, the memory allocation controller deletes the allocated memory block from the available memory block table;
in step S4, the memory release controller writes the start address of the released memory block into the available memory block table.
4. The method of claim 1, wherein the ref-cnt value for each memory block is stored in memory or in an internal cache of the memory release controller.
5. The method as claimed in claim 1, wherein in step S3, when the processor releases the data packet, the processor informs the memory release controller of the start address information of the data packet, and the memory release controller completes the release of the data packet.
6. The method as claimed in claim 5, wherein a third table is set in the memory or in the internal buffer of the memory release controller, the third table is used to store the initial address of the data packet to be released filled in by the processor; or table three is used to store: a pointer pointing to the initial address of the data packet needing to be released and the number of the data packets needing to be released; and the memory release controller determines the data packets to be released, reads the contents corresponding to the data packets to be released in the table III into the internal cache for processing, and releases the memory blocks occupied by the data packets to be released.
7. The method as claimed in claim 6, wherein each processor corresponds to a table three, or a plurality of processors share a table three.
8. The method according to claim 1, wherein the internal cache of the memory release controller stores: the address of the memory block to be released, the ref-cnt value of the memory block to be released.
9. The method according to claim 1, wherein the memory release controller outputs the exception information to the memory or to an internal cache of the memory release controller; each processor is responsible for processing the abnormal information output by the memory release controller.
10. A processing device for hardware management shared memory is characterized by comprising a configuration unit, a memory allocation unit, a data packet release unit and a memory release unit;
the configuration unit is used for dividing the shared memory into a plurality of memory blocks according to a fixed block size; recording the number of the data packets actually stored in each memory block as ref-cnt; the memory blocks with ref-cnt values of 0 are available memory blocks; the memory allocation controller provides available memory block information to each processor; the memory allocation controller provides a special register for each processor or different modules of the same processor, and mutual exclusion among the registers is realized by the memory allocation controller;
the memory allocation unit is used for reading a corresponding special register in the memory allocation controller when the processor needs to use the shared memory, the register returns the starting address information of an available memory block, and the processor is allocated with the available memory block; the processor also records the address of each memory block allocated and the ref-cnt value of each memory block allocated;
the data packet release unit is used for giving the data packet to be released to the memory release controller by the processor for releasing the data packet uniformly when the processor uses a certain data packet and needs to release the data packet; the memory release controller calculates the memory block to which the memory release controller belongs according to the initial address of the data packet, and subtracts 1 from the ref-cnt value of the memory block;
the memory releasing unit is used to release a memory block when the ref-cnt value of the memory block is reduced to 0.
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