CN113466758A - Cascade type low-offset vertical Hall sensor system - Google Patents
Cascade type low-offset vertical Hall sensor system Download PDFInfo
- Publication number
- CN113466758A CN113466758A CN202110828998.4A CN202110828998A CN113466758A CN 113466758 A CN113466758 A CN 113466758A CN 202110828998 A CN202110828998 A CN 202110828998A CN 113466758 A CN113466758 A CN 113466758A
- Authority
- CN
- China
- Prior art keywords
- hall
- group
- unit
- cascaded
- cascade
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 238000001514 detection method Methods 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 abstract description 30
- 230000035945 sensitivity Effects 0.000 abstract description 11
- 238000013461 design Methods 0.000 abstract description 5
- 238000004088 simulation Methods 0.000 abstract description 4
- 238000005253 cladding Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
- G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
- G01R33/07—Hall effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N52/00—Hall-effect devices
Abstract
The invention relates to a cascade low-offset vertical Hall sensor system which comprises four cascade Hall units, wherein the four cascade Hall units have completely consistent structures, the four cascade Hall units are connected together in pairs through contact hole lead wires to form a four-electrode vertical Hall sensor with a completely symmetrical structure, one pair of cascade Hall units are used as voltage or current input electrode pairs, and the other pair of cascade Hall units are used as Hall voltage or Hall current detection electrodes. The cascade low-offset vertical Hall sensor system has symmetrical structure and relatively small offset voltage. The invention can effectively utilize the advantages of the rotating current method to reduce the offset voltage to be less than one tenth of the offset voltage of the traditional five-electrode vertical Hall. The invention adopts the P-type covering layer and the P-type isolating ring, and improves the sensitivity and the noise isolation characteristic of the device through reasonable design and simulation of the size of the device.
Description
Technical Field
The invention relates to the field of sensors, in particular to the field of Hall sensors, and specifically relates to a cascade low-offset vertical Hall sensor system.
Background
The current in the material can be deflected from the original direction under the action of Lorentz force under the action of the magnetic field, so that the Hall effect is formed. Generally, a hall sensor will provide four electrodes, two of which are used to apply a voltage or current and the other pair is used to detect a hall voltage or a hall current. With the development of semiconductors and integrated circuits, CMOS, BCD process based hall sensors are the most widely used solution due to their low cost and ease of integration with application specific signal processing circuits (ASICs). The horizontal Hall sensor for detecting the vertical magnetic field has the advantages of simple structure, high sensitivity and easy realization, is widely applied to the detection of position, speed, angle, current and the like, and realizes intellectualization, automatic control and the like through the non-contact magnetic field induction. The horizontal hall sensor is developed to the present, and different structural shapes including a square shape, a rectangular shape and a cross shape are generated according to different process conditions.
But the horizontal hall sensor can only detect a magnetic field perpendicular to the chip surface. In many applications, because of the magnetic field direction and the convenience of installation, the magnetic field parallel to the chip surface needs to be detected, and only a vertical hall sensor is required to be designed in the CMOS and BCD processes to detect the horizontal magnetic field. However, the vertical hall sensor has poor symmetry, large offset voltage and low sensitivity, and thus cannot be popularized in the conventional standard CMOS or BCD process. Research thereon is also ongoing. Including the use of five electrodes as the initial structure of a vertical hall sensor, followed by the appearance of structures such as three, four, six, or even seven electrodes. The five electrodes are relatively symmetrical in shape structure, the original offset voltage is relatively small, but the offset voltage cannot be completely eliminated by the traditional four-phase rotating current method because the current paths are inconsistent, and although the four-electrode structure can be matched with the four-phase current rotating method of the horizontal Hall to eliminate the offset voltage, the four-electrode structure has larger offset voltage in structure. Six electrodes have the same problems as four electrodes. The seven-electrode structure developed from the five-electrode structure also has the same problems as the five-electrode structure.
Disclosure of Invention
It is an object of the present invention to overcome the above-mentioned drawbacks of the prior art and to provide a low-offset vertical hall sensor system of the cascaded type that satisfies the requirements of high sensitivity, low noise and low offset.
In order to achieve the above object, the cascade type low offset vertical hall sensor system of the present invention is as follows:
the cascade low-offset vertical Hall sensor system is mainly characterized by comprising four cascade Hall units, wherein the four cascade Hall units have completely consistent structures, the four cascade Hall units are connected together in pairs through contact hole lead wires to form a four-electrode vertical Hall sensor with a completely symmetrical structure, one pair of cascade Hall units are used as voltage or current input electrode pairs, and the other pair of cascade Hall units are used as Hall voltage or Hall current detection electrodes.
Preferably, the cascaded hall cell is a three-electrode vertical hall cell, and comprises a P-type substrate, an N-well active region, a P-type cover layer, a contact hole of the N-well active region, a P-type injection contact hole and a P-type isolation ring, wherein the N-well active region is formed by performing N-type injection on the P-type substrate, the contact hole of the N-well active region is used as an electrode of the cascaded hall cell, the P-type cover layer is formed by the P-type injection contact hole, the P-type isolation ring is formed by the P-type injection contact hole surrounding the N-well active region, and the P-type isolation ring and the P-type cover layer are both connected to a ground potential through the contact hole.
Preferably, the interconnection of the four cascaded hall units maintains equal interconnection impedance, and the current distribution path and the well resistance are symmetrical in condition.
Preferably, the device further comprises two groups of four cascaded hall units, namely a first group of cascaded hall units and a second group of cascaded hall units, wherein each group of hall units are sequentially connected, the first hall unit of the first group is connected with the third hall unit of the second group, the second hall unit of the first group is connected with the fourth hall unit of the second group, the third hall unit of the first group is connected with the first hall unit of the second group, and the fourth hall unit of the first group is connected with the second hall unit of the second group.
Preferably, the device further comprises four groups of four cascaded hall units, namely a first group of cascaded hall units, a second group of cascaded hall units, a third group of cascaded hall units and a fourth group of cascaded hall units, wherein each group of hall units are connected in sequence, and the first hall unit of each group of hall units is connected with the fourth hall unit of each group of hall units; the first Hall unit of the first group is connected with the fourth Hall unit of the second group, the first Hall unit of the second group is connected with the fourth Hall unit of the third group, and the first Hall unit of the third group is connected with the fourth Hall unit of the fourth group; the second Hall unit of the first group is connected with the first Hall unit of the second group, the third Hall unit of the first group is connected with the second Hall unit of the second group and the first Hall unit of the third group, the fourth Hall unit of the first group is connected with the third Hall unit of the second group, the second Hall unit of the third group and the first Hall unit of the fourth group, the fourth Hall unit of the second group is connected with the third Hall unit of the third group and the second Hall unit of the fourth group, and the fourth Hall unit of the third group is connected with the third Hall unit of the fourth group.
The cascade low-offset vertical Hall sensor system has symmetrical structure and relatively small offset voltage. The invention can adopt a four-phase rotating current method as the traditional horizontal Hall method to eliminate the offset of the device, the current path and the resistance of each phase are relatively matched and equivalent, and the advantage of the rotating current method can be effectively utilized to reduce the offset voltage to be less than one tenth of the offset voltage of the traditional five-electrode vertical Hall. The invention adopts the P-type covering layer and the P-type isolating ring, and improves the sensitivity and the noise isolation characteristic of the device through reasonable design and simulation of the size of the device.
Drawings
Fig. 1 is an overhead view of a four-level low offset vertical hall sensor structure of the cascaded low offset vertical hall sensor system of the present invention.
Fig. 2 is a cross-sectional view of a four-level low offset vertical hall sensor structure of the cascaded low offset vertical hall sensor system of the present invention.
Fig. 3 is a schematic diagram of the application of the four-phase rotating current method of the cascade-type low-offset vertical hall sensor system of the present invention to the horizontal hall.
Fig. 4 is a cross-sectional view of a five-electrode vertical hall structure of the prior art.
Fig. 5 is a schematic structural diagram of two groups of four-level and parallel hall units of the cascade type low-offset vertical hall sensor system of the invention.
Fig. 6 is a schematic structural diagram of four completely symmetrical groups of four cascaded parallel hall units of the cascaded low-offset vertical hall sensor system of the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The cascade type low-offset vertical Hall sensor system comprises four cascade Hall units, wherein the four cascade Hall units have completely consistent structures, the four cascade Hall units are connected together in pairs through contact hole lead wires to form a four-electrode vertical Hall sensor with a completely symmetrical structure, one pair of cascade Hall units are used as voltage or current input electrode pairs, and the other pair of cascade Hall units are used as Hall voltage or Hall current detection electrodes.
As a preferred embodiment of the present invention, the cascaded hall cell is a three-electrode vertical hall cell, and includes a P-type substrate, an N-well active region, a P-type cladding layer, a contact hole of the N-well active region, a P-type injection contact hole, and a P-type isolation ring, wherein the N-well active region is formed by performing N-type injection on the P-type substrate, the contact hole of the N-well active region serves as an electrode of the cascaded hall cell, the P-type cladding layer is formed by the P-type injection contact hole, the P-type isolation ring is formed by the P-type injection contact hole surrounding the N-well active region, and the P-type isolation ring and the P-type cladding layer are both connected to a ground potential through the contact hole.
As a preferred embodiment of the invention, the interconnection of the four cascaded Hall units keeps equal interconnection impedance, and the current distribution path and the trap resistance are symmetrical.
As a preferred embodiment of the present invention, the apparatus further includes two sets of four cascaded hall units, which are a first set of cascaded hall units and a second set of cascaded hall units, respectively, each set of hall units are sequentially connected, a first hall unit of the first set is connected to a third hall unit of the second set, a second hall unit of the first set is connected to a fourth hall unit of the second set, the third hall unit of the first set is connected to a first hall unit of the second set, and the fourth hall unit of the first set is connected to a second hall unit of the second set.
As a preferred embodiment of the present invention, the apparatus further includes four sets of four cascaded hall units, which are a first set of cascaded hall units, a second set of cascaded hall units, a third set of cascaded hall units, and a fourth set of cascaded hall units, respectively, wherein each set of hall units are connected in sequence, and a first hall unit of each set of hall units is connected to a fourth hall unit of each set of hall units; the first Hall unit of the first group is connected with the fourth Hall unit of the second group, the first Hall unit of the second group is connected with the fourth Hall unit of the third group, and the first Hall unit of the third group is connected with the fourth Hall unit of the fourth group; the second Hall unit of the first group is connected with the first Hall unit of the second group, the third Hall unit of the first group is connected with the second Hall unit of the second group and the first Hall unit of the third group, the fourth Hall unit of the first group is connected with the third Hall unit of the second group, the second Hall unit of the third group and the first Hall unit of the fourth group, the fourth Hall unit of the second group is connected with the third Hall unit of the third group and the second Hall unit of the fourth group, and the fourth Hall unit of the third group is connected with the third Hall unit of the fourth group.
In the specific implementation mode of the invention, the design of the cascade low-offset vertical Hall sensor is disclosed, the sensor can be compatible with standard CMOS and BCD processes, higher sensitivity can be obtained, and a four-phase rotating current method circuit like a horizontal Hall circuit can be adopted, so that the offset voltage is greatly reduced.
The vertical Hall sensor comprises four cascaded Hall units with completely consistent structures. The lead metals are connected together two by two through the contact holes. A four-electrode vertical Hall sensor with symmetrical complete structure is formed.
The cascaded Hall unit is a three-electrode vertical Hall unit. The device comprises a P-type substrate, an N-well active region, a P-type covering layer, three contact holes of the active region and a P-type isolating ring.
The N-well active region is formed by N-type implantation on a P-type substrate.
And the active region contact holes are used as electrodes of each cascading unit of the vertical Hall sensor.
The P-type covering layer is formed by a P-type injection contact hole of the region outside the contact hole of the N-well active region.
The P-type isolation ring is formed by a P-type implantation contact hole surrounding the N-well active region.
The P-type isolation ring and the P-type cladding layer are connected to ground potential through a contact hole.
The P-type cladding layer not only improves sensitivity, but also improves noise resistance. The P-type isolation ring ensures the consistency of the substrate potential and the noise isolation. The low-offset vertical Hall sensor formed by the four cascade units realizes the vertical Hall sensor with high sensitivity, low noise and low offset.
The invention realizes a cascaded low-offset vertical Hall sensor. As shown in fig. 1 and 2, the hall voltage or current detection circuit comprises four cascaded vertical hall cells and four extraction electrodes a, B, C and D, wherein one pair of electrodes can be used as a voltage or current input electrode pair, and the other pair of electrodes is used as a hall voltage or hall current detection electrode. The four electrodes and the symmetrical structure thereof can perfectly adopt a four-phase rotating current method of the traditional horizontal Hall sensor to eliminate offset voltage.
The cascaded hall cells of each stage are all composed of a three-electrode vertical hall cell structure, as shown in fig. 1. The three electrodes were named C1, C2, C3, respectively.
The contact hole C3 of the first cascaded Hall unit is connected with the contact hole C1 of the second cascaded Hall unit, the contact hole C3 of the second cascaded Hall unit is connected with the contact hole C1 of the third cascaded Hall unit, the contact hole C3 of the third cascaded Hall unit is connected with the contact hole C1 of the fourth cascaded Hall unit, and meanwhile, the contact hole C3 of the fourth cascaded Hall unit is connected with the contact hole C1 of the first cascaded Hall unit.
The cascaded Hall units with the same structure comprise a P-type substrate, an N-well active region, a P-type covering layer, three contact holes of the active region and a P-type isolating ring. The N-well active region is formed by N-type ion implantation once, twice or more on a P-type substrate. The N trap is provided with three contact electrodes C1, C2 and C3 formed by N + injection. The three electrodes are consistent in shape and distance between the electrodes. The P-type covering layer is formed on the active region of the N trap by injecting P + and covers the region except the three N + electrodes. The edge distances of each of the remaining electrodes are also equal. The P-type isolation ring is formed by injecting P + and surrounds the whole N-well active region. The P-type covering layer and the P-type isolating ring are connected with zero potential, so that the sensitivity and the noise isolation performance of the Hall sensor are improved.
The cascade vertical Hall sensor structure is suitable for different process doping and injection conditions. In the schematic diagram 1, the size of the N-well active region, the sizes of the N + electrode, the P + cladding layer, the isolation ring, the distance between various injection boundaries, and the like can be optimized and subjected to finite element simulation according to specific process parameters to obtain the optimal matching of sensitivity and size design.
In a conventional horizontal hall sensor with a completely symmetrical structure, as shown in fig. 3, a cross hall is taken as an example, and an offset voltage is eliminated by adopting a four-phase rotating current method. In the case of "one phase", a voltage is applied between the electrodes C1C2, and a Hall output voltage is detected between the electrodes C2C 4; in the case of the "second phase", a voltage is applied between the electrodes of C2C4, the hall output voltage is detected between the electrodes of C3C1, and so on, and the hall voltage detection of the "third phase" and the "fourth phase" is completed in this order. Due to the completely symmetrical cross-shaped structure, the offset voltage can be basically eliminated after the four-phase output voltages are added by the method.
The traditional five-electrode vertical Hall sensor implementation structure is the most widely applied. As shown in fig. 4, although it is symmetrical in view of structure, it has an initial offset voltage lower than that of other structures. However, the boundary conditions of the two shorted outer electrodes C1 and the inner C2, C3, C4 are not consistent. This causes a mismatch in the well resistance value and the voltage modulated PN junction depletion layer. The bias conditions for the two sets of the four-term rotation method are not consistent. Therefore, in the process of using the conventional phase rotation current method of the horizontal hall, the offset voltage of each phase is not completely consistent, so that the offset error cannot be effectively eliminated.
As shown in FIG. 1, the cascade vertical Hall sensor has the structure that the peripheral conditions of four electrodes C1, C2, C3 and C4 are completely consistent. By keeping the interconnection impedance of the four cascade units equal, the current distribution path and the well resistance condition are also completely symmetrical in the four modes of the four-phase current rotation method. This is highly symmetrical as in a conventional horizontal hall sensor, so the raw offset voltage is reduced. After the circuit processing by the four-phase current rotation method, the residual offset voltage is greatly eliminated, and the whole residual offset voltage is reduced by ten times or even more than dozens of times compared with the traditional five-electrode structure. Under the same bias condition, for example, the hall bias current is 500uA, after the conventional five-electrode vertical hall sensor is subjected to a four-phase rotating current method, the residual offset voltage is about 1-5 millitesla (mT). The cascade vertical Hall sensor of the invention can reach dozens of micro-Tesla (mu T) after a four-phase rotating current method.
Optionally, the present invention can also be extended based on the core idea of the present invention. Two sets of four-cascade vertical hall sensors are used and the connection method as shown in fig. 5 is used. The metal connecting lines 1, 2, and 3 may use metal layers of different levels as connecting lines according to the wiring aspect.
Optionally, the present invention can also be extended based on the core idea of the present invention. Four sets of four-cascade vertical hall sensors are used and the connection method as shown in fig. 6 is used. The metal connecting lines 1, 2, and 3 may use metal layers of different levels as connecting lines according to the wiring aspect.
The cascade low-offset vertical Hall sensor system has symmetrical structure and relatively small offset voltage. The invention can adopt a four-phase rotating current method as the traditional horizontal Hall method to eliminate the offset of the device, the current path and the resistance of each phase are relatively matched and equivalent, and the advantage of the rotating current method can be effectively utilized to reduce the offset voltage to be less than one tenth of the offset voltage of the traditional five-electrode vertical Hall. The invention adopts the P-type covering layer and the P-type isolating ring, and improves the sensitivity and the noise isolation characteristic of the device through reasonable design and simulation of the size of the device.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (5)
1. The cascade low-offset vertical Hall sensor system is characterized by comprising four cascade Hall units, wherein the four cascade Hall units have completely consistent structures, the four cascade Hall units are connected together in pairs through contact hole lead wires to form a four-electrode vertical Hall sensor with a completely symmetrical structure, one pair of cascade Hall units are used as voltage or current input electrode pairs, and the other pair of cascade Hall units are used as Hall voltage or Hall current detection electrodes.
2. The cascaded low-offset vertical hall sensor system of claim 1, wherein the cascaded hall cell is a three-electrode vertical hall cell, and comprises a P-type substrate, an N-well active region, a P-type cover layer, a contact hole of the N-well active region, a P-type injection contact hole, and a P-type isolation ring, wherein the N-well active region is formed by N-type injection performed on the P-type substrate, the contact hole of the N-well active region is used as an electrode of the cascaded hall cell, the P-type cover layer is formed by a P-type injection contact hole, the P-type isolation ring is formed by a P-type injection contact hole surrounding the N-well active region, and the P-type isolation ring and the P-type cover layer are both connected to ground potential through the contact holes.
3. The cascaded low offset vertical hall sensor system of claim 1 wherein the four cascaded hall elements are interconnected to maintain equal interconnection impedance, symmetrical current distribution path and well resistance conditions.
4. The cascaded low-offset vertical hall sensor system of claim 1 further comprising two sets of four cascaded hall elements, a first set of cascaded hall elements and a second set of cascaded hall elements, wherein each set of hall elements are connected in series, the first hall element of the first set is connected to the third hall element of the second set, the second hall element of the first set is connected to the fourth hall element of the second set, the third hall element of the first set is connected to the first hall element of the second set, and the fourth hall element of the first set is connected to the second hall element of the second set.
5. The cascaded low-offset vertical hall sensor system of claim 1, wherein the device further comprises four cascaded groups of four hall elements, namely a first cascaded group of hall elements, a second cascaded group of hall elements, a third cascaded group of hall elements and a fourth cascaded group of hall elements, wherein each group of hall elements are connected in sequence, and the first hall element of each group of hall elements is connected with the fourth hall element of each group of hall elements; the first Hall unit of the first group is connected with the fourth Hall unit of the second group, the first Hall unit of the second group is connected with the fourth Hall unit of the third group, and the first Hall unit of the third group is connected with the fourth Hall unit of the fourth group; the second Hall unit of the first group is connected with the first Hall unit of the second group, the third Hall unit of the first group is connected with the second Hall unit of the second group and the first Hall unit of the third group, the fourth Hall unit of the first group is connected with the third Hall unit of the second group, the second Hall unit of the third group and the first Hall unit of the fourth group, the fourth Hall unit of the second group is connected with the third Hall unit of the third group and the second Hall unit of the fourth group, and the fourth Hall unit of the third group is connected with the third Hall unit of the fourth group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110828998.4A CN113466758A (en) | 2021-07-22 | 2021-07-22 | Cascade type low-offset vertical Hall sensor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110828998.4A CN113466758A (en) | 2021-07-22 | 2021-07-22 | Cascade type low-offset vertical Hall sensor system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113466758A true CN113466758A (en) | 2021-10-01 |
Family
ID=77881776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110828998.4A Pending CN113466758A (en) | 2021-07-22 | 2021-07-22 | Cascade type low-offset vertical Hall sensor system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113466758A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130021026A1 (en) * | 2011-07-21 | 2013-01-24 | Infineon Technologies Ag | Electronic device with ring-connected hall effect regions |
| CN104953024A (en) * | 2015-06-15 | 2015-09-30 | 南京邮电大学 | Symmetrical-structure low-disadjustment vertical hall device |
| US20150331068A1 (en) * | 2014-05-19 | 2015-11-19 | Micronas Gmbh | Hall sensor |
| US20150346289A1 (en) * | 2014-04-28 | 2015-12-03 | Infineon Technologies Ag | Hall Effect Sensor Arrangement |
| US20160097826A1 (en) * | 2014-10-03 | 2016-04-07 | Infineon Technologies Ag | Three 3-contact vertical hall sensor elements connected in a ring and related devices, systems, and methods |
| US20160139214A1 (en) * | 2014-11-18 | 2016-05-19 | Infineon Technologies Ag | Systems and arrangements of three-contact hall-effect devices and related methods |
-
2021
- 2021-07-22 CN CN202110828998.4A patent/CN113466758A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130021026A1 (en) * | 2011-07-21 | 2013-01-24 | Infineon Technologies Ag | Electronic device with ring-connected hall effect regions |
| US20150346289A1 (en) * | 2014-04-28 | 2015-12-03 | Infineon Technologies Ag | Hall Effect Sensor Arrangement |
| US20150331068A1 (en) * | 2014-05-19 | 2015-11-19 | Micronas Gmbh | Hall sensor |
| US20160097826A1 (en) * | 2014-10-03 | 2016-04-07 | Infineon Technologies Ag | Three 3-contact vertical hall sensor elements connected in a ring and related devices, systems, and methods |
| US20160139214A1 (en) * | 2014-11-18 | 2016-05-19 | Infineon Technologies Ag | Systems and arrangements of three-contact hall-effect devices and related methods |
| CN104953024A (en) * | 2015-06-15 | 2015-09-30 | 南京邮电大学 | Symmetrical-structure low-disadjustment vertical hall device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10809318B2 (en) | Semiconductor-based hall sensor | |
| US8085035B2 (en) | Hall element and magnetic sensor | |
| US10996287B2 (en) | Hall sensor devices and methods for operating the same | |
| CN103890971A (en) | Light detection device | |
| WO2015171331A1 (en) | Magnetic field sensors and associated methods with reduced offset and improved accuracy | |
| US9484525B2 (en) | Hall effect device | |
| CN107356885B (en) | Monolithic integrated two-dimensional magnetic field sensor and manufacturing process thereof | |
| CN103094253B (en) | A kind of grid oxide layer test structure | |
| CN106164691B (en) | Low offset and high sensitivity vertical hall effect sensor | |
| CN108279028A (en) | Photoelectricity measures the structure and preparation method thereof, photoelectric detection system | |
| CN112086524A (en) | Infrared detection device and preparation method | |
| WO2019205585A1 (en) | Polycrystalline silicon resistor | |
| US9279864B2 (en) | Sensor device and sensor arrangement | |
| CN113466758A (en) | Cascade type low-offset vertical Hall sensor system | |
| US7858425B2 (en) | Monolithic nuclear event detector and method of manufacture | |
| CN102509767A (en) | Complementary metal oxide semiconductor (CMOS) sensor with octagonal Hall disk structure and manufacturing method for CMOS sensor | |
| JP2012204616A (en) | Hall element and manufacturing method therefor, semiconductor device | |
| WO2017156921A1 (en) | Battery management chip circuit on the basis of silicon on insulator (soi) process | |
| CN107561459B (en) | Apparatus and method using multiple magnetic field sensitive devices | |
| CN117279481B (en) | High-performance vertical Hall device | |
| CN206697478U (en) | Wafer sort structure | |
| US8901923B2 (en) | Magnetic field sensor | |
| JP2019002781A (en) | Pressure sensor and manufacturing method thereof | |
| JP3275218B2 (en) | Semiconductor device and method for forming the same | |
| US20190285707A1 (en) | Multi-contact hall plate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |